2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 2003 Maciej W. Rozycki
6 * Copyright (C) 1994 - 2003 Ralf Baechle
7 * Copyright (C) 2001 MIPS Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/config.h>
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <linux/ptrace.h>
18 #include <linux/stddef.h>
23 #include <asm/mipsregs.h>
24 #include <asm/system.h>
27 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
28 * the implementation of the "wait" feature differs between CPU families. This
29 * points to the function that implements CPU specific wait.
30 * The wait instruction stops the pipeline and reduces the power consumption of
33 void (*cpu_wait
)(void) = NULL
;
35 static void r3081_wait(void)
37 unsigned long cfg
= read_c0_conf();
38 write_c0_conf(cfg
| R30XX_CONF_HALT
);
41 static void r39xx_wait(void)
43 unsigned long cfg
= read_c0_conf();
44 write_c0_conf(cfg
| TX39_CONF_HALT
);
47 static void r4k_wait(void)
49 __asm__(".set\tmips3\n\t"
54 /* The Au1xxx wait is available only if using 32khz counter or
55 * external timer source, but specifically not CP0 Counter. */
57 static void au1k_wait(void)
59 unsigned long addr
= 0;
60 /* using the wait instruction makes CP0 counter unusable */
61 __asm__("la %0,au1k_wait\n\t"
63 "cache 0x14,0(%0)\n\t"
64 "cache 0x14,32(%0)\n\t"
76 static inline void check_wait(void)
78 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
80 printk("Checking for 'wait' instruction... ");
84 cpu_wait
= r3081_wait
;
85 printk(" available.\n");
88 cpu_wait
= r39xx_wait
;
89 printk(" available.\n");
110 printk(" available.\n");
117 if (allow_au1k_wait
) {
118 cpu_wait
= au1k_wait
;
119 printk(" available.\n");
121 printk(" unavailable.\n");
124 printk(" unavailable.\n");
129 void __init
check_bugs32(void)
135 * Probe whether cpu has config register by trying to play with
136 * alternate cache bit and see whether it matters.
137 * It's used by cpu_probe to distinguish between R3000A and R3081.
139 static inline int cpu_has_confreg(void)
141 #ifdef CONFIG_CPU_R3000
142 extern unsigned long r3k_cache_size(unsigned long);
143 unsigned long size1
, size2
;
144 unsigned long cfg
= read_c0_conf();
146 size1
= r3k_cache_size(ST0_ISC
);
147 write_c0_conf(cfg
^ R30XX_CONF_AC
);
148 size2
= r3k_cache_size(ST0_ISC
);
150 return size1
!= size2
;
157 * Get the FPU Implementation/Revision.
159 static inline unsigned long cpu_get_fpu_id(void)
161 unsigned long tmp
, fpu_id
;
163 tmp
= read_c0_status();
165 fpu_id
= read_32bit_cp1_register(CP1_REVISION
);
166 write_c0_status(tmp
);
171 * Check the CPU has an FPU the official way.
173 static inline int __cpu_has_fpu(void)
175 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE
);
178 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
181 static inline void cpu_probe_legacy(struct cpuinfo_mips
*c
)
183 switch (c
->processor_id
& 0xff00) {
185 c
->cputype
= CPU_R2000
;
186 c
->isa_level
= MIPS_CPU_ISA_I
;
187 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_NOFPUEX
;
189 c
->options
|= MIPS_CPU_FPU
;
193 if ((c
->processor_id
& 0xff) == PRID_REV_R3000A
)
194 if (cpu_has_confreg())
195 c
->cputype
= CPU_R3081E
;
197 c
->cputype
= CPU_R3000A
;
199 c
->cputype
= CPU_R3000
;
200 c
->isa_level
= MIPS_CPU_ISA_I
;
201 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_NOFPUEX
;
203 c
->options
|= MIPS_CPU_FPU
;
207 if (read_c0_config() & CONF_SC
) {
208 if ((c
->processor_id
& 0xff) >= PRID_REV_R4400
)
209 c
->cputype
= CPU_R4400PC
;
211 c
->cputype
= CPU_R4000PC
;
213 if ((c
->processor_id
& 0xff) >= PRID_REV_R4400
)
214 c
->cputype
= CPU_R4400SC
;
216 c
->cputype
= CPU_R4000SC
;
219 c
->isa_level
= MIPS_CPU_ISA_III
;
220 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
221 MIPS_CPU_WATCH
| MIPS_CPU_VCE
|
225 case PRID_IMP_VR41XX
:
226 switch (c
->processor_id
& 0xf0) {
227 #ifndef CONFIG_VR4181
228 case PRID_REV_VR4111
:
229 c
->cputype
= CPU_VR4111
;
232 case PRID_REV_VR4181
:
233 c
->cputype
= CPU_VR4181
;
236 case PRID_REV_VR4121
:
237 c
->cputype
= CPU_VR4121
;
239 case PRID_REV_VR4122
:
240 if ((c
->processor_id
& 0xf) < 0x3)
241 c
->cputype
= CPU_VR4122
;
243 c
->cputype
= CPU_VR4181A
;
245 case PRID_REV_VR4130
:
246 if ((c
->processor_id
& 0xf) < 0x4)
247 c
->cputype
= CPU_VR4131
;
249 c
->cputype
= CPU_VR4133
;
252 printk(KERN_INFO
"Unexpected CPU of NEC VR4100 series\n");
253 c
->cputype
= CPU_VR41XX
;
256 c
->isa_level
= MIPS_CPU_ISA_III
;
257 c
->options
= R4K_OPTS
;
261 c
->cputype
= CPU_R4300
;
262 c
->isa_level
= MIPS_CPU_ISA_III
;
263 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
268 c
->cputype
= CPU_R4600
;
269 c
->isa_level
= MIPS_CPU_ISA_III
;
270 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_LLSC
;
276 * This processor doesn't have an MMU, so it's not
277 * "real easy" to run Linux on it. It is left purely
278 * for documentation. Commented out because it shares
279 * it's c0_prid id number with the TX3900.
281 c
->cputype
= CPU_R4650
;
282 c
->isa_level
= MIPS_CPU_ISA_III
;
283 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_LLSC
;
288 c
->isa_level
= MIPS_CPU_ISA_I
;
289 c
->options
= MIPS_CPU_TLB
;
291 if ((c
->processor_id
& 0xf0) == (PRID_REV_TX3927
& 0xf0)) {
292 c
->cputype
= CPU_TX3927
;
295 switch (c
->processor_id
& 0xff) {
296 case PRID_REV_TX3912
:
297 c
->cputype
= CPU_TX3912
;
300 case PRID_REV_TX3922
:
301 c
->cputype
= CPU_TX3922
;
305 c
->cputype
= CPU_UNKNOWN
;
311 c
->cputype
= CPU_R4700
;
312 c
->isa_level
= MIPS_CPU_ISA_III
;
313 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
318 c
->cputype
= CPU_TX49XX
;
319 c
->isa_level
= MIPS_CPU_ISA_III
;
320 c
->options
= R4K_OPTS
| MIPS_CPU_LLSC
;
321 if (!(c
->processor_id
& 0x08))
322 c
->options
|= MIPS_CPU_FPU
| MIPS_CPU_32FPR
;
326 c
->cputype
= CPU_R5000
;
327 c
->isa_level
= MIPS_CPU_ISA_IV
;
328 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
333 c
->cputype
= CPU_R5432
;
334 c
->isa_level
= MIPS_CPU_ISA_IV
;
335 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
336 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
340 c
->cputype
= CPU_R5500
;
341 c
->isa_level
= MIPS_CPU_ISA_IV
;
342 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
343 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
346 case PRID_IMP_NEVADA
:
347 c
->cputype
= CPU_NEVADA
;
348 c
->isa_level
= MIPS_CPU_ISA_IV
;
349 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
350 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
;
354 c
->cputype
= CPU_R6000
;
355 c
->isa_level
= MIPS_CPU_ISA_II
;
356 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
360 case PRID_IMP_R6000A
:
361 c
->cputype
= CPU_R6000A
;
362 c
->isa_level
= MIPS_CPU_ISA_II
;
363 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
367 case PRID_IMP_RM7000
:
368 c
->cputype
= CPU_RM7000
;
369 c
->isa_level
= MIPS_CPU_ISA_IV
;
370 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
373 * Undocumented RM7000: Bit 29 in the info register of
374 * the RM7000 v2.0 indicates if the TLB has 48 or 64
377 * 29 1 => 64 entry JTLB
380 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
382 case PRID_IMP_RM9000
:
383 c
->cputype
= CPU_RM9000
;
384 c
->isa_level
= MIPS_CPU_ISA_IV
;
385 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
388 * Bit 29 in the info register of the RM9000
389 * indicates if the TLB has 48 or 64 entries.
391 * 29 1 => 64 entry JTLB
394 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
397 c
->cputype
= CPU_R8000
;
398 c
->isa_level
= MIPS_CPU_ISA_IV
;
399 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4KEX
|
400 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
402 c
->tlbsize
= 384; /* has weird TLB: 3-way x 128 */
404 case PRID_IMP_R10000
:
405 c
->cputype
= CPU_R10000
;
406 c
->isa_level
= MIPS_CPU_ISA_IV
;
407 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4KEX
|
408 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
409 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
413 case PRID_IMP_R12000
:
414 c
->cputype
= CPU_R12000
;
415 c
->isa_level
= MIPS_CPU_ISA_IV
;
416 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4KEX
|
417 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
418 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
425 static inline void decode_config1(struct cpuinfo_mips
*c
)
427 unsigned long config0
= read_c0_config();
428 unsigned long config1
;
430 if ((config0
& (1 << 31)) == 0)
431 return; /* actually wort a panic() */
433 /* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */
434 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4KEX
|
435 MIPS_CPU_4KTLB
| MIPS_CPU_COUNTER
| MIPS_CPU_DIVEC
|
436 MIPS_CPU_LLSC
| MIPS_CPU_MCHECK
;
437 config1
= read_c0_config1();
438 if (config1
& (1 << 3))
439 c
->options
|= MIPS_CPU_WATCH
;
440 if (config1
& (1 << 2))
441 c
->options
|= MIPS_CPU_MIPS16
;
442 if (config1
& (1 << 1))
443 c
->options
|= MIPS_CPU_EJTAG
;
445 c
->options
|= MIPS_CPU_FPU
;
446 c
->options
|= MIPS_CPU_32FPR
;
448 c
->scache
.flags
= MIPS_CACHE_NOT_PRESENT
;
450 c
->tlbsize
= ((config1
>> 25) & 0x3f) + 1;
453 static inline void cpu_probe_mips(struct cpuinfo_mips
*c
)
456 switch (c
->processor_id
& 0xff00) {
458 c
->cputype
= CPU_4KC
;
459 c
->isa_level
= MIPS_CPU_ISA_M32
;
462 c
->cputype
= CPU_4KEC
;
463 c
->isa_level
= MIPS_CPU_ISA_M32
;
466 c
->cputype
= CPU_4KSC
;
467 c
->isa_level
= MIPS_CPU_ISA_M32
;
470 c
->cputype
= CPU_5KC
;
471 c
->isa_level
= MIPS_CPU_ISA_M64
;
474 c
->cputype
= CPU_20KC
;
475 c
->isa_level
= MIPS_CPU_ISA_M64
;
478 c
->cputype
= CPU_24K
;
479 c
->isa_level
= MIPS_CPU_ISA_M32
;
482 c
->cputype
= CPU_25KF
;
483 c
->isa_level
= MIPS_CPU_ISA_M64
;
484 /* Probe for L2 cache */
485 c
->scache
.flags
&= ~MIPS_CACHE_NOT_PRESENT
;
490 static inline void cpu_probe_alchemy(struct cpuinfo_mips
*c
)
493 switch (c
->processor_id
& 0xff00) {
494 case PRID_IMP_AU1_REV1
:
495 case PRID_IMP_AU1_REV2
:
496 switch ((c
->processor_id
>> 24) & 0xff) {
498 c
->cputype
= CPU_AU1000
;
501 c
->cputype
= CPU_AU1500
;
504 c
->cputype
= CPU_AU1100
;
507 c
->cputype
= CPU_AU1550
;
510 c
->cputype
= CPU_AU1200
;
513 panic("Unknown Au Core!");
516 c
->isa_level
= MIPS_CPU_ISA_M32
;
521 static inline void cpu_probe_sibyte(struct cpuinfo_mips
*c
)
524 switch (c
->processor_id
& 0xff00) {
526 c
->cputype
= CPU_SB1
;
527 c
->isa_level
= MIPS_CPU_ISA_M64
;
528 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4KEX
|
529 MIPS_CPU_COUNTER
| MIPS_CPU_DIVEC
|
530 MIPS_CPU_MCHECK
| MIPS_CPU_EJTAG
|
531 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
532 #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
533 /* FPU in pass1 is known to have issues. */
534 c
->options
|= MIPS_CPU_FPU
| MIPS_CPU_32FPR
;
540 static inline void cpu_probe_sandcraft(struct cpuinfo_mips
*c
)
543 switch (c
->processor_id
& 0xff00) {
544 case PRID_IMP_SR71000
:
545 c
->cputype
= CPU_SR71000
;
546 c
->isa_level
= MIPS_CPU_ISA_M64
;
547 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4KEX
|
548 MIPS_CPU_4KTLB
| MIPS_CPU_FPU
|
549 MIPS_CPU_COUNTER
| MIPS_CPU_MCHECK
;
556 __init
void cpu_probe(void)
558 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
560 c
->processor_id
= PRID_IMP_UNKNOWN
;
561 c
->fpu_id
= FPIR_IMP_NONE
;
562 c
->cputype
= CPU_UNKNOWN
;
564 c
->processor_id
= read_c0_prid();
565 switch (c
->processor_id
& 0xff0000) {
566 case PRID_COMP_LEGACY
:
572 case PRID_COMP_ALCHEMY
:
573 cpu_probe_alchemy(c
);
575 case PRID_COMP_SIBYTE
:
579 case PRID_COMP_SANDCRAFT
:
580 cpu_probe_sandcraft(c
);
583 c
->cputype
= CPU_UNKNOWN
;
585 if (c
->options
& MIPS_CPU_FPU
)
586 c
->fpu_id
= cpu_get_fpu_id();
589 __init
void cpu_report(void)
591 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
593 printk("CPU revision is: %08x\n", c
->processor_id
);
594 if (c
->options
& MIPS_CPU_FPU
)
595 printk("FPU revision is: %08x\n", c
->fpu_id
);