arch/mips/au1000/common/time.c

   1 /*
   2  *
   3  * Copyright (C) 2001 MontaVista Software, ppopov@mvista.com
   4  * Copied and modified Carsten Langgaard's time.c
   5  *
   6  * Carsten Langgaard, carstenl@mips.com
   7  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
   8  *
   9  * ########################################################################
  10  *
  11  *  This program is free software; you can distribute it and/or modify it
  12  *  under the terms of the GNU General Public License (Version 2) as
  13  *  published by the Free Software Foundation.
  14  *
  15  *  This program is distributed in the hope it will be useful, but WITHOUT
  16  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  18  *  for more details.
  19  *
  20  *  You should have received a copy of the GNU General Public License along
  21  *  with this program; if not, write to the Free Software Foundation, Inc.,
  22  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  23  *
  24  * ########################################################################
  25  *
  26  * Setting up the clock on the MIPS boards.
  27  *
  28  * Update.  Always configure the kernel with CONFIG_NEW_TIME_C.  This
  29  * will use the user interface gettimeofday() functions from the
  30  * arch/mips/kernel/time.c, and we provide the clock interrupt processing
  31  * and the timer offset compute functions.  If CONFIG_PM is selected,
  32  * we also ensure the 32KHz timer is available.   -- Dan
  33  */
  34
  35 #include <linux/types.h>
  36 #include <linux/config.h>
  37 #include <linux/init.h>
  38 #include <linux/kernel_stat.h>
  39 #include <linux/sched.h>
  40 #include <linux/spinlock.h>
  41 #include <linux/hardirq.h>
  42
  43 #include <asm/compiler.h>
  44 #include <asm/mipsregs.h>
  45 #include <asm/ptrace.h>
  46 #include <asm/time.h>
  47 #include <asm/div64.h>
  48 #include <asm/mach-au1x00/au1000.h>
  49
  50 #include <linux/mc146818rtc.h>
  51 #include <linux/timex.h>
  52
  53 extern void do_softirq(void);
  54 extern volatile unsigned long wall_jiffies;
  55 unsigned long missed_heart_beats = 0;
  56
  57 static unsigned long r4k_offset; /* Amount to increment compare reg each time */
  58 static unsigned long r4k_cur;    /* What counter should be at next timer irq */
  59 int     no_au1xxx_32khz;
  60 extern int allow_au1k_wait; /* default off for CP0 Counter */
  61
  62 /* Cycle counter value at the previous timer interrupt.. */
  63 static unsigned int timerhi = 0, timerlo = 0;
  64
  65 #ifdef CONFIG_PM
  66 #define MATCH20_INC 328
  67 extern void startup_match20_interrupt(void (*handler)(int, void *, struct pt_regs *));
  68 static unsigned long last_pc0, last_match20;
  69 #endif
  70
  71 static DEFINE_SPINLOCK(time_lock);
  72
  73 static inline void ack_r4ktimer(unsigned long newval)
  74 {
  75         write_c0_compare(newval);
  76 }
  77
  78 /*
  79  * There are a lot of conceptually broken versions of the MIPS timer interrupt
  80  * handler floating around.  This one is rather different, but the algorithm
  81  * is provably more robust.
  82  */
  83 unsigned long wtimer;
  84 void mips_timer_interrupt(struct pt_regs *regs)
  85 {
  86         int irq = 63;
  87         unsigned long count;
  88
  89         irq_enter();
  90         kstat_this_cpu.irqs[irq]++;
  91
  92         if (r4k_offset == 0)
  93                 goto null;
  94
  95         do {
  96                 count = read_c0_count();
  97                 timerhi += (count < timerlo);   /* Wrap around */
  98                 timerlo = count;
  99
 100                 kstat_this_cpu.irqs[irq]++;
 101                 do_timer(regs);
 102 #ifndef CONFIG_SMP
 103                 update_process_times(user_mode(regs));
 104 #endif
 105                 r4k_cur += r4k_offset;
 106                 ack_r4ktimer(r4k_cur);
 107
 108         } while (((unsigned long)read_c0_count()
 109                  - r4k_cur) < 0x7fffffff);
 110
 111         irq_exit();
 112         return;
 113
 114 null:
 115         ack_r4ktimer(0);
 116 }
 117
 118 #ifdef CONFIG_PM
 119 void counter0_irq(int irq, void *dev_id, struct pt_regs *regs)
 120 {
 121         unsigned long pc0;
 122         int time_elapsed;
 123         static int jiffie_drift = 0;
 124
 125         kstat.irqs[0][irq]++;
 126         if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
 127                 /* should never happen! */
 128                 printk(KERN_WARNING "counter 0 w status eror\n");
 129                 return;
 130         }
 131
 132         pc0 = au_readl(SYS_TOYREAD);
 133         if (pc0 < last_match20) {
 134                 /* counter overflowed */
 135                 time_elapsed = (0xffffffff - last_match20) + pc0;
 136         }
 137         else {
 138                 time_elapsed = pc0 - last_match20;
 139         }
 140
 141         while (time_elapsed > 0) {
 142                 do_timer(regs);
 143 #ifndef CONFIG_SMP
 144                 update_process_times(user_mode(regs));
 145 #endif
 146                 time_elapsed -= MATCH20_INC;
 147                 last_match20 += MATCH20_INC;
 148                 jiffie_drift++;
 149         }
 150
 151         last_pc0 = pc0;
 152         au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
 153         au_sync();
 154
 155         /* our counter ticks at 10.009765625 ms/tick, we we're running
 156          * almost 10uS too slow per tick.
 157          */
 158
 159         if (jiffie_drift >= 999) {
 160                 jiffie_drift -= 999;
 161                 do_timer(regs); /* increment jiffies by one */
 162 #ifndef CONFIG_SMP
 163                 update_process_times(user_mode(regs));
 164 #endif
 165         }
 166 }
 167
 168 /* When we wakeup from sleep, we have to "catch up" on all of the
 169  * timer ticks we have missed.
 170  */
 171 void
 172 wakeup_counter0_adjust(void)
 173 {
 174         unsigned long pc0;
 175         int time_elapsed;
 176
 177         pc0 = au_readl(SYS_TOYREAD);
 178         if (pc0 < last_match20) {
 179                 /* counter overflowed */
 180                 time_elapsed = (0xffffffff - last_match20) + pc0;
 181         }
 182         else {
 183                 time_elapsed = pc0 - last_match20;
 184         }
 185
 186         while (time_elapsed > 0) {
 187                 time_elapsed -= MATCH20_INC;
 188                 last_match20 += MATCH20_INC;
 189         }
 190
 191         last_pc0 = pc0;
 192         au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
 193         au_sync();
 194
 195 }
 196
 197 /* This is just for debugging to set the timer for a sleep delay.
 198 */
 199 void
 200 wakeup_counter0_set(int ticks)
 201 {
 202         unsigned long pc0;
 203
 204         pc0 = au_readl(SYS_TOYREAD);
 205         last_pc0 = pc0;
 206         au_writel(last_match20 + (MATCH20_INC * ticks), SYS_TOYMATCH2);
 207         au_sync();
 208 }
 209 #endif
 210
 211 /* I haven't found anyone that doesn't use a 12 MHz source clock,
 212  * but just in case.....
 213  */
 214 #ifdef CONFIG_AU1000_SRC_CLK
 215 #define AU1000_SRC_CLK  CONFIG_AU1000_SRC_CLK
 216 #else
 217 #define AU1000_SRC_CLK  12000000
 218 #endif
 219
 220 /*
 221  * We read the real processor speed from the PLL.  This is important
 222  * because it is more accurate than computing it from the 32KHz
 223  * counter, if it exists.  If we don't have an accurate processor
 224  * speed, all of the peripherals that derive their clocks based on
 225  * this advertised speed will introduce error and sometimes not work
 226  * properly.  This function is futher convoluted to still allow configurations
 227  * to do that in case they have really, really old silicon with a
 228  * write-only PLL register, that we need the 32KHz when power management
 229  * "wait" is enabled, and we need to detect if the 32KHz isn't present
 230  * but requested......got it? :-)               -- Dan
 231  */
 232 unsigned long cal_r4koff(void)
 233 {
 234         unsigned long count;
 235         unsigned long cpu_speed;
 236         unsigned long flags;
 237         unsigned long counter;
 238
 239         spin_lock_irqsave(&time_lock, flags);
 240
 241         /* Power management cares if we don't have a 32KHz counter.
 242         */
 243         no_au1xxx_32khz = 0;
 244         counter = au_readl(SYS_COUNTER_CNTRL);
 245         if (counter & SYS_CNTRL_E0) {
 246                 int trim_divide = 16;
 247
 248                 au_writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL);
 249
 250                 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
 251                 /* RTC now ticks at 32.768/16 kHz */
 252                 au_writel(trim_divide-1, SYS_RTCTRIM);
 253                 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
 254
 255                 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
 256                 au_writel (0, SYS_TOYWRITE);
 257                 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
 258
 259 #if defined(CONFIG_AU1000_USE32K)
 260                 {
 261                         unsigned long start, end;
 262
 263                         start = au_readl(SYS_RTCREAD);
 264                         start += 2;
 265                         /* wait for the beginning of a new tick
 266                         */
 267                         while (au_readl(SYS_RTCREAD) < start);
 268
 269                         /* Start r4k counter.
 270                         */
 271                         write_c0_count(0);
 272
 273                         /* Wait 0.5 seconds.
 274                         */
 275                         end = start + (32768 / trim_divide)/2;
 276
 277                         while (end > au_readl(SYS_RTCREAD));
 278
 279                         count = read_c0_count();
 280                         cpu_speed = count * 2;
 281                 }
 282 #else
 283                 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
 284                         AU1000_SRC_CLK;
 285                 count = cpu_speed / 2;
 286 #endif
 287         }
 288         else {
 289                 /* The 32KHz oscillator isn't running, so assume there
 290                  * isn't one and grab the processor speed from the PLL.
 291                  * NOTE: some old silicon doesn't allow reading the PLL.
 292                  */
 293                 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
 294                 count = cpu_speed / 2;
 295                 no_au1xxx_32khz = 1;
 296         }
 297         mips_hpt_frequency = count;
 298         // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
 299         set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
 300         spin_unlock_irqrestore(&time_lock, flags);
 301         return (cpu_speed / HZ);
 302 }
 303
 304 /* This is for machines which generate the exact clock. */
 305 #define USECS_PER_JIFFY (1000000/HZ)
 306 #define USECS_PER_JIFFY_FRAC (0x100000000LL*1000000/HZ&0xffffffff)
 307
 308 static unsigned long
 309 div64_32(unsigned long v1, unsigned long v2, unsigned long v3)
 310 {
 311         unsigned long r0;
 312         do_div64_32(r0, v1, v2, v3);
 313         return r0;
 314 }
 315
 316 static unsigned long do_fast_cp0_gettimeoffset(void)
 317 {
 318         u32 count;
 319         unsigned long res, tmp;
 320         unsigned long r0;
 321
 322         /* Last jiffy when do_fast_gettimeoffset() was called. */
 323         static unsigned long last_jiffies=0;
 324         unsigned long quotient;
 325
 326         /*
 327          * Cached "1/(clocks per usec)*2^32" value.
 328          * It has to be recalculated once each jiffy.
 329          */
 330         static unsigned long cached_quotient=0;
 331
 332         tmp = jiffies;
 333
 334         quotient = cached_quotient;
 335
 336         if (tmp && last_jiffies != tmp) {
 337                 last_jiffies = tmp;
 338                 if (last_jiffies != 0) {
 339                         r0 = div64_32(timerhi, timerlo, tmp);
 340                         quotient = div64_32(USECS_PER_JIFFY, USECS_PER_JIFFY_FRAC, r0);
 341                         cached_quotient = quotient;
 342                 }
 343         }
 344
 345         /* Get last timer tick in absolute kernel time */
 346         count = read_c0_count();
 347
 348         /* .. relative to previous jiffy (32 bits is enough) */
 349         count -= timerlo;
 350
 351         __asm__("multu\t%1,%2\n\t"
 352                 "mfhi\t%0"
 353                 : "=r" (res)
 354                 : "r" (count), "r" (quotient)
 355                 : "hi", "lo", GCC_REG_ACCUM);
 356
 357         /*
 358          * Due to possible jiffies inconsistencies, we need to check
 359          * the result so that we'll get a timer that is monotonic.
 360          */
 361         if (res >= USECS_PER_JIFFY)
 362                 res = USECS_PER_JIFFY-1;
 363
 364         return res;
 365 }
 366
 367 #ifdef CONFIG_PM
 368 static unsigned long do_fast_pm_gettimeoffset(void)
 369 {
 370         unsigned long pc0;
 371         unsigned long offset;
 372
 373         pc0 = au_readl(SYS_TOYREAD);
 374         au_sync();
 375         offset = pc0 - last_pc0;
 376         if (offset > 2*MATCH20_INC) {
 377                 printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n",
 378                                 (unsigned)offset, (unsigned)last_pc0,
 379                                 (unsigned)last_match20, (unsigned)pc0);
 380         }
 381         offset = (unsigned long)((offset * 305) / 10);
 382         return offset;
 383 }
 384 #endif
 385
 386 void au1xxx_timer_setup(struct irqaction *irq)
 387 {
 388         unsigned int est_freq;
 389         extern unsigned long (*do_gettimeoffset)(void);
 390
 391         printk("calculating r4koff... ");
 392         r4k_offset = cal_r4koff();
 393         printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
 394
 395         //est_freq = 2*r4k_offset*HZ;
 396         est_freq = r4k_offset*HZ;
 397         est_freq += 5000;    /* round */
 398         est_freq -= est_freq%10000;
 399         printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
 400                (est_freq%1000000)*100/1000000);
 401         set_au1x00_speed(est_freq);
 402         set_au1x00_lcd_clock(); // program the LCD clock
 403
 404         r4k_cur = (read_c0_count() + r4k_offset);
 405         write_c0_compare(r4k_cur);
 406
 407 #ifdef CONFIG_PM
 408         /*
 409          * setup counter 0, since it keeps ticking after a
 410          * 'wait' instruction has been executed. The CP0 timer and
 411          * counter 1 do NOT continue running after 'wait'
 412          *
 413          * It's too early to call request_irq() here, so we handle
 414          * counter 0 interrupt as a special irq and it doesn't show
 415          * up under /proc/interrupts.
 416          *
 417          * Check to ensure we really have a 32KHz oscillator before
 418          * we do this.
 419          */
 420         if (no_au1xxx_32khz) {
 421                 unsigned int c0_status;
 422
 423                 printk("WARNING: no 32KHz clock found.\n");
 424                 do_gettimeoffset = do_fast_cp0_gettimeoffset;
 425
 426                 /* Ensure we get CPO_COUNTER interrupts.
 427                 */
 428                 c0_status = read_c0_status();
 429                 c0_status |= IE_IRQ5;
 430                 write_c0_status(c0_status);
 431         }
 432         else {
 433                 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
 434                 au_writel(0, SYS_TOYWRITE);
 435                 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
 436
 437                 au_writel(au_readl(SYS_WAKEMSK) | (1<<8), SYS_WAKEMSK);
 438                 au_writel(~0, SYS_WAKESRC);
 439                 au_sync();
 440                 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
 441
 442                 /* setup match20 to interrupt once every 10ms */
 443                 last_pc0 = last_match20 = au_readl(SYS_TOYREAD);
 444                 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
 445                 au_sync();
 446                 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
 447                 startup_match20_interrupt(counter0_irq);
 448
 449                 do_gettimeoffset = do_fast_pm_gettimeoffset;
 450
 451                 /* We can use the real 'wait' instruction.
 452                 */
 453                 allow_au1k_wait = 1;
 454         }
 455
 456 #else
 457         /* We have to do this here instead of in timer_init because
 458          * the generic code in arch/mips/kernel/time.c will write
 459          * over our function pointer.
 460          */
 461         do_gettimeoffset = do_fast_cp0_gettimeoffset;
 462 #endif
 463 }
 464
 465 void __init au1xxx_time_init(void)
 466 {
 467 }