arch/mips64/mm/sc-r5k.c

   1 /*
   2  * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org),
   3  * derived from r4xx0.c by David S. Miller (dm@engr.sgi.com).
   4  */
   5 #include <linux/init.h>
   6 #include <linux/kernel.h>
   7 #include <linux/sched.h>
   8 #include <linux/mm.h>
   9
  10 #include <asm/mipsregs.h>
  11 #include <asm/bcache.h>
  12 #include <asm/cacheops.h>
  13 #include <asm/page.h>
  14 #include <asm/pgtable.h>
  15 #include <asm/system.h>
  16 #include <asm/mmu_context.h>
  17
  18 /* Secondary cache size in bytes, if present.  */
  19 static unsigned long scache_size;
  20
  21 #define SC_LINE 32
  22 #define SC_PAGE (128*SC_LINE)
  23
  24 #define cache_op(base,op)                   \
  25 __asm__ __volatile__("                          \
  26                 .set noreorder;                 \
  27                 .set mips3;                     \
  28                 cache %1, (%0);                 \
  29                 .set mips0;                     \
  30                 .set reorder"                   \
  31                 :                               \
  32                 : "r" (base),                   \
  33                   "i" (op));
  34
  35 static inline void blast_r5000_scache(void)
  36 {
  37         unsigned long start = KSEG0;
  38         unsigned long end = KSEG0 + scache_size;
  39
  40         while(start < end) {
  41                 cache_op(start, R5K_Page_Invalidate_S);
  42                 start += SC_PAGE;
  43         }
  44 }
  45
  46 static void r5k_dma_cache_inv_sc(unsigned long addr, unsigned long size)
  47 {
  48         unsigned long end, a;
  49
  50         if (size >= scache_size) {
  51                 blast_r5000_scache();
  52                 return;
  53         }
  54
  55         /* On the R5000 secondary cache we cannot
  56          * invalidate less than a page at a time.
  57          * The secondary cache is physically indexed, write-through.
  58          */
  59         a = addr & ~(SC_PAGE - 1);
  60         end = (addr + size - 1) & ~(SC_PAGE - 1);
  61         while (a <= end) {
  62                 cache_op(a, R5K_Page_Invalidate_S);
  63                 a += SC_PAGE;
  64         }
  65 }
  66
  67 static void r5k_sc_enable(void)
  68 {
  69         unsigned long flags;
  70
  71         local_irq_save(flags);
  72         change_c0_config(R5K_CONF_SE, R5K_CONF_SE);
  73         blast_r5000_scache();
  74         local_irq_restore(flags);
  75 }
  76
  77 static void r5k_sc_disable(void)
  78 {
  79         unsigned long flags;
  80
  81         local_irq_save(flags);
  82         blast_r5000_scache();
  83         change_c0_config(R5K_CONF_SE, 0);
  84         local_irq_restore(flags);
  85 }
  86
  87 static inline int __init r5k_sc_probe(void)
  88 {
  89         unsigned long config = read_c0_config();
  90
  91         if (config & CONF_SC)
  92                 return(0);
  93
  94         scache_size = (512 * 1024) << ((config & R5K_CONF_SS) >> 20);
  95
  96         printk("R5000 SCACHE size %ldkB, linesize 32 bytes.\n",
  97                         scache_size >> 10);
  98
  99         return 1;
 100 }
 101
 102 static struct bcache_ops r5k_sc_ops = {
 103         .bc_enable = r5k_sc_enable,
 104         .bc_disable = r5k_sc_disable,
 105         .bc_wback_inv = r5k_dma_cache_inv_sc,
 106         .bc_inv = r5k_dma_cache_inv_sc
 107 };
 108
 109 void __init r5k_sc_init(void)
 110 {
 111         if (r5k_sc_probe()) {
 112                 r5k_sc_enable();
 113                 bcops = &r5k_sc_ops;
 114         }
 115 }