arch/mips/mm/tlb-sb1.c

   1 /*
   2  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
   3  * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org)
   4  * Copyright (C) 2000, 2001 Broadcom Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  19  */
  20 #include <linux/config.h>
  21 #include <asm/mmu_context.h>
  22 #include <asm/bootinfo.h>
  23 #include <asm/cpu.h>
  24
  25 extern char except_vec0_sb1[];
  26
  27 /* Dump the current entry* and pagemask registers */
  28 static inline void dump_cur_tlb_regs(void)
  29 {
  30         unsigned int entryhihi, entryhilo, entrylo0hi, entrylo0lo, entrylo1hi;
  31         unsigned int entrylo1lo, pagemask;
  32
  33         __asm__ __volatile__ (
  34                 ".set push             \n"
  35                 ".set noreorder        \n"
  36                 ".set mips64           \n"
  37                 ".set noat             \n"
  38                 "     dmfc0  $1, $10   \n"
  39                 "     dsrl32 %0, $1, 0 \n"
  40                 "     sll    %1, $1, 0 \n"
  41                 "     dmfc0  $1, $2    \n"
  42                 "     dsrl32 %2, $1, 0 \n"
  43                 "     sll    %3, $1, 0 \n"
  44                 "     dmfc0  $1, $3    \n"
  45                 "     dsrl32 %4, $1, 0 \n"
  46                 "     sll    %5, $1, 0 \n"
  47                 "     mfc0   %6, $5    \n"
  48                 ".set pop              \n"
  49                 : "=r" (entryhihi), "=r" (entryhilo),
  50                   "=r" (entrylo0hi), "=r" (entrylo0lo),
  51                   "=r" (entrylo1hi), "=r" (entrylo1lo),
  52                   "=r" (pagemask));
  53
  54         printk("%08X%08X %08X%08X %08X%08X %08X",
  55                entryhihi, entryhilo,
  56                entrylo0hi, entrylo0lo,
  57                entrylo1hi, entrylo1lo,
  58                pagemask);
  59 }
  60
  61 void sb1_dump_tlb(void)
  62 {
  63         unsigned long old_ctx;
  64         unsigned long flags;
  65         int entry;
  66         local_irq_save(flags);
  67         old_ctx = read_c0_entryhi();
  68         printk("Current TLB registers state:\n"
  69                "      EntryHi       EntryLo0          EntryLo1     PageMask  Index\n"
  70                "--------------------------------------------------------------------\n");
  71         dump_cur_tlb_regs();
  72         printk(" %08X\n", read_c0_index());
  73         printk("\n\nFull TLB Dump:\n"
  74                "Idx      EntryHi       EntryLo0          EntryLo1     PageMask\n"
  75                "--------------------------------------------------------------\n");
  76         for (entry = 0; entry < current_cpu_data.tlbsize; entry++) {
  77                 write_c0_index(entry);
  78                 printk("\n%02i ", entry);
  79                 tlb_read();
  80                 dump_cur_tlb_regs();
  81         }
  82         printk("\n");
  83         write_c0_entryhi(old_ctx);
  84         local_irq_restore(flags);
  85 }
  86
  87 void local_flush_tlb_all(void)
  88 {
  89         unsigned long flags;
  90         unsigned long old_ctx;
  91         int entry;
  92
  93         local_irq_save(flags);
  94         /* Save old context and create impossible VPN2 value */
  95         old_ctx = read_c0_entryhi() & ASID_MASK;
  96         write_c0_entrylo0(0);
  97         write_c0_entrylo1(0);
  98         for (entry = 0; entry < current_cpu_data.tlbsize; entry++) {
  99                 write_c0_entryhi(KSEG0 + (PAGE_SIZE << 1) * entry);
 100                 write_c0_index(entry);
 101                 tlb_write_indexed();
 102         }
 103         write_c0_entryhi(old_ctx);
 104         local_irq_restore(flags);
 105 }
 106
 107
 108 /*
 109  * Use a bogus region of memory (starting at 0) to sanitize the TLB's.
 110  * Use increments of the maximum page size (16MB), and check for duplicate
 111  * entries before doing a given write.  Then, when we're safe from collisions
 112  * with the firmware, go back and give all the entries invalid addresses with
 113  * the normal flush routine.
 114  */
 115 void sb1_sanitize_tlb(void)
 116 {
 117         int entry;
 118         long addr = 0;
 119
 120         long inc = 1<<24;  /* 16MB */
 121         /* Save old context and create impossible VPN2 value */
 122         write_c0_entrylo0(0);
 123         write_c0_entrylo1(0);
 124         for (entry = 0; entry < current_cpu_data.tlbsize; entry++) {
 125                 do {
 126                         addr += inc;
 127                         write_c0_entryhi(addr);
 128                         tlb_probe();
 129                 } while ((int)(read_c0_index()) >= 0);
 130                 write_c0_index(entry);
 131                 tlb_write_indexed();
 132         }
 133         /* Now that we know we're safe from collisions, we can safely flush
 134            the TLB with the "normal" routine. */
 135         local_flush_tlb_all();
 136 }
 137
 138 void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 139                       unsigned long end)
 140 {
 141         struct mm_struct *mm = vma->vm_mm;
 142         unsigned long flags;
 143         int cpu;
 144
 145         local_irq_save(flags);
 146         cpu = smp_processor_id();
 147         if (cpu_context(cpu, mm) != 0) {
 148                 int size;
 149                 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
 150                 size = (size + 1) >> 1;
 151                 if (size <= (current_cpu_data.tlbsize/2)) {
 152                         int oldpid = read_c0_entryhi() & ASID_MASK;
 153                         int newpid = cpu_asid(cpu, mm);
 154
 155                         start &= (PAGE_MASK << 1);
 156                         end += ((PAGE_SIZE << 1) - 1);
 157                         end &= (PAGE_MASK << 1);
 158                         while (start < end) {
 159                                 int idx;
 160
 161                                 write_c0_entryhi(start | newpid);
 162                                 start += (PAGE_SIZE << 1);
 163                                 tlb_probe();
 164                                 idx = read_c0_index();
 165                                 write_c0_entrylo0(0);
 166                                 write_c0_entrylo1(0);
 167                                 write_c0_entryhi(KSEG0 + (idx << (PAGE_SHIFT+1)));
 168                                 if (idx < 0)
 169                                         continue;
 170                                 tlb_write_indexed();
 171                         }
 172                         write_c0_entryhi(oldpid);
 173                 } else {
 174                         drop_mmu_context(mm, cpu);
 175                 }
 176         }
 177         local_irq_restore(flags);
 178 }
 179
 180 void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
 181 {
 182         unsigned long flags;
 183         int size;
 184
 185         size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
 186         size = (size + 1) >> 1;
 187
 188         local_irq_save(flags);
 189         if (size <= (current_cpu_data.tlbsize/2)) {
 190                 int pid = read_c0_entryhi();
 191
 192                 start &= (PAGE_MASK << 1);
 193                 end += ((PAGE_SIZE << 1) - 1);
 194                 end &= (PAGE_MASK << 1);
 195
 196                 while (start < end) {
 197                         int idx;
 198
 199                         write_c0_entryhi(start);
 200                         start += (PAGE_SIZE << 1);
 201                         tlb_probe();
 202                         idx = read_c0_index();
 203                         write_c0_entrylo0(0);
 204                         write_c0_entrylo1(0);
 205                         write_c0_entryhi(KSEG0 + (idx << (PAGE_SHIFT+1)));
 206                         if (idx < 0)
 207                                 continue;
 208                         tlb_write_indexed();
 209                 }
 210                 write_c0_entryhi(pid);
 211         } else {
 212                 local_flush_tlb_all();
 213         }
 214         local_irq_restore(flags);
 215 }
 216
 217 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 218 {
 219         unsigned long flags;
 220         int cpu = smp_processor_id();
 221
 222         local_irq_save(flags);
 223         if (cpu_context(cpu, vma->vm_mm) != 0) {
 224                 int oldpid, newpid, idx;
 225                 newpid = cpu_asid(cpu, vma->vm_mm);
 226                 page &= (PAGE_MASK << 1);
 227                 oldpid = read_c0_entryhi() & ASID_MASK;
 228                 write_c0_entryhi(page | newpid);
 229                 tlb_probe();
 230                 idx = read_c0_index();
 231                 write_c0_entrylo0(0);
 232                 write_c0_entrylo1(0);
 233                 if(idx < 0)
 234                         goto finish;
 235                 /* Make sure all entries differ. */
 236                 write_c0_entryhi(KSEG0+(idx<<(PAGE_SHIFT+1)));
 237                 tlb_write_indexed();
 238         finish:
 239                 write_c0_entryhi(oldpid);
 240         }
 241         local_irq_restore(flags);
 242 }
 243
 244 /*
 245  * This one is only used for pages with the global bit set so we don't care
 246  * much about the ASID.
 247  */
 248 void local_flush_tlb_one(unsigned long page)
 249 {
 250         unsigned long flags;
 251         int oldpid, idx;
 252
 253         local_irq_save(flags);
 254         page &= (PAGE_MASK << 1);
 255         oldpid = read_c0_entryhi() & ASID_MASK;
 256         write_c0_entryhi(page);
 257         tlb_probe();
 258         idx = read_c0_index();
 259         write_c0_entrylo0(0);
 260         write_c0_entrylo1(0);
 261         if (idx >= 0) {
 262                 /* Make sure all entries differ. */
 263                 write_c0_entryhi(KSEG0+(idx<<(PAGE_SHIFT+1)));
 264                 tlb_write_indexed();
 265         }
 266         write_c0_entryhi(oldpid);
 267
 268         local_irq_restore(flags);
 269 }
 270
 271 /* All entries common to a mm share an asid.  To effectively flush
 272    these entries, we just bump the asid. */
 273 void local_flush_tlb_mm(struct mm_struct *mm)
 274 {
 275         int cpu = smp_processor_id();
 276         if (cpu_context(cpu, mm) != 0) {
 277                 drop_mmu_context(mm, cpu);
 278         }
 279 }
 280
 281 /* Stolen from mips32 routines */
 282
 283 void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 284 {
 285         unsigned long flags;
 286         pgd_t *pgdp;
 287         pmd_t *pmdp;
 288         pte_t *ptep;
 289         int idx, pid;
 290
 291         /*
 292          * Handle debugger faulting in for debugee.
 293          */
 294         if (current->active_mm != vma->vm_mm)
 295                 return;
 296
 297         local_irq_save(flags);
 298
 299         pid = read_c0_entryhi() & ASID_MASK;
 300         address &= (PAGE_MASK << 1);
 301         write_c0_entryhi(address | (pid));
 302         pgdp = pgd_offset(vma->vm_mm, address);
 303         tlb_probe();
 304         pmdp = pmd_offset(pgdp, address);
 305         idx = read_c0_index();
 306         ptep = pte_offset_map(pmdp, address);
 307         write_c0_entrylo0(pte_val(*ptep++) >> 6);
 308         write_c0_entrylo1(pte_val(*ptep) >> 6);
 309         if (idx < 0) {
 310                 tlb_write_random();
 311         } else {
 312                 tlb_write_indexed();
 313         }
 314         local_irq_restore(flags);
 315 }
 316
 317 /*
 318  * This is called from loadmmu.c.  We have to set up all the
 319  * memory management function pointers, as well as initialize
 320  * the caches and tlbs
 321  */
 322 void sb1_tlb_init(void)
 323 {
 324         write_c0_pagemask(PM_4K);
 325
 326         /*
 327          * We don't know what state the firmware left the TLB's in, so this is
 328          * the ultra-conservative way to flush the TLB's and avoid machine
 329          * check exceptions due to duplicate TLB entries
 330          */
 331         sb1_sanitize_tlb();
 332
 333         memcpy((void *)KSEG0, except_vec0_sb1, 0x80);
 334         flush_icache_range(KSEG0, KSEG0 + 0x80);
 335 }