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Merge with Linux 2.4.0-test4-pre3.
[linux-2.6/linux-mips.git] / drivers / net / sunbmac.c
blobb89c4ec2e7deff3900fa5414047be780ee17a1c4
1 /* $Id: sunbmac.c,v 1.20 2000/07/11 22:35:22 davem Exp $
2 * sunbmac.c: Driver for Sparc BigMAC 100baseT ethernet adapters.
3 *
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
5 */
6
7 static char *version =
8 "sunbmac.c:v1.9 11/Sep/99 David S. Miller (davem@redhat.com)\n";
9
10 #include <linux/module.h>
11
12 #include <linux/kernel.h>
13 #include <linux/sched.h>
14 #include <linux/types.h>
15 #include <linux/fcntl.h>
16 #include <linux/interrupt.h>
17 #include <linux/ptrace.h>
18 #include <linux/ioport.h>
19 #include <linux/in.h>
20 #include <linux/malloc.h>
21 #include <linux/string.h>
22 #include <linux/delay.h>
23 #include <linux/init.h>
24 #include <asm/system.h>
25 #include <asm/bitops.h>
26 #include <asm/io.h>
27 #include <asm/dma.h>
28 #include <linux/errno.h>
29 #include <asm/byteorder.h>
30
31 #include <asm/idprom.h>
32 #include <asm/sbus.h>
33 #include <asm/openprom.h>
34 #include <asm/oplib.h>
35 #include <asm/auxio.h>
36 #include <asm/pgtable.h>
37
38 #include <linux/netdevice.h>
39 #include <linux/etherdevice.h>
40 #include <linux/skbuff.h>
41
42 #include "sunbmac.h"
43
44 #undef DEBUG_PROBE
45 #undef DEBUG_TX
46 #undef DEBUG_IRQ
47
48 #ifdef DEBUG_PROBE
49 #define DP(x) printk x
50 #else
51 #define DP(x)
52 #endif
53
54 #ifdef DEBUG_TX
55 #define DTX(x) printk x
56 #else
57 #define DTX(x)
58 #endif
59
60 #ifdef DEBUG_IRQ
61 #define DIRQ(x) printk x
62 #else
63 #define DIRQ(x)
64 #endif
65
66 #ifdef MODULE
67 static struct bigmac *root_bigmac_dev = NULL;
68 #endif
69
70 #define DEFAULT_JAMSIZE 4 /* Toe jam */
71
72 #define QEC_RESET_TRIES 200
73
74 static int qec_global_reset(unsigned long gregs)
75 {
76 int tries = QEC_RESET_TRIES;
77
78 sbus_writel(GLOB_CTRL_RESET, gregs + GLOB_CTRL);
79 while (--tries) {
80 if (sbus_readl(gregs + GLOB_CTRL) & GLOB_CTRL_RESET) {
81 udelay(20);
82 continue;
83 }
84 break;
85 }
86 if (tries)
87 return 0;
88 printk(KERN_ERR "BigMAC: Cannot reset the QEC.\n");
89 return -1;
90 }
91
92 static void qec_init(struct bigmac *bp)
93 {
94 unsigned long gregs = bp->gregs;
95 struct sbus_dev *qec_sdev = bp->qec_sdev;
96 u8 bsizes = bp->bigmac_bursts;
97 u32 regval;
98
99 /* 64byte bursts do not work at the moment, do
100 * not even try to enable them. -DaveM
101 */
102 if (bsizes & DMA_BURST32)
103 regval = GLOB_CTRL_B32;
104 else
105 regval = GLOB_CTRL_B16;
106 sbus_writel(regval | GLOB_CTRL_BMODE, gregs + GLOB_CTRL);
107 sbus_writel(GLOB_PSIZE_2048, gregs + GLOB_PSIZE);
108
109 /* All of memsize is given to bigmac. */
110 sbus_writel(qec_sdev->reg_addrs[1].reg_size,
111 gregs + GLOB_MSIZE);
112
113 /* Half to the transmitter, half to the receiver. */
114 sbus_writel(qec_sdev->reg_addrs[1].reg_size >> 1,
115 gregs + GLOB_TSIZE);
116 sbus_writel(qec_sdev->reg_addrs[1].reg_size >> 1,
117 gregs + GLOB_RSIZE);
118 }
119
120 #define TX_RESET_TRIES 32
121 #define RX_RESET_TRIES 32
122
123 static void bigmac_tx_reset(unsigned long bregs)
124 {
125 int tries = TX_RESET_TRIES;
126
127 sbus_writel(0, bregs + BMAC_TXCFG);
128
129 /* The fifo threshold bit is read-only and does
130 * not clear. -DaveM
131 */
132 while ((sbus_readl(bregs + BMAC_TXCFG) & ~(BIGMAC_TXCFG_FIFO)) != 0 &&
133 --tries != 0)
134 udelay(20);
135
136 if (!tries) {
137 printk(KERN_ERR "BIGMAC: Transmitter will not reset.\n");
138 printk(KERN_ERR "BIGMAC: tx_cfg is %08x\n",
139 sbus_readl(bregs + BMAC_TXCFG));
140 }
141 }
142
143 static void bigmac_rx_reset(unsigned long bregs)
144 {
145 int tries = RX_RESET_TRIES;
146
147 sbus_writel(0, bregs + BMAC_RXCFG);
148 while (sbus_readl(bregs + BMAC_RXCFG) && --tries)
149 udelay(20);
150
151 if (!tries) {
152 printk(KERN_ERR "BIGMAC: Receiver will not reset.\n");
153 printk(KERN_ERR "BIGMAC: rx_cfg is %08x\n",
154 sbus_readl(bregs + BMAC_RXCFG));
155 }
156 }
157
158 /* Reset the transmitter and receiver. */
159 static void bigmac_stop(struct bigmac *bp)
160 {
161 bigmac_tx_reset(bp->bregs);
162 bigmac_rx_reset(bp->bregs);
163 }
164
165 static void bigmac_get_counters(struct bigmac *bp, unsigned long bregs)
166 {
167 struct net_device_stats *stats = &bp->enet_stats;
168
169 stats->rx_crc_errors += sbus_readl(bregs + BMAC_RCRCECTR);
170 sbus_writel(0, bregs + BMAC_RCRCECTR);
171
172 stats->rx_frame_errors += sbus_readl(bregs + BMAC_UNALECTR);
173 sbus_writel(0, bregs + BMAC_UNALECTR);
174
175 stats->rx_length_errors += sbus_readl(bregs + BMAC_GLECTR);
176 sbus_writel(0, bregs + BMAC_GLECTR);
177
178 stats->tx_aborted_errors += sbus_readl(bregs + BMAC_EXCTR);
179
180 stats->collisions +=
181 (sbus_readl(bregs + BMAC_EXCTR) +
182 sbus_readl(bregs + BMAC_LTCTR));
183 sbus_writel(0, bregs + BMAC_EXCTR);
184 sbus_writel(0, bregs + BMAC_LTCTR);
185 }
186
187 static void bigmac_clean_rings(struct bigmac *bp)
188 {
189 int i;
190
191 for (i = 0; i < RX_RING_SIZE; i++) {
192 if (bp->rx_skbs[i] != NULL) {
193 dev_kfree_skb_any(bp->rx_skbs[i]);
194 bp->rx_skbs[i] = NULL;
195 }
196 }
197
198 for (i = 0; i < TX_RING_SIZE; i++) {
199 if (bp->tx_skbs[i] != NULL) {
200 dev_kfree_skb_any(bp->tx_skbs[i]);
201 bp->tx_skbs[i] = NULL;
202 }
203 }
204 }
205
206 static void bigmac_init_rings(struct bigmac *bp, int from_irq)
207 {
208 struct bmac_init_block *bb = bp->bmac_block;
209 struct net_device *dev = bp->dev;
210 int i, gfp_flags = GFP_KERNEL;
211
212 if (from_irq || in_interrupt())
213 gfp_flags = GFP_ATOMIC;
214
215 bp->rx_new = bp->rx_old = bp->tx_new = bp->tx_old = 0;
216
217 /* Free any skippy bufs left around in the rings. */
218 bigmac_clean_rings(bp);
219
220 /* Now get new skbufs for the receive ring. */
221 for (i = 0; i < RX_RING_SIZE; i++) {
222 struct sk_buff *skb;
223
224 skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, gfp_flags);
225 if (!skb)
226 continue;
227
228 bp->rx_skbs[i] = skb;
229 skb->dev = dev;
230
231 /* Because we reserve afterwards. */
232 skb_put(skb, ETH_FRAME_LEN);
233 skb_reserve(skb, 34);
234
235 bb->be_rxd[i].rx_addr =
236 sbus_map_single(bp->bigmac_sdev, skb->data,
237 RX_BUF_ALLOC_SIZE - 34,
238 SBUS_DMA_FROMDEVICE);
239 bb->be_rxd[i].rx_flags =
240 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
241 }
242
243 for (i = 0; i < TX_RING_SIZE; i++)
244 bb->be_txd[i].tx_flags = bb->be_txd[i].tx_addr = 0;
245 }
246
247 #define MGMT_CLKON (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB|MGMT_PAL_DCLOCK)
248 #define MGMT_CLKOFF (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB)
249
250 static void idle_transceiver(unsigned long tregs)
251 {
252 int i = 20;
253
254 while (i--) {
255 sbus_writel(MGMT_CLKOFF, tregs + TCVR_MPAL);
256 sbus_readl(tregs + TCVR_MPAL);
257 sbus_writel(MGMT_CLKON, tregs + TCVR_MPAL);
258 sbus_readl(tregs + TCVR_MPAL);
259 }
260 }
261
262 static void write_tcvr_bit(struct bigmac *bp, unsigned long tregs, int bit)
263 {
264 if (bp->tcvr_type == internal) {
265 bit = (bit & 1) << 3;
266 sbus_writel(bit | (MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO),
267 tregs + TCVR_MPAL);
268 sbus_readl(tregs + TCVR_MPAL);
269 sbus_writel(bit | MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
270 tregs + TCVR_MPAL);
271 sbus_readl(tregs + TCVR_MPAL);
272 } else if (bp->tcvr_type == external) {
273 bit = (bit & 1) << 2;
274 sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB,
275 tregs + TCVR_MPAL);
276 sbus_readl(tregs + TCVR_MPAL);
277 sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB | MGMT_PAL_DCLOCK,
278 tregs + TCVR_MPAL);
279 sbus_readl(tregs + TCVR_MPAL);
280 } else {
281 printk(KERN_ERR "write_tcvr_bit: No transceiver type known!\n");
282 }
283 }
284
285 static int read_tcvr_bit(struct bigmac *bp, unsigned long tregs)
286 {
287 int retval = 0;
288
289 if (bp->tcvr_type == internal) {
290 sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
291 sbus_readl(tregs + TCVR_MPAL);
292 sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
293 tregs + TCVR_MPAL);
294 sbus_readl(tregs + TCVR_MPAL);
295 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3;
296 } else if (bp->tcvr_type == external) {
297 sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL);
298 sbus_readl(tregs + TCVR_MPAL);
299 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
300 sbus_readl(tregs + TCVR_MPAL);
301 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2;
302 } else {
303 printk(KERN_ERR "read_tcvr_bit: No transceiver type known!\n");
304 }
305 return retval;
306 }
307
308 static int read_tcvr_bit2(struct bigmac *bp, unsigned long tregs)
309 {
310 int retval = 0;
311
312 if (bp->tcvr_type == internal) {
313 sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
314 sbus_readl(tregs + TCVR_MPAL);
315 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3;
316 sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
317 sbus_readl(tregs + TCVR_MPAL);
318 } else if (bp->tcvr_type == external) {
319 sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL);
320 sbus_readl(tregs + TCVR_MPAL);
321 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2;
322 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
323 sbus_readl(tregs + TCVR_MPAL);
324 } else {
325 printk(KERN_ERR "read_tcvr_bit2: No transceiver type known!\n");
326 }
327 return retval;
328 }
329
330 static void put_tcvr_byte(struct bigmac *bp,
331 unsigned long tregs,
332 unsigned int byte)
333 {
334 int shift = 4;
335
336 do {
337 write_tcvr_bit(bp, tregs, ((byte >> shift) & 1));
338 shift -= 1;
339 } while (shift >= 0);
340 }
341
342 static void bigmac_tcvr_write(struct bigmac *bp, unsigned long tregs,
343 int reg, unsigned short val)
344 {
345 int shift;
346
347 reg &= 0xff;
348 val &= 0xffff;
349 switch(bp->tcvr_type) {
350 case internal:
351 case external:
352 break;
353
354 default:
355 printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n");
356 return;
357 };
358
359 idle_transceiver(tregs);
360 write_tcvr_bit(bp, tregs, 0);
361 write_tcvr_bit(bp, tregs, 1);
362 write_tcvr_bit(bp, tregs, 0);
363 write_tcvr_bit(bp, tregs, 1);
364
365 put_tcvr_byte(bp, tregs,
366 ((bp->tcvr_type == internal) ?
367 BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL));
368
369 put_tcvr_byte(bp, tregs, reg);
370
371 write_tcvr_bit(bp, tregs, 1);
372 write_tcvr_bit(bp, tregs, 0);
373
374 shift = 15;
375 do {
376 write_tcvr_bit(bp, tregs, (val >> shift) & 1);
377 shift -= 1;
378 } while (shift >= 0);
379 }
380
381 static unsigned short bigmac_tcvr_read(struct bigmac *bp,
382 unsigned long tregs,
383 int reg)
384 {
385 unsigned short retval = 0;
386
387 reg &= 0xff;
388 switch(bp->tcvr_type) {
389 case internal:
390 case external:
391 break;
392
393 default:
394 printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n");
395 return 0xffff;
396 };
397
398 idle_transceiver(tregs);
399 write_tcvr_bit(bp, tregs, 0);
400 write_tcvr_bit(bp, tregs, 1);
401 write_tcvr_bit(bp, tregs, 1);
402 write_tcvr_bit(bp, tregs, 0);
403
404 put_tcvr_byte(bp, tregs,
405 ((bp->tcvr_type == internal) ?
406 BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL));
407
408 put_tcvr_byte(bp, tregs, reg);
409
410 if (bp->tcvr_type == external) {
411 int shift = 15;
412
413 (void) read_tcvr_bit2(bp, tregs);
414 (void) read_tcvr_bit2(bp, tregs);
415
416 do {
417 int tmp;
418
419 tmp = read_tcvr_bit2(bp, tregs);
420 retval |= ((tmp & 1) << shift);
421 shift -= 1;
422 } while (shift >= 0);
423
424 (void) read_tcvr_bit2(bp, tregs);
425 (void) read_tcvr_bit2(bp, tregs);
426 (void) read_tcvr_bit2(bp, tregs);
427 } else {
428 int shift = 15;
429
430 (void) read_tcvr_bit(bp, tregs);
431 (void) read_tcvr_bit(bp, tregs);
432
433 do {
434 int tmp;
435
436 tmp = read_tcvr_bit(bp, tregs);
437 retval |= ((tmp & 1) << shift);
438 shift -= 1;
439 } while (shift >= 0);
440
441 (void) read_tcvr_bit(bp, tregs);
442 (void) read_tcvr_bit(bp, tregs);
443 (void) read_tcvr_bit(bp, tregs);
444 }
445 return retval;
446 }
447
448 static void bigmac_tcvr_init(struct bigmac *bp)
449 {
450 unsigned long tregs = bp->tregs;
451 u32 mpal;
452
453 idle_transceiver(tregs);
454 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
455 tregs + TCVR_MPAL);
456 sbus_readl(tregs + TCVR_MPAL);
457
458 /* Only the bit for the present transceiver (internal or
459 * external) will stick, set them both and see what stays.
460 */
461 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
462 sbus_readl(tregs + TCVR_MPAL);
463 udelay(20);
464
465 mpal = sbus_readl(tregs + TCVR_MPAL);
466 if (mpal & MGMT_PAL_EXT_MDIO) {
467 bp->tcvr_type = external;
468 sbus_writel(~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE),
469 tregs + TCVR_TPAL);
470 sbus_readl(tregs + TCVR_TPAL);
471 } else if (mpal & MGMT_PAL_INT_MDIO) {
472 bp->tcvr_type = internal;
473 sbus_writel(~(TCVR_PAL_SERIAL | TCVR_PAL_EXTLBACK |
474 TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE),
475 tregs + TCVR_TPAL);
476 sbus_readl(tregs + TCVR_TPAL);
477 } else {
478 printk(KERN_ERR "BIGMAC: AIEEE, neither internal nor "
479 "external MDIO available!\n");
480 printk(KERN_ERR "BIGMAC: mgmt_pal[%08x] tcvr_pal[%08x]\n",
481 sbus_readl(tregs + TCVR_MPAL),
482 sbus_readl(tregs + TCVR_TPAL));
483 }
484 }
485
486 static int bigmac_init(struct bigmac *, int);
487
488 static int try_next_permutation(struct bigmac *bp, unsigned long tregs)
489 {
490 if (bp->sw_bmcr & BMCR_SPEED100) {
491 int timeout;
492
493 /* Reset the PHY. */
494 bp->sw_bmcr = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK);
495 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
496 bp->sw_bmcr = (BMCR_RESET);
497 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
498
499 timeout = 64;
500 while (--timeout) {
501 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
502 if ((bp->sw_bmcr & BMCR_RESET) == 0)
503 break;
504 udelay(20);
505 }
506 if (timeout == 0)
507 printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name);
508
509 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
510
511 /* Now we try 10baseT. */
512 bp->sw_bmcr &= ~(BMCR_SPEED100);
513 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
514 return 0;
515 }
516
517 /* We've tried them all. */
518 return -1;
519 }
520
521 static void bigmac_timer(unsigned long data)
522 {
523 struct bigmac *bp = (struct bigmac *) data;
524 unsigned long tregs = bp->tregs;
525 int restart_timer = 0;
526
527 bp->timer_ticks++;
528 if (bp->timer_state == ltrywait) {
529 bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMSR);
530 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
531 if (bp->sw_bmsr & BMSR_LSTATUS) {
532 printk(KERN_INFO "%s: Link is now up at %s.\n",
533 bp->dev->name,
534 (bp->sw_bmcr & BMCR_SPEED100) ?
535 "100baseT" : "10baseT");
536 bp->timer_state = asleep;
537 restart_timer = 0;
538 } else {
539 if (bp->timer_ticks >= 4) {
540 int ret;
541
542 ret = try_next_permutation(bp, tregs);
543 if (ret == -1) {
544 printk(KERN_ERR "%s: Link down, cable problem?\n",
545 bp->dev->name);
546 ret = bigmac_init(bp, 0);
547 if (ret) {
548 printk(KERN_ERR "%s: Error, cannot re-init the "
549 "BigMAC.\n", bp->dev->name);
550 }
551 return;
552 }
553 bp->timer_ticks = 0;
554 restart_timer = 1;
555 } else {
556 restart_timer = 1;
557 }
558 }
559 } else {
560 /* Can't happens.... */
561 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
562 bp->dev->name);
563 restart_timer = 0;
564 bp->timer_ticks = 0;
565 bp->timer_state = asleep; /* foo on you */
566 }
567
568 if (restart_timer != 0) {
569 bp->bigmac_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
570 add_timer(&bp->bigmac_timer);
571 }
572 }
573
574 /* Well, really we just force the chip into 100baseT then
575 * 10baseT, each time checking for a link status.
576 */
577 static void bigmac_begin_auto_negotiation(struct bigmac *bp)
578 {
579 unsigned long tregs = bp->tregs;
580 int timeout;
581
582 /* Grab new software copies of PHY registers. */
583 bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMSR);
584 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
585
586 /* Reset the PHY. */
587 bp->sw_bmcr = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK);
588 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
589 bp->sw_bmcr = (BMCR_RESET);
590 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
591
592 timeout = 64;
593 while (--timeout) {
594 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
595 if ((bp->sw_bmcr & BMCR_RESET) == 0)
596 break;
597 udelay(20);
598 }
599 if (timeout == 0)
600 printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name);
601
602 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
603
604 /* First we try 100baseT. */
605 bp->sw_bmcr |= BMCR_SPEED100;
606 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
607
608 bp->timer_state = ltrywait;
609 bp->timer_ticks = 0;
610 bp->bigmac_timer.expires = jiffies + (12 * HZ) / 10;
611 bp->bigmac_timer.data = (unsigned long) bp;
612 bp->bigmac_timer.function = &bigmac_timer;
613 add_timer(&bp->bigmac_timer);
614 }
615
616 static int bigmac_init(struct bigmac *bp, int from_irq)
617 {
618 unsigned long gregs = bp->gregs;
619 unsigned long cregs = bp->creg;
620 unsigned long bregs = bp->bregs;
621 unsigned char *e = &bp->dev->dev_addr[0];
622
623 /* Latch current counters into statistics. */
624 bigmac_get_counters(bp, bregs);
625
626 /* Reset QEC. */
627 qec_global_reset(gregs);
628
629 /* Init QEC. */
630 qec_init(bp);
631
632 /* Alloc and reset the tx/rx descriptor chains. */
633 bigmac_init_rings(bp, from_irq);
634
635 /* Initialize the PHY. */
636 bigmac_tcvr_init(bp);
637
638 /* Stop transmitter and receiver. */
639 bigmac_stop(bp);
640
641 /* Set hardware ethernet address. */
642 sbus_writel(((e[4] << 8) | e[5]), bregs + BMAC_MACADDR2);
643 sbus_writel(((e[2] << 8) | e[3]), bregs + BMAC_MACADDR1);
644 sbus_writel(((e[0] << 8) | e[1]), bregs + BMAC_MACADDR0);
645
646 /* Clear the hash table until mc upload occurs. */
647 sbus_writel(0, bregs + BMAC_HTABLE3);
648 sbus_writel(0, bregs + BMAC_HTABLE2);
649 sbus_writel(0, bregs + BMAC_HTABLE1);
650 sbus_writel(0, bregs + BMAC_HTABLE0);
651
652 /* Enable Big Mac hash table filter. */
653 sbus_writel(BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_FIFO,
654 bregs + BMAC_RXCFG);
655 udelay(20);
656
657 /* Ok, configure the Big Mac transmitter. */
658 sbus_writel(BIGMAC_TXCFG_FIFO, bregs + BMAC_TXCFG);
659
660 /* The HME docs recommend to use the 10LSB of our MAC here. */
661 sbus_writel(((e[5] | e[4] << 8) & 0x3ff),
662 bregs + BMAC_RSEED);
663
664 /* Enable the output drivers no matter what. */
665 sbus_writel(BIGMAC_XCFG_ODENABLE | BIGMAC_XCFG_RESV,
666 bregs + BMAC_XIFCFG);
667
668 /* Tell the QEC where the ring descriptors are. */
669 sbus_writel(bp->bblock_dvma + bib_offset(be_rxd, 0),
670 cregs + CREG_RXDS);
671 sbus_writel(bp->bblock_dvma + bib_offset(be_txd, 0),
672 cregs + CREG_TXDS);
673
674 /* Setup the FIFO pointers into QEC local memory. */
675 sbus_writel(0, cregs + CREG_RXRBUFPTR);
676 sbus_writel(0, cregs + CREG_RXWBUFPTR);
677 sbus_writel(sbus_readl(gregs + GLOB_RSIZE),
678 cregs + CREG_TXRBUFPTR);
679 sbus_writel(sbus_readl(gregs + GLOB_RSIZE),
680 cregs + CREG_TXWBUFPTR);
681
682 /* Tell bigmac what interrupts we don't want to hear about. */
683 sbus_writel(BIGMAC_IMASK_GOTFRAME | BIGMAC_IMASK_SENTFRAME,
684 bregs + BMAC_IMASK);
685
686 /* Enable the various other irq's. */
687 sbus_writel(0, cregs + CREG_RIMASK);
688 sbus_writel(0, cregs + CREG_TIMASK);
689 sbus_writel(0, cregs + CREG_QMASK);
690 sbus_writel(0, cregs + CREG_BMASK);
691
692 /* Set jam size to a reasonable default. */
693 sbus_writel(DEFAULT_JAMSIZE, bregs + BMAC_JSIZE);
694
695 /* Clear collision counter. */
696 sbus_writel(0, cregs + CREG_CCNT);
697
698 /* Enable transmitter and receiver. */
699 sbus_writel(sbus_readl(bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE,
700 bregs + BMAC_TXCFG);
701 sbus_writel(sbus_readl(bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE,
702 bregs + BMAC_RXCFG);
703
704 /* Ok, start detecting link speed/duplex. */
705 bigmac_begin_auto_negotiation(bp);
706
707 /* Success. */
708 return 0;
709 }
710
711 /* Error interrupts get sent here. */
712 static void bigmac_is_medium_rare(struct bigmac *bp, u32 qec_status, u32 bmac_status)
713 {
714 printk(KERN_ERR "bigmac_is_medium_rare: ");
715 if (qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) {
716 if (qec_status & GLOB_STAT_ER)
717 printk("QEC_ERROR, ");
718 if (qec_status & GLOB_STAT_BM)
719 printk("QEC_BMAC_ERROR, ");
720 }
721 if (bmac_status & CREG_STAT_ERRORS) {
722 if (bmac_status & CREG_STAT_BERROR)
723 printk("BMAC_ERROR, ");
724 if (bmac_status & CREG_STAT_TXDERROR)
725 printk("TXD_ERROR, ");
726 if (bmac_status & CREG_STAT_TXLERR)
727 printk("TX_LATE_ERROR, ");
728 if (bmac_status & CREG_STAT_TXPERR)
729 printk("TX_PARITY_ERROR, ");
730 if (bmac_status & CREG_STAT_TXSERR)
731 printk("TX_SBUS_ERROR, ");
732
733 if (bmac_status & CREG_STAT_RXDROP)
734 printk("RX_DROP_ERROR, ");
735
736 if (bmac_status & CREG_STAT_RXSMALL)
737 printk("RX_SMALL_ERROR, ");
738 if (bmac_status & CREG_STAT_RXLERR)
739 printk("RX_LATE_ERROR, ");
740 if (bmac_status & CREG_STAT_RXPERR)
741 printk("RX_PARITY_ERROR, ");
742 if (bmac_status & CREG_STAT_RXSERR)
743 printk("RX_SBUS_ERROR, ");
744 }
745
746 printk(" RESET\n");
747 bigmac_init(bp, 1);
748 }
749
750 /* BigMAC transmit complete service routines. */
751 static void bigmac_tx(struct bigmac *bp)
752 {
753 struct be_txd *txbase = &bp->bmac_block->be_txd[0];
754 struct net_device *dev = bp->dev;
755 int elem;
756
757 spin_lock(&bp->lock);
758
759 elem = bp->tx_old;
760 DTX(("bigmac_tx: tx_old[%d] ", elem));
761 while (elem != bp->tx_new) {
762 struct sk_buff *skb;
763 struct be_txd *this = &txbase[elem];
764
765 DTX(("this(%p) [flags(%08x)addr(%08x)]",
766 this, this->tx_flags, this->tx_addr));
767
768 if (this->tx_flags & TXD_OWN)
769 break;
770 skb = bp->tx_skbs[elem];
771 bp->enet_stats.tx_packets++;
772 bp->enet_stats.tx_bytes += skb->len;
773 sbus_unmap_single(bp->bigmac_sdev,
774 this->tx_addr, skb->len,
775 SBUS_DMA_TODEVICE);
776
777 DTX(("skb(%p) ", skb));
778 bp->tx_skbs[elem] = NULL;
779 dev_kfree_skb_irq(skb);
780
781 elem = NEXT_TX(elem);
782 }
783 DTX((" DONE, tx_old=%d\n", elem));
784 bp->tx_old = elem;
785
786 if (netif_queue_stopped(dev) &&
787 TX_BUFFS_AVAIL(bp) > 0)
788 netif_wake_queue(bp->dev);
789
790 spin_unlock(&bp->lock);
791 }
792
793 /* BigMAC receive complete service routines. */
794 static void bigmac_rx(struct bigmac *bp)
795 {
796 struct be_rxd *rxbase = &bp->bmac_block->be_rxd[0];
797 struct be_rxd *this;
798 int elem = bp->rx_new, drops = 0;
799 u32 flags;
800
801 this = &rxbase[elem];
802 while (!((flags = this->rx_flags) & RXD_OWN)) {
803 struct sk_buff *skb;
804 int len = (flags & RXD_LENGTH); /* FCS not included */
805
806 /* Check for errors. */
807 if (len < ETH_ZLEN) {
808 bp->enet_stats.rx_errors++;
809 bp->enet_stats.rx_length_errors++;
810
811 drop_it:
812 /* Return it to the BigMAC. */
813 bp->enet_stats.rx_dropped++;
814 this->rx_flags =
815 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
816 goto next;
817 }
818 skb = bp->rx_skbs[elem];
819 if (len > RX_COPY_THRESHOLD) {
820 struct sk_buff *new_skb;
821
822 /* Now refill the entry, if we can. */
823 new_skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
824 if (new_skb == NULL) {
825 drops++;
826 goto drop_it;
827 }
828 sbus_unmap_single(bp->bigmac_sdev,
829 this->rx_addr,
830 RX_BUF_ALLOC_SIZE - 34,
831 SBUS_DMA_FROMDEVICE);
832 bp->rx_skbs[elem] = new_skb;
833 new_skb->dev = bp->dev;
834 skb_put(new_skb, ETH_FRAME_LEN);
835 skb_reserve(new_skb, 34);
836 this->rx_addr = sbus_map_single(bp->bigmac_sdev,
837 new_skb->data,
838 RX_BUF_ALLOC_SIZE - 34,
839 SBUS_DMA_FROMDEVICE);
840 this->rx_flags =
841 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
842
843 /* Trim the original skb for the netif. */
844 skb_trim(skb, len);
845 } else {
846 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
847
848 if (copy_skb == NULL) {
849 drops++;
850 goto drop_it;
851 }
852 copy_skb->dev = bp->dev;
853 skb_reserve(copy_skb, 2);
854 skb_put(copy_skb, len);
855 sbus_dma_sync_single(bp->bigmac_sdev,
856 this->rx_addr, len, SBUS_DMA_FROMDEVICE);
857 eth_copy_and_sum(copy_skb, (unsigned char *)skb->data, len, 0);
858
859 /* Reuse original ring buffer. */
860 this->rx_flags =
861 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
862
863 skb = copy_skb;
864 }
865
866 /* No checksums done by the BigMAC ;-( */
867 skb->protocol = eth_type_trans(skb, bp->dev);
868 netif_rx(skb);
869 bp->enet_stats.rx_packets++;
870 bp->enet_stats.rx_bytes += len;
871 next:
872 elem = NEXT_RX(elem);
873 this = &rxbase[elem];
874 }
875 bp->rx_new = elem;
876 if (drops)
877 printk(KERN_NOTICE "%s: Memory squeeze, deferring packet.\n", bp->dev->name);
878 }
879
880 static void bigmac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
881 {
882 struct bigmac *bp = (struct bigmac *) dev_id;
883 u32 qec_status, bmac_status;
884
885 DIRQ(("bigmac_interrupt: "));
886
887 /* Latch status registers now. */
888 bmac_status = sbus_readl(bp->creg + CREG_STAT);
889 qec_status = sbus_readl(bp->gregs + GLOB_STAT);
890
891 DIRQ(("qec_status=%08x bmac_status=%08x\n", qec_status, bmac_status));
892 if ((qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) ||
893 (bmac_status & CREG_STAT_ERRORS))
894 bigmac_is_medium_rare(bp, qec_status, bmac_status);
895
896 if (bmac_status & CREG_STAT_TXIRQ)
897 bigmac_tx(bp);
898
899 if (bmac_status & CREG_STAT_RXIRQ)
900 bigmac_rx(bp);
901 }
902
903 static int bigmac_open(struct net_device *dev)
904 {
905 struct bigmac *bp = (struct bigmac *) dev->priv;
906 int res;
907
908 if (request_irq(dev->irq, &bigmac_interrupt,
909 SA_SHIRQ, "BIG MAC", (void *) bp)) {
910 printk(KERN_ERR "BIGMAC: Can't order irq %d to go.\n", dev->irq);
911 return -EAGAIN;
912 }
913 init_timer(&bp->bigmac_timer);
914 res = bigmac_init(bp, 0);
915 if (!res) {
916 MOD_INC_USE_COUNT;
917 }
918 return res;
919 }
920
921 static int bigmac_close(struct net_device *dev)
922 {
923 struct bigmac *bp = (struct bigmac *) dev->priv;
924
925 del_timer(&bp->bigmac_timer);
926 bp->timer_state = asleep;
927 bp->timer_ticks = 0;
928
929 bigmac_stop(bp);
930 bigmac_clean_rings(bp);
931 free_irq(dev->irq, (void *)bp);
932 MOD_DEC_USE_COUNT;
933 return 0;
934 }
935
936 static void bigmac_tx_timeout(struct net_device *dev)
937 {
938 struct bigmac *bp = (struct bigmac *) dev->priv;
939
940 bigmac_init(bp, 0);
941 netif_wake_queue(dev);
942 }
943
944 /* Put a packet on the wire. */
945 static int bigmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
946 {
947 struct bigmac *bp = (struct bigmac *) dev->priv;
948 int len, entry;
949 u32 mapping;
950
951 len = skb->len;
952 mapping = sbus_map_single(bp->bigmac_sdev, skb->data, len, SBUS_DMA_TODEVICE);
953
954 /* Avoid a race... */
955 spin_lock_irq(&bp->lock);
956 entry = bp->tx_new;
957 DTX(("bigmac_start_xmit: len(%d) entry(%d)\n", len, entry));
958 bp->bmac_block->be_txd[entry].tx_flags = TXD_UPDATE;
959 bp->tx_skbs[entry] = skb;
960 bp->bmac_block->be_txd[entry].tx_addr = mapping;
961 bp->bmac_block->be_txd[entry].tx_flags =
962 (TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH));
963 bp->tx_new = NEXT_TX(entry);
964 if (TX_BUFFS_AVAIL(bp) <= 0)
965 netif_stop_queue(dev);
966 spin_unlock_irq(&bp->lock);
967
968 /* Get it going. */
969 sbus_writel(CREG_CTRL_TWAKEUP, bp->creg + CREG_CTRL);
970
971
972 dev->trans_start = jiffies;
973
974 return 0;
975 }
976
977 static struct net_device_stats *bigmac_get_stats(struct net_device *dev)
978 {
979 struct bigmac *bp = (struct bigmac *) dev->priv;
980
981 bigmac_get_counters(bp, bp->bregs);
982 return &bp->enet_stats;
983 }
984
985 #define CRC_POLYNOMIAL_BE 0x04c11db7UL /* Ethernet CRC, big endian */
986 #define CRC_POLYNOMIAL_LE 0xedb88320UL /* Ethernet CRC, little endian */
987
988 static void bigmac_set_multicast(struct net_device *dev)
989 {
990 struct bigmac *bp = (struct bigmac *) dev->priv;
991 unsigned long bregs = bp->bregs;
992 struct dev_mc_list *dmi = dev->mc_list;
993 char *addrs;
994 int i, j, bit, byte;
995 u32 tmp, crc, poly = CRC_POLYNOMIAL_LE;
996
997 /* Disable the receiver. The bit self-clears when
998 * the operation is complete.
999 */
1000 tmp = sbus_readl(bregs + BMAC_RXCFG);
1001 tmp &= ~(BIGMAC_RXCFG_ENABLE);
1002 sbus_writel(tmp, bregs + BMAC_RXCFG);
1003 while ((sbus_readl(bregs + BMAC_RXCFG) & BIGMAC_RXCFG_ENABLE) != 0)
1004 udelay(20);
1005
1006 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
1007 sbus_writel(0xffff, bregs + BMAC_HTABLE0);
1008 sbus_writel(0xffff, bregs + BMAC_HTABLE1);
1009 sbus_writel(0xffff, bregs + BMAC_HTABLE2);
1010 sbus_writel(0xffff, bregs + BMAC_HTABLE3);
1011 } else if (dev->flags & IFF_PROMISC) {
1012 tmp = sbus_readl(bregs + BMAC_RXCFG);
1013 tmp |= BIGMAC_RXCFG_PMISC;
1014 sbus_writel(tmp, bregs + BMAC_RXCFG);
1015 } else {
1016 u16 hash_table[4];
1017
1018 for (i = 0; i < 4; i++)
1019 hash_table[i] = 0;
1020
1021 for (i = 0; i < dev->mc_count; i++) {
1022 addrs = dmi->dmi_addr;
1023 dmi = dmi->next;
1024
1025 if (!(*addrs & 1))
1026 continue;
1027
1028 crc = 0xffffffffU;
1029 for (byte = 0; byte < 6; byte++) {
1030 for (bit = *addrs++, j = 0; j < 8; j++, bit >>= 1) {
1031 int test;
1032
1033 test = ((bit ^ crc) & 0x01);
1034 crc >>= 1;
1035 if (test)
1036 crc = crc ^ poly;
1037 }
1038 }
1039 crc >>= 26;
1040 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1041 }
1042 sbus_writel(hash_table[0], bregs + BMAC_HTABLE0);
1043 sbus_writel(hash_table[1], bregs + BMAC_HTABLE1);
1044 sbus_writel(hash_table[2], bregs + BMAC_HTABLE2);
1045 sbus_writel(hash_table[3], bregs + BMAC_HTABLE3);
1046 }
1047
1048 /* Re-enable the receiver. */
1049 tmp = sbus_readl(bregs + BMAC_RXCFG);
1050 tmp |= BIGMAC_RXCFG_ENABLE;
1051 sbus_writel(tmp, bregs + BMAC_RXCFG);
1052 }
1053
1054 static int __init bigmac_ether_init(struct net_device *dev, struct sbus_dev *qec_sdev)
1055 {
1056 static int version_printed = 0;
1057 struct bigmac *bp = 0;
1058 u8 bsizes, bsizes_more;
1059 int i, res = ENOMEM;
1060
1061 /* Get a new device struct for this interface. */
1062 dev = init_etherdev(0, sizeof(struct bigmac));
1063
1064 if (version_printed++ == 0)
1065 printk(KERN_INFO "%s", version);
1066
1067 /* Report what we have found to the user. */
1068 printk(KERN_INFO "%s: BigMAC 100baseT Ethernet ", dev->name);
1069 dev->base_addr = (long) qec_sdev;
1070 for (i = 0; i < 6; i++)
1071 printk("%2.2x%c", dev->dev_addr[i] = idprom->id_ethaddr[i],
1072 i == 5 ? ' ' : ':');
1073 printk("\n");
1074
1075 /* Setup softc, with backpointers to QEC and BigMAC SBUS device structs. */
1076 bp = (struct bigmac *) dev->priv;
1077 bp->qec_sdev = qec_sdev;
1078 bp->bigmac_sdev = qec_sdev->child;
1079
1080 spin_lock_init(&bp->lock);
1081
1082 /* All further failures we find return this. */
1083 res = ENODEV;
1084
1085 /* Verify the registers we expect, are actually there. */
1086 if ((bp->bigmac_sdev->num_registers != 3) ||
1087 (bp->qec_sdev->num_registers != 2)) {
1088 printk(KERN_ERR "BIGMAC: Device does not have 2 and 3 regs, it has %d and %d.\n",
1089 bp->qec_sdev->num_registers,
1090 bp->bigmac_sdev->num_registers);
1091 printk(KERN_ERR "BIGMAC: Would you like that for here or to go?\n");
1092 goto fail_and_cleanup;
1093 }
1094
1095 /* Map in QEC global control registers. */
1096 bp->gregs = sbus_ioremap(&bp->qec_sdev->resource[0], 0,
1097 GLOB_REG_SIZE, "BigMAC QEC GLobal Regs");
1098 if (!bp->gregs) {
1099 printk(KERN_ERR "BIGMAC: Cannot map QEC global registers.\n");
1100 goto fail_and_cleanup;
1101 }
1102
1103 /* Make sure QEC is in BigMAC mode. */
1104 if ((sbus_readl(bp->gregs + GLOB_CTRL) & 0xf0000000) != GLOB_CTRL_BMODE) {
1105 printk(KERN_ERR "BigMAC: AIEEE, QEC is not in BigMAC mode!\n");
1106 goto fail_and_cleanup;
1107 }
1108
1109 /* Reset the QEC. */
1110 if (qec_global_reset(bp->gregs))
1111 goto fail_and_cleanup;
1112
1113 /* Get supported SBUS burst sizes. */
1114 bsizes = prom_getintdefault(bp->qec_sdev->prom_node,
1115 "burst-sizes",
1116 0xff);
1117
1118 bsizes_more = prom_getintdefault(bp->qec_sdev->bus->prom_node,
1119 "burst-sizes",
1120 0xff);
1121
1122 bsizes &= 0xff;
1123 if (bsizes_more != 0xff)
1124 bsizes &= bsizes_more;
1125 if (bsizes == 0xff || (bsizes & DMA_BURST16) == 0 ||
1126 (bsizes & DMA_BURST32) == 0)
1127 bsizes = (DMA_BURST32 - 1);
1128 bp->bigmac_bursts = bsizes;
1129
1130 /* Perform QEC initialization. */
1131 qec_init(bp);
1132
1133 /* Map in the BigMAC channel registers. */
1134 bp->creg = sbus_ioremap(&bp->bigmac_sdev->resource[0], 0,
1135 CREG_REG_SIZE, "BigMAC QEC Channel Regs");
1136 if (!bp->creg) {
1137 printk(KERN_ERR "BIGMAC: Cannot map QEC channel registers.\n");
1138 goto fail_and_cleanup;
1139 }
1140
1141 /* Map in the BigMAC control registers. */
1142 bp->bregs = sbus_ioremap(&bp->bigmac_sdev->resource[1], 0,
1143 BMAC_REG_SIZE, "BigMAC Primary Regs");
1144 if (!bp->bregs) {
1145 printk(KERN_ERR "BIGMAC: Cannot map BigMAC primary registers.\n");
1146 goto fail_and_cleanup;
1147 }
1148
1149 /* Map in the BigMAC transceiver registers, this is how you poke at
1150 * the BigMAC's PHY.
1151 */
1152 bp->tregs = sbus_ioremap(&bp->bigmac_sdev->resource[2], 0,
1153 TCVR_REG_SIZE, "BigMAC Transceiver Regs");
1154 if (!bp->tregs) {
1155 printk(KERN_ERR "BIGMAC: Cannot map BigMAC transceiver registers.\n");
1156 goto fail_and_cleanup;
1157 }
1158
1159 /* Stop the BigMAC. */
1160 bigmac_stop(bp);
1161
1162 /* Allocate transmit/receive descriptor DVMA block. */
1163 bp->bmac_block = sbus_alloc_consistent(bp->bigmac_sdev,
1164 PAGE_SIZE,
1165 &bp->bblock_dvma);
1166 if (bp->bmac_block == NULL || bp->bblock_dvma == 0) {
1167 printk(KERN_ERR "BIGMAC: Cannot allocate consistent DMA.\n");
1168 goto fail_and_cleanup;
1169 }
1170
1171 /* Get the board revision of this BigMAC. */
1172 bp->board_rev = prom_getintdefault(bp->bigmac_sdev->prom_node,
1173 "board-version", 1);
1174
1175 /* Init auto-negotiation timer state. */
1176 init_timer(&bp->bigmac_timer);
1177 bp->timer_state = asleep;
1178 bp->timer_ticks = 0;
1179
1180 /* Backlink to generic net device struct. */
1181 bp->dev = dev;
1182
1183 /* Set links to our BigMAC open and close routines. */
1184 dev->open = &bigmac_open;
1185 dev->stop = &bigmac_close;
1186 dev->hard_start_xmit = &bigmac_start_xmit;
1187
1188 /* Set links to BigMAC statistic and multi-cast loading code. */
1189 dev->get_stats = &bigmac_get_stats;
1190 dev->set_multicast_list = &bigmac_set_multicast;
1191
1192 dev->tx_timeout = &bigmac_tx_timeout;
1193 dev->watchdog_timeo = 5*HZ;
1194
1195 /* Finish net device registration. */
1196 dev->irq = bp->bigmac_sdev->irqs[0];
1197 dev->dma = 0;
1198 ether_setup(dev);
1199
1200 #ifdef MODULE
1201 /* Put us into the list of instances attached for later module unloading. */
1202 bp->next_module = root_bigmac_dev;
1203 root_bigmac_dev = bp;
1204 #endif
1205 return 0;
1206
1207 fail_and_cleanup:
1208 /* Something went wrong, undo whatever we did so far. */
1209 if (bp) {
1210 /* Free register mappings if any. */
1211 if (bp->gregs)
1212 sbus_iounmap(bp->gregs, GLOB_REG_SIZE);
1213 if (bp->creg)
1214 sbus_iounmap(bp->creg, CREG_REG_SIZE);
1215 if (bp->bregs)
1216 sbus_iounmap(bp->bregs, BMAC_REG_SIZE);
1217 if (bp->tregs)
1218 sbus_iounmap(bp->tregs, TCVR_REG_SIZE);
1219
1220 if (bp->bmac_block)
1221 sbus_free_consistent(bp->bigmac_sdev,
1222 PAGE_SIZE,
1223 bp->bmac_block,
1224 bp->bblock_dvma);
1225
1226 /* Free the BigMAC softc. */
1227 kfree(bp);
1228 dev->priv = 0;
1229 }
1230 return res; /* Return error code. */
1231 }
1232
1233 /* QEC can be the parent of either QuadEthernet or
1234 * a BigMAC. We want the latter.
1235 */
1236 static int __init bigmac_match(struct sbus_dev *sdev)
1237 {
1238 struct sbus_dev *child = sdev->child;
1239
1240 if (strcmp(sdev->prom_name, "qec") != 0)
1241 return 0;
1242
1243 if (child == NULL)
1244 return 0;
1245
1246 if (strcmp(child->prom_name, "be") != 0)
1247 return 0;
1248
1249 return 1;
1250 }
1251
1252 static int __init bigmac_probe(void)
1253 {
1254 struct net_device *dev = NULL;
1255 struct sbus_bus *sbus;
1256 struct sbus_dev *sdev = 0;
1257 static int called = 0;
1258 int cards = 0, v;
1259
1260 #ifdef MODULE
1261 root_bigmac_dev = NULL;
1262 #endif
1263
1264 if (called)
1265 return -ENODEV;
1266 called++;
1267
1268 for_each_sbus(sbus) {
1269 for_each_sbusdev(sdev, sbus) {
1270 if (cards)
1271 dev = NULL;
1272
1273 if (bigmac_match(sdev)) {
1274 cards++;
1275 if ((v = bigmac_ether_init(dev, sdev)))
1276 return v;
1277 }
1278 }
1279 }
1280 if (!cards)
1281 return -ENODEV;
1282 return 0;
1283 }
1284
1285 static void __exit bigmac_cleanup(void)
1286 {
1287 #ifdef MODULE
1288 /* No need to check MOD_IN_USE, as sys_delete_module() checks. */
1289 while (root_bigmac_dev) {
1290 struct bigmac *bp = root_bigmac_dev;
1291 struct bigmac *bp_nxt = root_bigmac_dev->next_module;
1292
1293 sbus_iounmap(bp->gregs, GLOB_REG_SIZE);
1294 sbus_iounmap(bp->creg, CREG_REG_SIZE);
1295 sbus_iounmap(bp->bregs, BMAC_REG_SIZE);
1296 sbus_iounmap(bp->tregs, TCVR_REG_SIZE);
1297 sbus_free_consistent(bp->bigmac_sdev,
1298 PAGE_SIZE,
1299 bp->bmac_block,
1300 bp->bblock_dvma);
1301
1302 unregister_netdev(bp->dev);
1303 kfree(bp->dev);
1304 root_bigmac_dev = bp_nxt;
1305 }
1306 #endif /* MODULE */
1307 }
1308
1309 module_init(bigmac_probe);
1310 module_exit(bigmac_cleanup);
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