1 /* $Id: pcic.c,v 1.16 2000/07/11 01:38:57 davem Exp $
2 * pcic.c: Sparc/PCI controller support
4 * Copyright (C) 1998 V. Roganov and G. Raiko
6 * Code is derived from Ultra/PCI PSYCHO controller support, see that
9 * Support for diverse IIep based platforms by Pete Zaitcev.
10 * CP-1200 by Eric Brower.
13 #include <linux/config.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/init.h>
18 #include <linux/malloc.h>
21 #include <asm/sbus.h> /* for sanity check... */
22 #include <asm/swift.h> /* for cache flushing. */
25 #include <linux/ctype.h>
26 #include <linux/pci.h>
27 #include <linux/timex.h>
28 #include <linux/interrupt.h>
31 #include <asm/oplib.h>
33 #include <asm/timer.h>
34 #include <asm/uaccess.h>
38 int pcibios_present(void)
43 asmlinkage
int sys_pciconfig_read(unsigned long bus
,
52 asmlinkage
int sys_pciconfig_write(unsigned long bus
,
63 #ifdef CONFIG_SUN_JSFLASH
64 extern int jsflash_init(void);
67 struct pci_fixup pcibios_fixups
[] = {
71 unsigned int pcic_pin_to_irq(unsigned int pin
, char *name
);
74 * I studied different documents and many live PROMs both from 2.30
75 * family and 3.xx versions. I came to the amazing conclusion: there is
76 * absolutely no way to route interrupts in IIep systems relying on
77 * information which PROM presents. We must hardcode interrupt routing
78 * schematics. And this actually sucks. -- zaitcev 1999/05/12
80 * To find irq for a device we determine which routing map
81 * is in effect or, in other words, on which machine we are running.
82 * We use PROM name for this although other techniques may be used
83 * in special cases (Gleb reports a PROMless IIep based system).
84 * Once we know the map we take device configuration address and
85 * find PCIC pin number where INT line goes. Then we may either program
86 * preferred irq into the PCIC or supply the preexisting irq to the device.
89 unsigned char busno
; /* PCI bus number */
90 unsigned char devfn
; /* Configuration address */
91 unsigned char pin
; /* PCIC external interrupt pin */
92 unsigned char irq
; /* Preferred IRQ (mappable in PCIC) */
93 unsigned int force
; /* Enforce preferred IRQ */
98 struct pcic_ca2irq
*intmap
;
103 * JavaEngine-1 apparently has different versions.
105 * According to communications with Sun folks, for P2 build 501-4628-03:
106 * pin 0 - parallel, audio;
109 * pin 3 - PS/2 kbd and mouse.
111 * OEM manual (805-1486):
114 * pin 2: IGA (unused)
115 * pin 3: Not connected
116 * OEM manual says that 501-4628 & 501-4811 are the same thing,
117 * only the latter has NAND flash in place.
119 * So far unofficial Sun wins over the OEM manual. Poor OEMs...
121 static struct pcic_ca2irq pcic_i_je1a
[] = { /* 501-4811-03 */
122 { 0, 0x00, 2, 12, 0 }, /* EBus: hogs all */
123 { 0, 0x01, 1, 6, 1 }, /* Happy Meal */
124 { 0, 0x80, 0, 7, 0 }, /* IGA (unused) */
127 /* XXX JS-E entry is incomplete - PCI Slot 2 address (pin 7)? */
128 static struct pcic_ca2irq pcic_i_jse
[] = {
129 { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */
130 { 0, 0x01, 1, 6, 0 }, /* hme */
131 { 0, 0x08, 2, 9, 0 }, /* VGA - we hope not used :) */
132 { 0, 0x10, 6, 8, 0 }, /* PCI INTA# in Slot 1 */
133 { 0, 0x18, 7, 12, 0 }, /* PCI INTA# in Slot 2, shared w. RTC */
134 { 0, 0x38, 4, 9, 0 }, /* All ISA devices. Read 8259. */
135 { 0, 0x80, 5, 11, 0 }, /* EIDE */
136 /* {0,0x88, 0,0,0} - unknown device... PMU? Probably no interrupt. */
137 { 0, 0xA0, 4, 9, 0 }, /* USB */
139 * Some pins belong to non-PCI devices, we hardcode them in drivers.
140 * sun4m timers - irq 10, 14
141 * PC style RTC - pin 7, irq 4 ?
142 * Smart card, Parallel - pin 4 shared with USB, ISA
143 * audio - pin 3, irq 5 ?
147 /* SPARCengine-6 was the original release name of CP1200.
148 * The documentation differs between the two versions
150 static struct pcic_ca2irq pcic_i_se6
[] = {
151 { 0, 0x08, 0, 2, 0 }, /* SCSI */
152 { 0, 0x01, 1, 6, 0 }, /* HME */
153 { 0, 0x00, 3, 13, 0 }, /* EBus */
157 * Krups (courtesy of Varol Kaptan)
158 * No documentation available, but it was easy to guess
159 * because it was very similar to Espresso.
161 * pin 0 - kbd, mouse, serial;
163 * pin 2 - igs (we do not use it);
165 * pin 4,5,6 - unused;
166 * pin 7 - RTC (from P2 onwards as David B. says).
168 static struct pcic_ca2irq pcic_i_jk
[] = {
169 { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */
170 { 0, 0x01, 1, 6, 0 }, /* hme */
174 * Several entries in this list may point to the same routing map
175 * as several PROMs may be installed on the same physical board.
177 #define SN2L_INIT(name, map) \
178 { name, map, sizeof(map)/sizeof(struct pcic_ca2irq) }
180 static struct pcic_sn2list pcic_known_sysnames
[] = {
181 SN2L_INIT("SUNW,JavaEngine1", pcic_i_je1a
), /* JE1, PROM 2.32 */
182 SN2L_INIT("SUNW,JS-E", pcic_i_jse
), /* PROLL JavaStation-E */
183 SN2L_INIT("SUNW,SPARCengine-6", pcic_i_se6
), /* SPARCengine-6/CP-1200 */
184 SN2L_INIT("SUNW,JS-NC", pcic_i_jk
), /* PROLL JavaStation-NC */
185 SN2L_INIT("SUNW,JSIIep", pcic_i_jk
), /* OBP JavaStation-NC */
190 * Only one PCIC per IIep,
191 * and since we have no SMP IIep, only one per system.
193 static int pcic0_up
= 0;
194 static struct linux_pcic pcic0
;
196 unsigned int pcic_regs
;
197 volatile int pcic_speculative
;
198 volatile int pcic_trapped
;
200 static void pci_do_gettimeofday(struct timeval
*tv
);
201 static void pci_do_settimeofday(struct timeval
*tv
);
203 #define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (((unsigned int)bus) << 16) | (((unsigned int)device_fn) << 8) | (where & ~3))
205 static int pcic_read_config_dword(struct pci_dev
*dev
, int where
, u32
*value
);
206 static int pcic_write_config_dword(struct pci_dev
*dev
, int where
, u32 value
);
208 static int pcic_read_config_byte(struct pci_dev
*dev
, int where
, u8
*value
)
212 pcic_read_config_dword(dev
, where
&~3, &v
);
213 *value
= 0xff & (v
>> (8*(where
& 3)));
214 return PCIBIOS_SUCCESSFUL
;
217 static int pcic_read_config_word(struct pci_dev
*dev
, int where
, u16
*value
)
220 if (where
&1) return PCIBIOS_BAD_REGISTER_NUMBER
;
222 pcic_read_config_dword(dev
, where
&~3, &v
);
223 *value
= 0xffff & (v
>> (8*(where
& 3)));
224 return PCIBIOS_SUCCESSFUL
;
227 static int pcic_read_config_dword(struct pci_dev
*dev
, int where
, u32
*value
)
229 unsigned char bus
= dev
->bus
->number
;
230 unsigned char device_fn
= dev
->devfn
;
231 /* unsigned char where; */
233 struct linux_pcic
*pcic
;
236 if (where
&3) return PCIBIOS_BAD_REGISTER_NUMBER
;
237 if (bus
!= 0) return PCIBIOS_DEVICE_NOT_FOUND
;
241 #if 0 /* does not fail here */
242 pcic_speculative
= 1;
245 writel(CONFIG_CMD(bus
,device_fn
,where
), pcic
->pcic_config_space_addr
);
246 #if 0 /* does not fail here */
249 restore_flags(flags
);
251 return PCIBIOS_SUCCESSFUL
;
254 pcic_speculative
= 2;
256 *value
= readl(pcic
->pcic_config_space_data
+ (where
&4));
259 pcic_speculative
= 0;
260 restore_flags(flags
);
262 return PCIBIOS_SUCCESSFUL
;
264 pcic_speculative
= 0;
265 restore_flags(flags
);
266 return PCIBIOS_SUCCESSFUL
;
269 static int pcic_write_config_byte(struct pci_dev
*dev
, int where
, u8 value
)
273 pcic_read_config_dword(dev
, where
&~3, &v
);
274 v
= (v
& ~(0xff << (8*(where
&3)))) |
275 ((0xff&(unsigned)value
) << (8*(where
&3)));
276 return pcic_write_config_dword(dev
, where
&~3, v
);
279 static int pcic_write_config_word(struct pci_dev
*dev
, int where
, u16 value
)
283 if (where
&1) return PCIBIOS_BAD_REGISTER_NUMBER
;
284 pcic_read_config_dword(dev
, where
&~3, &v
);
285 v
= (v
& ~(0xffff << (8*(where
&3)))) |
286 ((0xffff&(unsigned)value
) << (8*(where
&3)));
287 return pcic_write_config_dword(dev
, where
&~3, v
);
290 static int pcic_write_config_dword(struct pci_dev
*dev
, int where
, u32 value
)
292 unsigned char bus
= dev
->bus
->number
;
293 unsigned char devfn
= dev
->devfn
;
294 struct linux_pcic
*pcic
;
297 if (where
&3) return PCIBIOS_BAD_REGISTER_NUMBER
;
298 if (bus
!= 0) return PCIBIOS_DEVICE_NOT_FOUND
;
302 writel(CONFIG_CMD(bus
,devfn
,where
), pcic
->pcic_config_space_addr
);
303 writel(value
, pcic
->pcic_config_space_data
+ (where
&4));
304 restore_flags(flags
);
305 return PCIBIOS_SUCCESSFUL
;
308 static struct pci_ops pcic_ops
= {
309 pcic_read_config_byte
,
310 pcic_read_config_word
,
311 pcic_read_config_dword
,
312 pcic_write_config_byte
,
313 pcic_write_config_word
,
314 pcic_write_config_dword
,
318 * On sparc64 pcibios_init() calls pci_controller_probe().
319 * We want PCIC probed little ahead so that interrupt controller
320 * would be operational.
322 int __init
pcic_probe(void)
324 struct linux_pcic
*pcic
;
325 struct linux_prom_registers regs
[PROMREG_MAX
];
326 struct linux_pbm_info
* pbm
;
332 prom_printf("PCIC: called twice!\n");
337 node
= prom_getchild (prom_root_node
);
338 node
= prom_searchsiblings (node
, "pci");
342 * Map in PCIC register set, config space, and IO base
344 err
= prom_getproperty(node
, "reg", (char*)regs
, sizeof(regs
));
345 if (err
== 0 || err
== -1) {
346 prom_printf("PCIC: Error, cannot get PCIC registers "
353 pcic
->pcic_res_regs
.name
= "pcic_registers";
354 pcic
->pcic_regs
= (unsigned long)
355 ioremap(regs
[0].phys_addr
, regs
[0].reg_size
);
356 if (!pcic
->pcic_regs
) {
357 prom_printf("PCIC: Error, cannot map PCIC registers.\n");
361 pcic
->pcic_res_io
.name
= "pcic_io";
362 if ((pcic
->pcic_io
= (unsigned long)
363 ioremap(regs
[1].phys_addr
, 0x10000)) == 0) {
364 prom_printf("PCIC: Error, cannot map PCIC IO Base.\n");
368 pcic
->pcic_res_cfg_addr
.name
= "pcic_cfg_addr";
369 if ((pcic
->pcic_config_space_addr
= (unsigned long)
370 ioremap(regs
[2].phys_addr
, regs
[2].reg_size
* 2)) == 0) {
371 prom_printf("PCIC: Error, cannot map"
372 "PCI Configuration Space Address.\n");
377 * Docs say three least significant bits in address and data
378 * must be the same. Thus, we need adjust size of data.
380 pcic
->pcic_res_cfg_data
.name
= "pcic_cfg_data";
381 if ((pcic
->pcic_config_space_data
= (unsigned long)
382 ioremap(regs
[3].phys_addr
, regs
[3].reg_size
* 2)) == 0) {
383 prom_printf("PCIC: Error, cannot map"
384 "PCI Configuration Space Data.\n");
389 pbm
->prom_node
= node
;
390 prom_getstring(node
, "name", namebuf
, 63); namebuf
[63] = 0;
391 strcpy(pbm
->prom_name
, namebuf
);
394 extern volatile int t_nmi
[1];
395 extern int pcic_nmi_trap_patch
[1];
397 t_nmi
[0] = pcic_nmi_trap_patch
[0];
398 t_nmi
[1] = pcic_nmi_trap_patch
[1];
399 t_nmi
[2] = pcic_nmi_trap_patch
[2];
400 t_nmi
[3] = pcic_nmi_trap_patch
[3];
401 swift_flush_dcache();
402 pcic_regs
= pcic
->pcic_regs
;
405 prom_getstring(prom_root_node
, "name", namebuf
, 63); namebuf
[63] = 0;
407 struct pcic_sn2list
*p
;
409 for (p
= pcic_known_sysnames
; p
->sysname
!= NULL
; p
++) {
410 if (strcmp(namebuf
, p
->sysname
) == 0)
413 pcic
->pcic_imap
= p
->intmap
;
414 pcic
->pcic_imdim
= p
->mapdim
;
416 if (pcic
->pcic_imap
== NULL
) {
418 * We do not panic here for the sake of embedded systems.
420 printk("PCIC: System %s is unknown, cannot route interrupts\n",
427 static void __init
pcic_pbm_scan_bus(struct linux_pcic
*pcic
)
429 struct linux_pbm_info
*pbm
= &pcic
->pbm
;
431 pbm
->pci_bus
= pci_scan_bus(pbm
->pci_first_busno
, &pcic_ops
, pbm
);
432 #if 0 /* deadwood transplanted from sparc64 */
433 pci_fill_in_pbm_cookies(pbm
->pci_bus
, pbm
, pbm
->prom_node
);
434 pci_record_assignments(pbm
, pbm
->pci_bus
);
435 pci_assign_unassigned(pbm
, pbm
->pci_bus
);
436 pci_fixup_irq(pbm
, pbm
->pci_bus
);
441 * Main entry point from the PCI subsystem.
443 void __init
pcibios_init(void)
445 struct linux_pcic
*pcic
;
448 * PCIC should be initialized at start of the timer.
449 * So, here we report the presence of PCIC and do some magic passes.
456 * Switch off IOTLB translation.
458 writeb(PCI_DVMA_CONTROL_IOTLB_DISABLE
,
459 pcic
->pcic_regs
+PCI_DVMA_CONTROL
);
462 * Increase mapped size for PCI memory space (DMA access).
463 * Should be done in that order (size first, address second).
464 * Why we couldn't set up 4GB and forget about it? XXX
466 writel(0xF0000000UL
, pcic
->pcic_regs
+PCI_SIZE_0
);
467 writel(0+PCI_BASE_ADDRESS_SPACE_MEMORY
,
468 pcic
->pcic_regs
+PCI_BASE_ADDRESS_0
);
470 pcic_pbm_scan_bus(pcic
);
473 #ifdef CONFIG_SUN_JSFLASH
478 int pcic_present(void)
483 static int __init
pdev_to_pnode(struct linux_pbm_info
*pbm
,
484 struct pci_dev
*pdev
)
486 struct linux_prom_pci_registers regs
[PROMREG_MAX
];
488 int node
= prom_getchild(pbm
->prom_node
);
491 err
= prom_getproperty(node
, "reg",
492 (char *)®s
[0], sizeof(regs
));
493 if(err
!= 0 && err
!= -1) {
494 unsigned long devfn
= (regs
[0].which_io
>> 8) & 0xff;
495 if(devfn
== pdev
->devfn
)
498 node
= prom_getsibling(node
);
503 static inline struct pcidev_cookie
*pci_devcookie_alloc(void)
505 return kmalloc(sizeof(struct pcidev_cookie
), GFP_ATOMIC
);
508 static void pcic_map_pci_device(struct linux_pcic
*pcic
,
509 struct pci_dev
*dev
, int node
)
512 unsigned long address
;
516 if (node
== 0 || node
== -1) {
517 strcpy(namebuf
, "???");
519 prom_getstring(node
, "name", namebuf
, 63); namebuf
[63] = 0;
522 for (j
= 0; j
< 6; j
++) {
523 address
= dev
->resource
[j
].start
;
524 if (address
== 0) break; /* are sequential */
525 flags
= dev
->resource
[j
].flags
;
526 if ((flags
& IORESOURCE_IO
) != 0) {
527 if (address
< 0x10000) {
529 * A device responds to I/O cycles on PCI.
530 * We generate these cycles with memory
531 * access into the fixed map (phys 0x30000000).
533 * Since a device driver does not want to
534 * do ioremap() before accessing PC-style I/O,
535 * we supply virtual, ready to access address.
537 * Ebus devices do not come here even if
538 * CheerIO makes a similar conversion.
539 * See ebus.c for details.
541 * Note that check_region()/request_region()
542 * work for these devices.
544 * XXX Neat trick, but it's a *bad* idea
545 * to shit into regions like that.
546 * What if we want to allocate one more
547 * PCI base address...
549 dev
->resource
[j
].start
=
550 pcic
->pcic_io
+ address
;
551 dev
->resource
[j
].end
= 1; /* XXX */
552 dev
->resource
[j
].flags
=
553 (flags
& ~IORESOURCE_IO
) | IORESOURCE_MEM
;
556 * OOPS... PCI Spec allows this. Sun does
557 * not have any devices getting above 64K
558 * so it must be user with a weird I/O
559 * board in a PCI slot. We must remap it
560 * under 64K but it is not done yet. XXX
562 printk("PCIC: Skipping I/O space at 0x%lx,"
563 "this will Oops if a driver attaches;"
564 "device '%s' (%x,%x)\n", address
, namebuf
,
565 dev
->device
, dev
->vendor
);
572 pcic_fill_irq(struct linux_pcic
*pcic
, struct pci_dev
*dev
, int node
)
574 struct pcic_ca2irq
*p
;
576 char namebuf
[64]; /* P3 remove */
578 if (node
== 0 || node
== -1) {
579 strcpy(namebuf
, "???");
581 prom_getstring(node
, "name", namebuf
, sizeof(namebuf
)); /* P3 remove */
584 if ((p
= pcic
->pcic_imap
) == 0) {
588 for (i
= 0; i
< pcic
->pcic_imdim
; i
++) {
589 if (p
->busno
== dev
->bus
->number
&& p
->devfn
== dev
->devfn
)
593 if (i
>= pcic
->pcic_imdim
) {
594 printk("PCIC: device %s devfn %02x:%02x not found in %d\n",
595 namebuf
, dev
->bus
->number
, dev
->devfn
, pcic
->pcic_imdim
);
601 if (i
>= 0 && i
< 4) {
602 ivec
= readw(pcic
->pcic_regs
+PCI_INT_SELECT_LO
);
603 dev
->irq
= ivec
>> (i
<< 2) & 0xF;
604 } else if (i
>= 4 && i
< 8) {
605 ivec
= readw(pcic
->pcic_regs
+PCI_INT_SELECT_HI
);
606 dev
->irq
= ivec
>> ((i
-4) << 2) & 0xF;
607 } else { /* Corrupted map */
608 printk("PCIC: BAD PIN %d\n", i
); for (;;) {}
610 /* P3 */ /* printk("PCIC: device %s pin %d ivec 0x%x irq %x\n", namebuf, i, ivec, dev->irq); */
613 * dev->irq=0 means PROM did not bother to program the upper
614 * half of PCIC. This happens on JS-E with PROM 3.11, for instance.
616 if (dev
->irq
== 0 || p
->force
) {
617 if (p
->irq
== 0 || p
->irq
>= 15) { /* Corrupted map */
618 printk("PCIC: BAD IRQ %d\n", p
->irq
); for (;;) {}
620 printk("PCIC: setting irq %x for device (%x,%x)\n",
621 p
->irq
, dev
->device
, dev
->vendor
);
626 ivec
= readw(pcic
->pcic_regs
+PCI_INT_SELECT_HI
);
627 ivec
&= ~(0xF << ((i
- 4) << 2));
628 ivec
|= p
->irq
<< ((i
- 4) << 2);
629 writew(ivec
, pcic
->pcic_regs
+PCI_INT_SELECT_HI
);
631 ivec
= readw(pcic
->pcic_regs
+PCI_INT_SELECT_LO
);
632 ivec
&= ~(0xF << (i
<< 2));
633 ivec
|= p
->irq
<< (i
<< 2);
634 writew(ivec
, pcic
->pcic_regs
+PCI_INT_SELECT_LO
);
642 * Normally called from {do_}pci_scan_bus...
644 void __init
pcibios_fixup_bus(struct pci_bus
*bus
)
646 struct list_head
*walk
;
647 int i
, has_io
, has_mem
;
649 struct linux_pcic
*pcic
;
650 /* struct linux_pbm_info* pbm = &pcic->pbm; */
652 struct pcidev_cookie
*pcp
;
655 printk("pcibios_fixup_bus: no PCIC\n");
661 * Next crud is an equivalent of pbm = pcic_bus_to_pbm(bus);
663 if (bus
->number
!= 0) {
664 printk("pcibios_fixup_bus: nonzero bus 0x%x\n", bus
->number
);
668 walk
= &bus
->devices
;
669 for (walk
= walk
->next
; walk
!= &bus
->devices
; walk
= walk
->next
) {
670 struct pci_dev
*dev
= pci_dev_b(walk
);
673 * Comment from i386 branch:
674 * There are buggy BIOSes that forget to enable I/O and memory
675 * access to PCI devices. We try to fix this, but we need to
676 * be sure that the BIOS didn't forget to assign an address
677 * to the device. [mj]
678 * OBP is a case of such BIOS :-)
680 has_io
= has_mem
= 0;
682 unsigned long f
= dev
->resource
[i
].flags
;
683 if (f
& IORESOURCE_IO
) {
685 } else if (f
& IORESOURCE_MEM
)
688 pcic_read_config_word(dev
, PCI_COMMAND
, &cmd
);
689 if (has_io
&& !(cmd
& PCI_COMMAND_IO
)) {
690 printk("PCIC: Enabling I/O for device %02x:%02x\n",
691 dev
->bus
->number
, dev
->devfn
);
692 cmd
|= PCI_COMMAND_IO
;
693 pcic_write_config_word(dev
, PCI_COMMAND
, cmd
);
695 if (has_mem
&& !(cmd
& PCI_COMMAND_MEMORY
)) {
696 printk("PCIC: Enabling memory for device %02x:%02x\n",
697 dev
->bus
->number
, dev
->devfn
);
698 cmd
|= PCI_COMMAND_MEMORY
;
699 pcic_write_config_word(dev
, PCI_COMMAND
, cmd
);
702 node
= pdev_to_pnode(&pcic
->pbm
, dev
);
707 pcp
= pci_devcookie_alloc();
708 pcp
->pbm
= &pcic
->pbm
;
709 pcp
->prom_node
= node
;
712 /* fixing I/O to look like memory */
713 if ((dev
->class>>16) != PCI_BASE_CLASS_BRIDGE
)
714 pcic_map_pci_device(pcic
, dev
, node
);
716 pcic_fill_irq(pcic
, dev
, node
);
721 * pcic_pin_to_irq() is exported to ebus.c.
724 pcic_pin_to_irq(unsigned int pin
, char *name
)
726 struct linux_pcic
*pcic
= &pcic0
;
731 ivec
= readw(pcic
->pcic_regs
+PCI_INT_SELECT_LO
);
732 irq
= ivec
>> (pin
<< 2) & 0xF;
733 } else if (pin
< 8) {
734 ivec
= readw(pcic
->pcic_regs
+PCI_INT_SELECT_HI
);
735 irq
= ivec
>> ((pin
-4) << 2) & 0xF;
736 } else { /* Corrupted map */
737 printk("PCIC: BAD PIN %d FOR %s\n", pin
, name
);
738 for (;;) {} /* XXX Cannot panic properly in case of PROLL */
740 /* P3 */ /* printk("PCIC: dev %s pin %d ivec 0x%x irq %x\n", name, pin, ivec, irq); */
744 /* Makes compiler happy */
745 static volatile int pcic_timer_dummy
;
747 static void pcic_clear_clock_irq(void)
749 pcic_timer_dummy
= readl(pcic0
.pcic_regs
+PCI_SYS_LIMIT
);
752 static void pcic_timer_handler (int irq
, void *h
, struct pt_regs
*regs
)
754 pcic_clear_clock_irq();
758 #define USECS_PER_JIFFY 10000 /* We have 100HZ "standard" timer for sparc */
759 #define TICK_TIMER_LIMIT ((100*1000000/4)/100)
761 void __init
pci_time_init(void)
763 struct linux_pcic
*pcic
= &pcic0
;
767 do_get_fast_time
= pci_do_gettimeofday
;
768 /* A hack until do_gettimeofday prototype is moved to arch specific headers
769 and btfixupped. Patch do_gettimeofday with ba pci_do_gettimeofday; nop */
770 ((unsigned int *)do_gettimeofday
)[0] =
771 0x10800000 | ((((unsigned long)pci_do_gettimeofday
-
772 (unsigned long)do_gettimeofday
) >> 2) & 0x003fffff);
773 ((unsigned int *)do_gettimeofday
)[1] = 0x01000000;
774 BTFIXUPSET_CALL(bus_do_settimeofday
, pci_do_settimeofday
, BTFIXUPCALL_NORM
);
777 writel (TICK_TIMER_LIMIT
, pcic
->pcic_regs
+PCI_SYS_LIMIT
);
778 /* PROM should set appropriate irq */
779 v
= readb(pcic
->pcic_regs
+PCI_COUNTER_IRQ
);
780 timer_irq
= PCI_COUNTER_IRQ_SYS(v
);
781 writel (PCI_COUNTER_IRQ_SET(timer_irq
, 0),
782 pcic
->pcic_regs
+PCI_COUNTER_IRQ
);
783 irq
= request_irq(timer_irq
, pcic_timer_handler
,
784 (SA_INTERRUPT
| SA_STATIC_ALLOC
), "timer", NULL
);
786 prom_printf("time_init: unable to attach IRQ%d\n", timer_irq
);
792 static __inline__
unsigned long do_gettimeoffset(void)
794 struct tasklet_struct
*t
;
795 unsigned long offset
= 0;
798 * We devide all to 100
799 * to have microsecond resolution and to avoid overflow
801 unsigned long count
=
802 readl(pcic0
.pcic_regs
+PCI_SYS_COUNTER
) & ~PCI_SYS_COUNTER_OVERFLOW
;
803 count
= ((count
/100)*USECS_PER_JIFFY
) / (TICK_TIMER_LIMIT
/100);
805 t
= &bh_task_vec
[TIMER_BH
];
806 if (test_bit(TASKLET_STATE_SCHED
, &t
->state
))
808 return offset
+ count
;
811 extern volatile unsigned long wall_jiffies
;
813 static void pci_do_gettimeofday(struct timeval
*tv
)
819 tv
->tv_usec
+= do_gettimeoffset();
822 * xtime is atomically updated in timer_bh. The difference
823 * between jiffies and wall_jiffies is nonzero if the timer
824 * bottom half hasnt executed yet.
826 if ((jiffies
- wall_jiffies
) != 0)
827 tv
->tv_usec
+= USECS_PER_JIFFY
;
829 restore_flags(flags
);
831 if (tv
->tv_usec
>= 1000000) {
832 tv
->tv_usec
-= 1000000;
837 static void pci_do_settimeofday(struct timeval
*tv
)
840 tv
->tv_usec
-= do_gettimeoffset();
841 if(tv
->tv_usec
< 0) {
842 tv
->tv_usec
+= 1000000;
846 time_adjust
= 0; /* stop active adjtime() */
847 time_status
|= STA_UNSYNC
;
848 time_maxerror
= NTP_PHASE_LIMIT
;
849 time_esterror
= NTP_PHASE_LIMIT
;
854 static void watchdog_reset() {
855 writeb(0, pcic
->pcic_regs
+PCI_SYS_STATUS
);
860 * Other archs parse arguments here.
862 char * __init
pcibios_setup(char *str
)
869 void pcibios_update_resource(struct pci_dev
*pdev
, struct resource
*res1
,
870 struct resource
*res2
, int index
)
875 void pcibios_update_irq(struct pci_dev
*pdev
, int irq
)
879 unsigned long resource_fixup(struct pci_dev
*pdev
, struct resource
*res
,
880 unsigned long start
, unsigned long size
)
885 void pcibios_fixup_pbus_ranges(struct pci_bus
*pbus
,
886 struct pbus_set_ranges_data
*pranges
)
891 void pcibios_align_resource(void *data
, struct resource
*res
, unsigned long size
)
895 int pcibios_enable_device(struct pci_dev
*pdev
)
903 void pcic_nmi(unsigned int pend
, struct pt_regs
*regs
)
906 pend
= flip_dword(pend
);
908 if (!pcic_speculative
|| (pend
& PCI_SYS_INT_PENDING_PIO
) == 0) {
910 * XXX On CP-1200 PCI #SERR may happen, we do not know
911 * what to do about it yet.
913 printk("Aiee, NMI pend 0x%x pc 0x%x spec %d, hanging\n",
914 pend
, (int)regs
->pc
, pcic_speculative
);
917 pcic_speculative
= 0;
919 regs
->pc
= regs
->npc
;
924 * XXX Gleb wrote me that he needs this for X server (only).
925 * Since we successfuly use XF86_FBDev, we do not need these anymore.
927 * Following code added to handle extra PCI-related system calls
929 asmlinkage
int sys_pciconfig_read(unsigned long bus
,
936 unsigned short ushort
;
946 pcibios_read_config_byte(bus
, dfn
, off
, &ubyte
);
947 put_user(ubyte
, (unsigned char *)buf
);
950 pcibios_read_config_word(bus
, dfn
, off
, &ushort
);
951 put_user(ushort
, (unsigned short *)buf
);
954 pcibios_read_config_dword(bus
, dfn
, off
, &uint
);
955 put_user(uint
, (unsigned int *)buf
);
967 asmlinkage
int sys_pciconfig_write(unsigned long bus
,
974 unsigned short ushort
;
984 err
= get_user(ubyte
, (unsigned char *)buf
);
987 pcibios_write_config_byte(bus
, dfn
, off
, ubyte
);
991 err
= get_user(ushort
, (unsigned short *)buf
);
994 pcibios_write_config_byte(bus
, dfn
, off
, ushort
);
998 err
= get_user(uint
, (unsigned int *)buf
);
1001 pcibios_write_config_byte(bus
, dfn
, off
, uint
);
1014 static inline unsigned long get_irqmask(int irq_nr
)
1019 static inline char *pcic_irq_itoa(unsigned int irq
)
1021 static char buff
[16];
1022 sprintf(buff
, "%d", irq
);
1026 static void pcic_disable_irq(unsigned int irq_nr
)
1028 unsigned long mask
, flags
;
1030 mask
= get_irqmask(irq_nr
);
1031 save_and_cli(flags
);
1032 writel(mask
, pcic0
.pcic_regs
+PCI_SYS_INT_TARGET_MASK_SET
);
1033 restore_flags(flags
);
1036 static void pcic_enable_irq(unsigned int irq_nr
)
1038 unsigned long mask
, flags
;
1040 mask
= get_irqmask(irq_nr
);
1041 save_and_cli(flags
);
1042 writel(mask
, pcic0
.pcic_regs
+PCI_SYS_INT_TARGET_MASK_CLEAR
);
1043 restore_flags(flags
);
1046 static void pcic_clear_profile_irq(int cpu
)
1048 printk("PCIC: unimplemented code: FILE=%s LINE=%d", __FILE__
, __LINE__
);
1051 static void pcic_load_profile_irq(int cpu
, unsigned int limit
)
1053 printk("PCIC: unimplemented code: FILE=%s LINE=%d", __FILE__
, __LINE__
);
1056 /* We assume the caller is local cli()'d when these are called, or else
1057 * very bizarre behavior will result.
1059 static void pcic_disable_pil_irq(unsigned int pil
)
1061 writel(get_irqmask(pil
), pcic0
.pcic_regs
+PCI_SYS_INT_TARGET_MASK_SET
);
1064 static void pcic_enable_pil_irq(unsigned int pil
)
1066 writel(get_irqmask(pil
), pcic0
.pcic_regs
+PCI_SYS_INT_TARGET_MASK_CLEAR
);
1069 void __init
sun4m_pci_init_IRQ(void)
1071 BTFIXUPSET_CALL(enable_irq
, pcic_enable_irq
, BTFIXUPCALL_NORM
);
1072 BTFIXUPSET_CALL(disable_irq
, pcic_disable_irq
, BTFIXUPCALL_NORM
);
1073 BTFIXUPSET_CALL(enable_pil_irq
, pcic_enable_pil_irq
, BTFIXUPCALL_NORM
);
1074 BTFIXUPSET_CALL(disable_pil_irq
, pcic_disable_pil_irq
, BTFIXUPCALL_NORM
);
1075 BTFIXUPSET_CALL(clear_clock_irq
, pcic_clear_clock_irq
, BTFIXUPCALL_NORM
);
1076 BTFIXUPSET_CALL(clear_profile_irq
, pcic_clear_profile_irq
, BTFIXUPCALL_NORM
);
1077 BTFIXUPSET_CALL(load_profile_irq
, pcic_load_profile_irq
, BTFIXUPCALL_NORM
);
1078 BTFIXUPSET_CALL(__irq_itoa
, pcic_irq_itoa
, BTFIXUPCALL_NORM
);
1081 int pcibios_assign_resource(struct pci_dev
*pdev
, int resource
)
1087 * This probably belongs here rather than ioport.c because
1088 * we do not want this crud linked into SBus kernels.
1089 * Also, think for a moment about likes of floppy.c that
1090 * include architecture specific parts. They may want to redefine ins/outs.
1092 * We do not use horroble macroses here because we want to
1093 * advance pointer by sizeof(size).
1095 void outsb(unsigned long addr
, const void *src
, unsigned long count
) {
1098 writeb(*(const char *)src
, addr
);
1104 void outsw(unsigned long addr
, const void *src
, unsigned long count
) {
1107 writew(*(const short *)src
, addr
);
1113 void outsl(unsigned long addr
, const void *src
, unsigned long count
) {
1116 writel(*(const long *)src
, addr
);
1122 void insb(unsigned long addr
, void *dst
, unsigned long count
) {
1125 *(unsigned char *)dst
= readb(addr
);
1131 void insw(unsigned long addr
, void *dst
, unsigned long count
) {
1134 *(unsigned short *)dst
= readw(addr
);
1140 void insl(unsigned long addr
, void *dst
, unsigned long count
) {
1144 * XXX I am sure we are in for an unaligned trap here.
1146 *(unsigned long *)dst
= readl(addr
);