3 * snull.h -- definitions for the network module
5 * Copyright (C) 2001 Alessandro Rubini and Jonathan Corbet
6 * Copyright (C) 2001 O'Reilly & Associates
8 * The source code in this file can be freely used, adapted,
9 * and redistributed in source or binary form, so long as an
10 * acknowledgment appears in derived source files. The citation
11 * should list that the code comes from the book "Linux Device
12 * Drivers" by Alessandro Rubini and Jonathan Corbet, published
13 * by O'Reilly & Associates. No warranty is attached;
14 * we cannot take responsibility for errors or fitness for use.
17 /* version dependencies have been confined to a separate file */
19 #define SGI_MFE (MACE_BASE+MACE_ENET)
22 /* Tunable parameters */
23 #define TX_RING_ENTRIES 64 /* 64-512?*/
25 #define RX_RING_ENTRIES 16 /* Do not change */
26 /* Internal constants */
27 #define TX_RING_BUFFER_SIZE (TX_RING_ENTRIES*sizeof(tx_packet))
28 #define RX_BUFFER_SIZE 1546 /* ethenet packet size */
29 #define METH_RX_BUFF_SIZE 4096
30 #define METH_RX_HEAD 34 /* status + 3 quad garbage-fill + 2 byte zero-pad */
31 #define RX_BUFFER_OFFSET (sizeof(rx_status_vector)+2) /* staus vector + 2 bytes of padding */
32 #define RX_BUCKET_SIZE 256
36 /* For more detailed explanations of what each field menas,
37 see Nick's great comments to #defines below (or docs, if
38 you are lucky enough toget hold of them :)*/
40 /* tx status vector is written over tx command header upon
43 typedef struct tx_status_vector
{
44 u64 sent
:1; /* always set to 1...*/
45 u64 pad0
:34;/* always set to 0 */
46 u64 flags
:9; /*I'm too lazy to specify each one separately at the moment*/
47 u64 col_retry_cnt
:4; /*collision retry count*/
48 u64 len
:16; /*Transmit length in bytes*/
52 * Each packet is 128 bytes long.
53 * It consists of header, 0-3 concatination
54 * buffer pointers and up to 120 data bytes.
56 typedef struct tx_packet_hdr
{
57 u64 pad1
:36; /*should be filled with 0 */
58 u64 cat_ptr3_valid
:1, /*Concatination pointer valid flags*/
61 u64 tx_int_flag
:1; /*Generate TX intrrupt when packet has been sent*/
62 u64 term_dma_flag
:1; /*Terminate transmit DMA on transmit abort conditions*/
63 u64 data_offset
:7; /*Starting byte offset in ring data block*/
64 u64 data_len
:16; /*Length of valid data in bytes-1*/
66 typedef union tx_cat_ptr
{
68 u64 pad2
:16; /* should be 0 */
69 u64 len
:16; /*length of buffer data - 1*/
70 u64 start_addr
:29; /*Physical starting address*/
71 u64 pad1
:3; /* should be zero */
76 typedef struct tx_packet
{
83 tx_cat_ptr cat_buf
[3];
88 typedef union rx_status_vector
{
90 u64 pad1
:1;/*fill it with ones*/
91 u64 pad2
:15;/*fill with 0*/
95 u64 mcast_addr_match
:1;
96 u64 carrier_event_seen
:1;
98 u64 long_event_seen
:1;
99 u64 invalid_preamble
:1;
104 u64 rx_code_violation
:1;
110 typedef struct rx_packet
{
111 rx_status_vector status
;
112 u64 pad
[3]; /* For whatever reason, there needs to be 4 double-word offset */
114 char buf
[METH_RX_BUFF_SIZE
-sizeof(rx_status_vector
)-3*sizeof(u64
)-sizeof(u16
)];/* data */
117 #define TX_INFO_RPTR 0x00FF0000
118 #define TX_INFO_WPTR 0x000000FF
119 typedef struct meth_regs
{
120 u64 mac_ctrl
; /*0x00,rw,31:0*/
121 u64 int_flags
; /*0x08,rw,30:0*/
122 u64 dma_ctrl
; /*0x10,rw,15:0*/
123 u64 timer
; /*0x18,rw,5:0*/
124 u64 int_tx
; /*0x20,wo,0:0*/
125 u64 int_rx
; /*0x28,wo,9:4*/
126 u64 tx_info
; /*0x30,rw,31:0*/
127 u64 tx_info_al
; /*0x38,rw,31:0*/
128 u64 rx_buff
; /*0x40,ro,23:0*/
129 u64 rx_buff_al1
; /*0x48,ro,23:0*/
130 u64 rx_buff_al2
; /*0x50,ro,23:0*/
131 u64 int_update
; /*0x58,wo,31:0*/
133 u32 phy_data
; /*0x60,rw,16:0*/
135 u32 phy_registers
; /*0x68,rw,9:0*/
136 u64 phy_trans_go
; /*0x70,wo,0:0*/
137 u64 backoff_seed
; /*0x78,wo,10:0*/
138 u64 imq_reserved
[4];/*0x80,ro,64:0(x4)*/
139 /*===================================*/
140 u64 mac_addr
; /*0xA0,rw,47:0, I think it's MAC address, but I'm not sure*/
141 u64 mcast_addr
; /*0xA8,rw,47:0, This seems like secondary MAC address*/
142 u64 mcast_filter
; /*0xB0,rw,63:0*/
143 u64 tx_ring_base
; /*0xB8,rw,31:13*/
144 /* Following are read-only debugging info register */
145 u64 tx_pkt1_hdr
; /*0xC0,ro,63:0*/
146 u64 tx_pkt1_ptr
[3]; /*0xC8,ro,63:0(x3)*/
147 u64 tx_pkt2_hdr
; /*0xE0,ro,63:0*/
148 u64 tx_pkt2_ptr
[3]; /*0xE8,ro,63:0(x3)*/
149 /*===================================*/
155 /* Bits in METH_MAC */
157 #define SGI_MAC_RESET BIT(0) /* 0: MAC110 active in run mode, 1: Global reset signal to MAC110 core is active */
158 #define METH_PHY_FDX BIT(1) /* 0: Disable full duplex, 1: Enable full duplex */
159 #define METH_PHY_LOOP BIT(2) /* 0: Normal operation, follows 10/100mbit and M10T/MII select, 1: loops internal MII bus */
160 /* selects ignored */
161 #define METH_100MBIT BIT(3) /* 0: 10meg mode, 1: 100meg mode */
162 #define METH_PHY_MII BIT(4) /* 0: MII selected, 1: SIA selected */
163 /* Note: when loopback is set this bit becomes collision control. Setting this bit will */
164 /* cause a collision to be reported. */
166 /* Bits 5 and 6 are used to determine the the Destination address filter mode */
167 #define METH_ACCEPT_MY 0 /* 00: Accept PHY address only */
168 #define METH_ACCEPT_MCAST 0x20 /* 01: Accept physical, broadcast, and multicast filter matches only */
169 #define METH_ACCEPT_AMCAST 0x40 /* 10: Accept physical, broadcast, and all multicast packets */
170 #define METH_PROMISC 0x60 /* 11: Promiscious mode */
172 #define METH_PHY_LINK_FAIL BIT(7) /* 0: Link failure detection disabled, 1: Hardware scans for link failure in PHY */
174 #define METH_MAC_IPG 0x1ffff00
176 #define METH_DEFAULT_IPG ((17<<15) | (11<<22) | (21<<8))
177 /* 0x172e5c00 */ /* 23, 23, 23 */ /*0x54A9500 *//*21,21,21*/
178 /* Bits 8 through 14 are used to determine Inter-Packet Gap between "Back to Back" packets */
179 /* The gap depends on the clock speed of the link, 80ns per increment for 100baseT, 800ns */
180 /* per increment for 10BaseT */
182 /* Bits 15 through 21 are used to determine IPGR1 */
184 /* Bits 22 through 28 are used to determine IPGR2 */
186 #define METH_REV_SHIFT 29 /* Bits 29 through 31 are used to determine the revision */
187 /* 000: Inital revision */
188 /* 001: First revision, Improved TX concatenation */
191 /* DMA control bits */
192 #define METH_RX_OFFSET_SHIFT 12 /* Bits 12:14 of DMA control register indicate starting offset of packet data for RX operation */
193 #define METH_RX_DEPTH_SHIFT 4 /* Bits 8:4 define RX fifo depth -- when # of RX fifo entries != depth, interrupt is generted */
195 #define METH_DMA_TX_EN BIT(1) /* enable TX DMA */
196 #define METH_DMA_TX_INT_EN BIT(0) /* enable TX Buffer Empty interrupt */
197 #define METH_DMA_RX_EN BIT(15) /* Enable RX */
198 #define METH_DMA_RX_INT_EN BIT(9) /* Enable interrupt on RX packet */
200 /* RX FIFO MCL Info bits */
201 #define METH_RX_FIFO_WPTR(x) ((x>>16)&0xF)
202 #define METH_RX_FIFO_RPTR(x) ((x>>8)&0xF)
203 #define METH_RX_FIFO_DEPTH(x) (x&0x1F)
207 #define METH_RX_ST_VALID BIT(63)
208 #define METH_RX_ST_RCV_CODE_VIOLATION BIT(16)
209 #define METH_RX_ST_DRBL_NBL BIT(17)
210 #define METH_RX_ST_CRC_ERR BIT(18)
211 #define METH_RX_ST_MCAST_PKT BIT(19)
212 #define METH_RX_ST_BCAST_PKT BIT(20)
213 #define METH_RX_ST_INV_PREAMBLE_CTX BIT(21)
214 #define METH_RX_ST_LONG_EVT_SEEN BIT(22)
215 #define METH_RX_ST_BAD_PACKET BIT(23)
216 #define METH_RX_ST_CARRIER_EVT_SEEN BIT(24)
217 #define METH_RX_ST_MCAST_FILTER_MATCH BIT(25)
218 #define METH_RX_ST_PHYS_ADDR_MATCH BIT(26)
220 #define METH_RX_STATUS_ERRORS \
222 METH_RX_ST_RCV_CODE_VIOLATION| \
223 METH_RX_ST_CRC_ERR| \
224 METH_RX_ST_INV_PREAMBLE_CTX| \
225 METH_RX_ST_LONG_EVT_SEEN| \
226 METH_RX_ST_BAD_PACKET| \
227 METH_RX_ST_CARRIER_EVT_SEEN \
229 /* Bits in METH_INT */
230 /* Write _1_ to corresponding bit to clear */
231 #define METH_INT_TX_EMPTY BIT(0) /* 0: No interrupt pending, 1: The TX ring buffer is empty */
232 #define METH_INT_TX_PKT BIT(1) /* 0: No interrupt pending */
233 /* 1: A TX message had the INT request bit set, the packet has been sent. */
234 #define METH_INT_TX_LINK_FAIL BIT(2) /* 0: No interrupt pending, 1: PHY has reported a link failure */
235 #define METH_INT_MEM_ERROR BIT(3) /* 0: No interrupt pending */
236 /* 1: A memory error occurred durring DMA, DMA stopped, Fatal */
237 #define METH_INT_TX_ABORT BIT(4) /* 0: No interrupt pending, 1: The TX aborted operation, DMA stopped, FATAL */
238 #define METH_INT_RX_THRESHOLD BIT(5) /* 0: No interrupt pending, 1: Selected receive threshold condition Valid */
239 #define METH_INT_RX_UNDERFLOW BIT(6) /* 0: No interrupt pending, 1: FIFO was empty, packet could not be queued */
240 #define METH_INT_RX_OVERFLOW BIT(7) /* 0: No interrupt pending, 1: DMA FIFO Overflow, DMA stopped, FATAL */
242 /*#define METH_INT_RX_RPTR_MASK 0x0001F00*/ /* Bits 8 through 12 alias of RX read-pointer */
243 #define METH_INT_RX_RPTR_MASK 0x0000F00 /* Bits 8 through 11 alias of RX read-pointer - so, is Rx FIFO 16 or 32 entry?*/
245 /* Bits 13 through 15 are always 0. */
247 #define METH_INT_TX_RPTR_MASK 0x1FF0000 /* Bits 16 through 24 alias of TX read-pointer */
249 #define METH_INT_SEQ_MASK 0x2E000000 /* Bits 25 through 29 are the starting seq number for the message at the */
250 /* top of the queue */
252 #define METH_INT_ERROR (METH_INT_TX_LINK_FAIL| \
253 METH_INT_MEM_ERROR| \
255 METH_INT_RX_OVERFLOW| \
256 METH_INT_RX_UNDERFLOW)
258 #define METH_INT_MCAST_HASH BIT(30) /* If RX DMA is enabled the hash select logic output is latched here */
261 #define METH_TX_STATUS_DONE BIT(23) /* Packet was transmitted successfully */
263 /* Tx command header bits */
264 #define METH_TX_CMD_INT_EN BIT(24) /* Generate TX interrupt when packet is sent */
266 /* Phy MDIO interface busy flag */
267 #define MDIO_BUSY BIT(16)
268 #define MDIO_DATA_MASK 0xFFFF
270 #define PHY_QS6612X 0x0181441 /* Quality TX */
271 #define PHY_ICS1889 0x0015F41 /* ICS FX */
272 #define PHY_ICS1890 0x0015F42 /* ICS TX */
273 #define PHY_DP83840 0x20005C0 /* National TX */
275 #define ADVANCE_RX_PTR(x) x=(x+1)&(RX_RING_ENTRIES-1)