2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
7 * Copyright (C) 1996 by Paul M. Antoine
8 * Copyright (C) 1999 Silicon Graphics
9 * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000 MIPS Technologies, Inc.
15 #include <linux/types.h>
16 #include <linux/irqflags.h>
18 #include <asm/addrspace.h>
19 #include <asm/barrier.h>
20 #include <asm/cpu-features.h>
22 #include <asm/ptrace.h>
27 * switch_to(n) should switch tasks to task nr n, first
28 * checking that n isn't the current task, in which case it does nothing.
30 extern asmlinkage
void *resume(void *last
, void *next
, void *next_ti
);
34 #ifdef CONFIG_MIPS_MT_FPAFF
37 * Handle the scheduler resume end of FPU affinity management. We do this
38 * inline to try to keep the overhead down. If we have been forced to run on
39 * a "CPU" with an FPU because of a previous high level of FP computation,
40 * but did not actually use the FPU during the most recent time-slice (CU1
41 * isn't set), we undo the restriction on cpus_allowed.
43 * We're not calling set_cpus_allowed() here, because we have no need to
44 * force prompt migration - we're already switching the current CPU to a
48 #define switch_to(prev,next,last) \
51 (prev->thread.mflags & MF_FPUBOUND) && \
52 (!(KSTK_STATUS(prev) & ST0_CU1))) { \
53 prev->thread.mflags &= ~MF_FPUBOUND; \
54 prev->cpus_allowed = prev->thread.user_cpus_allowed; \
58 next->thread.emulated_fp = 0; \
59 (last) = resume(prev, next, next->thread_info); \
61 __restore_dsp(current); \
65 #define switch_to(prev,next,last) \
69 (last) = resume(prev, next, task_thread_info(next)); \
71 __restore_dsp(current); \
76 * On SMP systems, when the scheduler does migration-cost autodetection,
77 * it needs a way to flush as much of the CPU's caches as possible.
81 static inline void sched_cacheflush(void)
85 static inline unsigned long __xchg_u32(volatile int * m
, unsigned int val
)
89 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
94 "1: ll %0, %3 # xchg_u32 \n"
101 : "=&r" (retval
), "=m" (*m
), "=&r" (dummy
)
102 : "R" (*m
), "Jr" (val
)
104 } else if (cpu_has_llsc
) {
107 __asm__
__volatile__(
109 "1: ll %0, %3 # xchg_u32 \n"
116 : "=&r" (retval
), "=m" (*m
), "=&r" (dummy
)
117 : "R" (*m
), "Jr" (val
)
122 local_irq_save(flags
);
125 local_irq_restore(flags
); /* implies memory barrier */
134 static inline __u64
__xchg_u64(volatile __u64
* m
, __u64 val
)
138 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
141 __asm__
__volatile__(
143 "1: lld %0, %3 # xchg_u64 \n"
148 : "=&r" (retval
), "=m" (*m
), "=&r" (dummy
)
149 : "R" (*m
), "Jr" (val
)
151 } else if (cpu_has_llsc
) {
154 __asm__
__volatile__(
156 "1: lld %0, %3 # xchg_u64 \n"
161 : "=&r" (retval
), "=m" (*m
), "=&r" (dummy
)
162 : "R" (*m
), "Jr" (val
)
167 local_irq_save(flags
);
170 local_irq_restore(flags
); /* implies memory barrier */
178 extern __u64
__xchg_u64_unsupported_on_32bit_kernels(volatile __u64
* m
, __u64 val
);
179 #define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
182 /* This function doesn't exist, so you'll get a linker error
183 if something tries to do an invalid xchg(). */
184 extern void __xchg_called_with_bad_pointer(void);
186 static inline unsigned long __xchg(unsigned long x
, volatile void * ptr
, int size
)
190 return __xchg_u32(ptr
, x
);
192 return __xchg_u64(ptr
, x
);
194 __xchg_called_with_bad_pointer();
198 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
199 #define tas(ptr) (xchg((ptr),1))
201 #define __HAVE_ARCH_CMPXCHG 1
203 static inline unsigned long __cmpxchg_u32(volatile int * m
, unsigned long old
,
208 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
209 __asm__
__volatile__(
213 "1: ll %0, %2 # __cmpxchg_u32 \n"
214 " bne %0, %z3, 2f \n"
222 : "=&r" (retval
), "=R" (*m
)
223 : "R" (*m
), "Jr" (old
), "Jr" (new)
225 } else if (cpu_has_llsc
) {
226 __asm__
__volatile__(
230 "1: ll %0, %2 # __cmpxchg_u32 \n"
231 " bne %0, %z3, 2f \n"
239 : "=&r" (retval
), "=R" (*m
)
240 : "R" (*m
), "Jr" (old
), "Jr" (new)
245 local_irq_save(flags
);
249 local_irq_restore(flags
); /* implies memory barrier */
258 static inline unsigned long __cmpxchg_u64(volatile int * m
, unsigned long old
,
263 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
264 __asm__
__volatile__(
268 "1: lld %0, %2 # __cmpxchg_u64 \n"
269 " bne %0, %z3, 2f \n"
275 : "=&r" (retval
), "=R" (*m
)
276 : "R" (*m
), "Jr" (old
), "Jr" (new)
278 } else if (cpu_has_llsc
) {
279 __asm__
__volatile__(
283 "1: lld %0, %2 # __cmpxchg_u64 \n"
284 " bne %0, %z3, 2f \n"
290 : "=&r" (retval
), "=R" (*m
)
291 : "R" (*m
), "Jr" (old
), "Jr" (new)
296 local_irq_save(flags
);
300 local_irq_restore(flags
); /* implies memory barrier */
308 extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels(
309 volatile int * m
, unsigned long old
, unsigned long new);
310 #define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels
313 /* This function doesn't exist, so you'll get a linker error
314 if something tries to do an invalid cmpxchg(). */
315 extern void __cmpxchg_called_with_bad_pointer(void);
317 static inline unsigned long __cmpxchg(volatile void * ptr
, unsigned long old
,
318 unsigned long new, int size
)
322 return __cmpxchg_u32(ptr
, old
, new);
324 return __cmpxchg_u64(ptr
, old
, new);
326 __cmpxchg_called_with_bad_pointer();
330 #define cmpxchg(ptr,old,new) ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
332 extern void set_handler (unsigned long offset
, void *addr
, unsigned long len
);
333 extern void set_uncached_handler (unsigned long offset
, void *addr
, unsigned long len
);
334 extern void *set_vi_handler (int n
, void *addr
);
335 extern void *set_except_vector(int n
, void *addr
);
336 extern unsigned long ebase
;
337 extern void per_cpu_trap_init(void);
339 extern NORET_TYPE
void die(const char *, struct pt_regs
*);
341 static inline void die_if_kernel(const char *str
, struct pt_regs
*regs
)
343 if (unlikely(!user_mode(regs
)))
347 extern int stop_a_enabled
;
350 * See include/asm-ia64/system.h; prevents deadlock on SMP
353 #define __ARCH_WANT_UNLOCKED_CTXSW
355 #define arch_align_stack(x) (x)
357 #endif /* _ASM_SYSTEM_H */