[PATCH] i386: fall back to sensible CPU model name
[linux-2.6/linux-mips.git] / arch / i386 / kernel / cpu / common.c
blob7e3d6b6a4e963bc7db6beee8dccbdd94ae96532e
1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
4 #include <linux/smp.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/bootmem.h>
8 #include <asm/semaphore.h>
9 #include <asm/processor.h>
10 #include <asm/i387.h>
11 #include <asm/msr.h>
12 #include <asm/io.h>
13 #include <asm/mmu_context.h>
14 #ifdef CONFIG_X86_LOCAL_APIC
15 #include <asm/mpspec.h>
16 #include <asm/apic.h>
17 #include <mach_apic.h>
18 #endif
20 #include "cpu.h"
22 DEFINE_PER_CPU(struct Xgt_desc_struct, cpu_gdt_descr);
23 EXPORT_PER_CPU_SYMBOL(cpu_gdt_descr);
25 DEFINE_PER_CPU(unsigned char, cpu_16bit_stack[CPU_16BIT_STACK_SIZE]);
26 EXPORT_PER_CPU_SYMBOL(cpu_16bit_stack);
28 static int cachesize_override __cpuinitdata = -1;
29 static int disable_x86_fxsr __cpuinitdata;
30 static int disable_x86_serial_nr __cpuinitdata = 1;
31 static int disable_x86_sep __cpuinitdata;
33 struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {};
35 extern int disable_pse;
37 static void default_init(struct cpuinfo_x86 * c)
39 /* Not much we can do here... */
40 /* Check if at least it has cpuid */
41 if (c->cpuid_level == -1) {
42 /* No cpuid. It must be an ancient CPU */
43 if (c->x86 == 4)
44 strcpy(c->x86_model_id, "486");
45 else if (c->x86 == 3)
46 strcpy(c->x86_model_id, "386");
50 static struct cpu_dev default_cpu = {
51 .c_init = default_init,
52 .c_vendor = "Unknown",
54 static struct cpu_dev * this_cpu = &default_cpu;
56 static int __init cachesize_setup(char *str)
58 get_option (&str, &cachesize_override);
59 return 1;
61 __setup("cachesize=", cachesize_setup);
63 int __cpuinit get_model_name(struct cpuinfo_x86 *c)
65 unsigned int *v;
66 char *p, *q;
68 if (cpuid_eax(0x80000000) < 0x80000004)
69 return 0;
71 v = (unsigned int *) c->x86_model_id;
72 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
73 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
74 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
75 c->x86_model_id[48] = 0;
77 /* Intel chips right-justify this string for some dumb reason;
78 undo that brain damage */
79 p = q = &c->x86_model_id[0];
80 while ( *p == ' ' )
81 p++;
82 if ( p != q ) {
83 while ( *p )
84 *q++ = *p++;
85 while ( q <= &c->x86_model_id[48] )
86 *q++ = '\0'; /* Zero-pad the rest */
89 return 1;
93 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
95 unsigned int n, dummy, ecx, edx, l2size;
97 n = cpuid_eax(0x80000000);
99 if (n >= 0x80000005) {
100 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
101 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
102 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
103 c->x86_cache_size=(ecx>>24)+(edx>>24);
106 if (n < 0x80000006) /* Some chips just has a large L1. */
107 return;
109 ecx = cpuid_ecx(0x80000006);
110 l2size = ecx >> 16;
112 /* do processor-specific cache resizing */
113 if (this_cpu->c_size_cache)
114 l2size = this_cpu->c_size_cache(c,l2size);
116 /* Allow user to override all this if necessary. */
117 if (cachesize_override != -1)
118 l2size = cachesize_override;
120 if ( l2size == 0 )
121 return; /* Again, no L2 cache is possible */
123 c->x86_cache_size = l2size;
125 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
126 l2size, ecx & 0xFF);
129 /* Naming convention should be: <Name> [(<Codename>)] */
130 /* This table only is used unless init_<vendor>() below doesn't set it; */
131 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
133 /* Look up CPU names by table lookup. */
134 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
136 struct cpu_model_info *info;
138 if ( c->x86_model >= 16 )
139 return NULL; /* Range check */
141 if (!this_cpu)
142 return NULL;
144 info = this_cpu->c_models;
146 while (info && info->family) {
147 if (info->family == c->x86)
148 return info->model_names[c->x86_model];
149 info++;
151 return NULL; /* Not found */
155 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early)
157 char *v = c->x86_vendor_id;
158 int i;
159 static int printed;
161 for (i = 0; i < X86_VENDOR_NUM; i++) {
162 if (cpu_devs[i]) {
163 if (!strcmp(v,cpu_devs[i]->c_ident[0]) ||
164 (cpu_devs[i]->c_ident[1] &&
165 !strcmp(v,cpu_devs[i]->c_ident[1]))) {
166 c->x86_vendor = i;
167 if (!early)
168 this_cpu = cpu_devs[i];
169 return;
173 if (!printed) {
174 printed++;
175 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
176 printk(KERN_ERR "CPU: Your system may be unstable.\n");
178 c->x86_vendor = X86_VENDOR_UNKNOWN;
179 this_cpu = &default_cpu;
183 static int __init x86_fxsr_setup(char * s)
185 disable_x86_fxsr = 1;
186 return 1;
188 __setup("nofxsr", x86_fxsr_setup);
191 static int __init x86_sep_setup(char * s)
193 disable_x86_sep = 1;
194 return 1;
196 __setup("nosep", x86_sep_setup);
199 /* Standard macro to see if a specific flag is changeable */
200 static inline int flag_is_changeable_p(u32 flag)
202 u32 f1, f2;
204 asm("pushfl\n\t"
205 "pushfl\n\t"
206 "popl %0\n\t"
207 "movl %0,%1\n\t"
208 "xorl %2,%0\n\t"
209 "pushl %0\n\t"
210 "popfl\n\t"
211 "pushfl\n\t"
212 "popl %0\n\t"
213 "popfl\n\t"
214 : "=&r" (f1), "=&r" (f2)
215 : "ir" (flag));
217 return ((f1^f2) & flag) != 0;
221 /* Probe for the CPUID instruction */
222 static int __cpuinit have_cpuid_p(void)
224 return flag_is_changeable_p(X86_EFLAGS_ID);
227 /* Do minimum CPU detection early.
228 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
229 The others are not touched to avoid unwanted side effects.
231 WARNING: this function is only called on the BP. Don't add code here
232 that is supposed to run on all CPUs. */
233 static void __init early_cpu_detect(void)
235 struct cpuinfo_x86 *c = &boot_cpu_data;
237 c->x86_cache_alignment = 32;
239 if (!have_cpuid_p())
240 return;
242 /* Get vendor name */
243 cpuid(0x00000000, &c->cpuid_level,
244 (int *)&c->x86_vendor_id[0],
245 (int *)&c->x86_vendor_id[8],
246 (int *)&c->x86_vendor_id[4]);
248 get_cpu_vendor(c, 1);
250 c->x86 = 4;
251 if (c->cpuid_level >= 0x00000001) {
252 u32 junk, tfms, cap0, misc;
253 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
254 c->x86 = (tfms >> 8) & 15;
255 c->x86_model = (tfms >> 4) & 15;
256 if (c->x86 == 0xf)
257 c->x86 += (tfms >> 20) & 0xff;
258 if (c->x86 >= 0x6)
259 c->x86_model += ((tfms >> 16) & 0xF) << 4;
260 c->x86_mask = tfms & 15;
261 if (cap0 & (1<<19))
262 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
266 void __cpuinit generic_identify(struct cpuinfo_x86 * c)
268 u32 tfms, xlvl;
269 int junk;
271 if (have_cpuid_p()) {
272 /* Get vendor name */
273 cpuid(0x00000000, &c->cpuid_level,
274 (int *)&c->x86_vendor_id[0],
275 (int *)&c->x86_vendor_id[8],
276 (int *)&c->x86_vendor_id[4]);
278 get_cpu_vendor(c, 0);
279 /* Initialize the standard set of capabilities */
280 /* Note that the vendor-specific code below might override */
282 /* Intel-defined flags: level 0x00000001 */
283 if ( c->cpuid_level >= 0x00000001 ) {
284 u32 capability, excap;
285 cpuid(0x00000001, &tfms, &junk, &excap, &capability);
286 c->x86_capability[0] = capability;
287 c->x86_capability[4] = excap;
288 c->x86 = (tfms >> 8) & 15;
289 c->x86_model = (tfms >> 4) & 15;
290 if (c->x86 == 0xf)
291 c->x86 += (tfms >> 20) & 0xff;
292 if (c->x86 >= 0x6)
293 c->x86_model += ((tfms >> 16) & 0xF) << 4;
294 c->x86_mask = tfms & 15;
295 } else {
296 /* Have CPUID level 0 only - unheard of */
297 c->x86 = 4;
300 /* AMD-defined flags: level 0x80000001 */
301 xlvl = cpuid_eax(0x80000000);
302 if ( (xlvl & 0xffff0000) == 0x80000000 ) {
303 if ( xlvl >= 0x80000001 ) {
304 c->x86_capability[1] = cpuid_edx(0x80000001);
305 c->x86_capability[6] = cpuid_ecx(0x80000001);
307 if ( xlvl >= 0x80000004 )
308 get_model_name(c); /* Default name */
312 early_intel_workaround(c);
314 #ifdef CONFIG_X86_HT
315 phys_proc_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff;
316 #endif
319 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
321 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
322 /* Disable processor serial number */
323 unsigned long lo,hi;
324 rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
325 lo |= 0x200000;
326 wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
327 printk(KERN_NOTICE "CPU serial number disabled.\n");
328 clear_bit(X86_FEATURE_PN, c->x86_capability);
330 /* Disabling the serial number may affect the cpuid level */
331 c->cpuid_level = cpuid_eax(0);
335 static int __init x86_serial_nr_setup(char *s)
337 disable_x86_serial_nr = 0;
338 return 1;
340 __setup("serialnumber", x86_serial_nr_setup);
345 * This does the hard work of actually picking apart the CPU stuff...
347 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
349 int i;
351 c->loops_per_jiffy = loops_per_jiffy;
352 c->x86_cache_size = -1;
353 c->x86_vendor = X86_VENDOR_UNKNOWN;
354 c->cpuid_level = -1; /* CPUID not detected */
355 c->x86_model = c->x86_mask = 0; /* So far unknown... */
356 c->x86_vendor_id[0] = '\0'; /* Unset */
357 c->x86_model_id[0] = '\0'; /* Unset */
358 c->x86_max_cores = 1;
359 memset(&c->x86_capability, 0, sizeof c->x86_capability);
361 if (!have_cpuid_p()) {
362 /* First of all, decide if this is a 486 or higher */
363 /* It's a 486 if we can modify the AC flag */
364 if ( flag_is_changeable_p(X86_EFLAGS_AC) )
365 c->x86 = 4;
366 else
367 c->x86 = 3;
370 generic_identify(c);
372 printk(KERN_DEBUG "CPU: After generic identify, caps:");
373 for (i = 0; i < NCAPINTS; i++)
374 printk(" %08lx", c->x86_capability[i]);
375 printk("\n");
377 if (this_cpu->c_identify) {
378 this_cpu->c_identify(c);
380 printk(KERN_DEBUG "CPU: After vendor identify, caps:");
381 for (i = 0; i < NCAPINTS; i++)
382 printk(" %08lx", c->x86_capability[i]);
383 printk("\n");
387 * Vendor-specific initialization. In this section we
388 * canonicalize the feature flags, meaning if there are
389 * features a certain CPU supports which CPUID doesn't
390 * tell us, CPUID claiming incorrect flags, or other bugs,
391 * we handle them here.
393 * At the end of this section, c->x86_capability better
394 * indicate the features this CPU genuinely supports!
396 if (this_cpu->c_init)
397 this_cpu->c_init(c);
399 /* Disable the PN if appropriate */
400 squash_the_stupid_serial_number(c);
403 * The vendor-specific functions might have changed features. Now
404 * we do "generic changes."
407 /* TSC disabled? */
408 if ( tsc_disable )
409 clear_bit(X86_FEATURE_TSC, c->x86_capability);
411 /* FXSR disabled? */
412 if (disable_x86_fxsr) {
413 clear_bit(X86_FEATURE_FXSR, c->x86_capability);
414 clear_bit(X86_FEATURE_XMM, c->x86_capability);
417 /* SEP disabled? */
418 if (disable_x86_sep)
419 clear_bit(X86_FEATURE_SEP, c->x86_capability);
421 if (disable_pse)
422 clear_bit(X86_FEATURE_PSE, c->x86_capability);
424 /* If the model name is still unset, do table lookup. */
425 if ( !c->x86_model_id[0] ) {
426 char *p;
427 p = table_lookup_model(c);
428 if ( p )
429 strcpy(c->x86_model_id, p);
430 else
431 /* Last resort... */
432 sprintf(c->x86_model_id, "%02x/%02x",
433 c->x86, c->x86_model);
436 /* Now the feature flags better reflect actual CPU features! */
438 printk(KERN_DEBUG "CPU: After all inits, caps:");
439 for (i = 0; i < NCAPINTS; i++)
440 printk(" %08lx", c->x86_capability[i]);
441 printk("\n");
444 * On SMP, boot_cpu_data holds the common feature set between
445 * all CPUs; so make sure that we indicate which features are
446 * common between the CPUs. The first time this routine gets
447 * executed, c == &boot_cpu_data.
449 if ( c != &boot_cpu_data ) {
450 /* AND the already accumulated flags with these */
451 for ( i = 0 ; i < NCAPINTS ; i++ )
452 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
455 /* Init Machine Check Exception if available. */
456 mcheck_init(c);
458 if (c == &boot_cpu_data)
459 sysenter_setup();
460 enable_sep_cpu();
462 if (c == &boot_cpu_data)
463 mtrr_bp_init();
464 else
465 mtrr_ap_init();
468 #ifdef CONFIG_X86_HT
469 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
471 u32 eax, ebx, ecx, edx;
472 int index_msb, core_bits;
473 int cpu = smp_processor_id();
475 cpuid(1, &eax, &ebx, &ecx, &edx);
477 c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0);
479 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
480 return;
482 smp_num_siblings = (ebx & 0xff0000) >> 16;
484 if (smp_num_siblings == 1) {
485 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
486 } else if (smp_num_siblings > 1 ) {
488 if (smp_num_siblings > NR_CPUS) {
489 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
490 smp_num_siblings = 1;
491 return;
494 index_msb = get_count_order(smp_num_siblings);
495 phys_proc_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
497 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
498 phys_proc_id[cpu]);
500 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
502 index_msb = get_count_order(smp_num_siblings) ;
504 core_bits = get_count_order(c->x86_max_cores);
506 cpu_core_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) &
507 ((1 << core_bits) - 1);
509 if (c->x86_max_cores > 1)
510 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
511 cpu_core_id[cpu]);
514 #endif
516 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
518 char *vendor = NULL;
520 if (c->x86_vendor < X86_VENDOR_NUM)
521 vendor = this_cpu->c_vendor;
522 else if (c->cpuid_level >= 0)
523 vendor = c->x86_vendor_id;
525 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
526 printk("%s ", vendor);
528 if (!c->x86_model_id[0])
529 printk("%d86", c->x86);
530 else
531 printk("%s", c->x86_model_id);
533 if (c->x86_mask || c->cpuid_level >= 0)
534 printk(" stepping %02x\n", c->x86_mask);
535 else
536 printk("\n");
539 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
541 /* This is hacky. :)
542 * We're emulating future behavior.
543 * In the future, the cpu-specific init functions will be called implicitly
544 * via the magic of initcalls.
545 * They will insert themselves into the cpu_devs structure.
546 * Then, when cpu_init() is called, we can just iterate over that array.
549 extern int intel_cpu_init(void);
550 extern int cyrix_init_cpu(void);
551 extern int nsc_init_cpu(void);
552 extern int amd_init_cpu(void);
553 extern int centaur_init_cpu(void);
554 extern int transmeta_init_cpu(void);
555 extern int rise_init_cpu(void);
556 extern int nexgen_init_cpu(void);
557 extern int umc_init_cpu(void);
559 void __init early_cpu_init(void)
561 intel_cpu_init();
562 cyrix_init_cpu();
563 nsc_init_cpu();
564 amd_init_cpu();
565 centaur_init_cpu();
566 transmeta_init_cpu();
567 rise_init_cpu();
568 nexgen_init_cpu();
569 umc_init_cpu();
570 early_cpu_detect();
572 #ifdef CONFIG_DEBUG_PAGEALLOC
573 /* pse is not compatible with on-the-fly unmapping,
574 * disable it even if the cpus claim to support it.
576 clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
577 disable_pse = 1;
578 #endif
581 * cpu_init() initializes state that is per-CPU. Some data is already
582 * initialized (naturally) in the bootstrap process, such as the GDT
583 * and IDT. We reload them nevertheless, this function acts as a
584 * 'CPU state barrier', nothing should get across.
586 void __cpuinit cpu_init(void)
588 int cpu = smp_processor_id();
589 struct tss_struct * t = &per_cpu(init_tss, cpu);
590 struct thread_struct *thread = &current->thread;
591 struct desc_struct *gdt;
592 __u32 stk16_off = (__u32)&per_cpu(cpu_16bit_stack, cpu);
593 struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu);
595 if (cpu_test_and_set(cpu, cpu_initialized)) {
596 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
597 for (;;) local_irq_enable();
599 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
601 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
602 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
603 if (tsc_disable && cpu_has_tsc) {
604 printk(KERN_NOTICE "Disabling TSC...\n");
605 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
606 clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability);
607 set_in_cr4(X86_CR4_TSD);
611 * This is a horrible hack to allocate the GDT. The problem
612 * is that cpu_init() is called really early for the boot CPU
613 * (and hence needs bootmem) but much later for the secondary
614 * CPUs, when bootmem will have gone away
616 if (NODE_DATA(0)->bdata->node_bootmem_map) {
617 gdt = (struct desc_struct *)alloc_bootmem_pages(PAGE_SIZE);
618 /* alloc_bootmem_pages panics on failure, so no check */
619 memset(gdt, 0, PAGE_SIZE);
620 } else {
621 gdt = (struct desc_struct *)get_zeroed_page(GFP_KERNEL);
622 if (unlikely(!gdt)) {
623 printk(KERN_CRIT "CPU%d failed to allocate GDT\n", cpu);
624 for (;;)
625 local_irq_enable();
630 * Initialize the per-CPU GDT with the boot GDT,
631 * and set up the GDT descriptor:
633 memcpy(gdt, cpu_gdt_table, GDT_SIZE);
635 /* Set up GDT entry for 16bit stack */
636 *(__u64 *)(&gdt[GDT_ENTRY_ESPFIX_SS]) |=
637 ((((__u64)stk16_off) << 16) & 0x000000ffffff0000ULL) |
638 ((((__u64)stk16_off) << 32) & 0xff00000000000000ULL) |
639 (CPU_16BIT_STACK_SIZE - 1);
641 cpu_gdt_descr->size = GDT_SIZE - 1;
642 cpu_gdt_descr->address = (unsigned long)gdt;
644 load_gdt(cpu_gdt_descr);
645 load_idt(&idt_descr);
648 * Set up and load the per-CPU TSS and LDT
650 atomic_inc(&init_mm.mm_count);
651 current->active_mm = &init_mm;
652 if (current->mm)
653 BUG();
654 enter_lazy_tlb(&init_mm, current);
656 load_esp0(t, thread);
657 set_tss_desc(cpu,t);
658 load_TR_desc();
659 load_LDT(&init_mm.context);
661 #ifdef CONFIG_DOUBLEFAULT
662 /* Set up doublefault TSS pointer in the GDT */
663 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
664 #endif
666 /* Clear %fs and %gs. */
667 asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs");
669 /* Clear all 6 debug registers: */
670 set_debugreg(0, 0);
671 set_debugreg(0, 1);
672 set_debugreg(0, 2);
673 set_debugreg(0, 3);
674 set_debugreg(0, 6);
675 set_debugreg(0, 7);
678 * Force FPU initialization:
680 current_thread_info()->status = 0;
681 clear_used_math();
682 mxcsr_feature_mask_init();
685 #ifdef CONFIG_HOTPLUG_CPU
686 void __cpuinit cpu_uninit(void)
688 int cpu = raw_smp_processor_id();
689 cpu_clear(cpu, cpu_initialized);
691 /* lazy TLB state */
692 per_cpu(cpu_tlbstate, cpu).state = 0;
693 per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;
695 #endif