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Merge with 2.3.99-pre9.
[linux-2.6/linux-mips.git] / drivers / ide / hpt366.c
blob28232b5768dc51ebf1a45dd51a762d7242fe8ca5
1 /*
2 * linux/drivers/ide/hpt366.c Version 0.17 Mar. 18, 2000
3 *
4 * Copyright (C) 1999-2000 Andre Hedrick <andre@suse.com>
5 * May be copied or modified under the terms of the GNU General Public License
6 *
7 * Thanks to HighPoint Technologies for their assistance, and hardware.
8 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
9 * donation of an ABit BP6 mainboard, processor, and memory acellerated
10 * development and support.
11 */
12
13 #include <linux/config.h>
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/delay.h>
17 #include <linux/timer.h>
18 #include <linux/mm.h>
19 #include <linux/ioport.h>
20 #include <linux/blkdev.h>
21 #include <linux/hdreg.h>
22
23 #include <linux/interrupt.h>
24 #include <linux/pci.h>
25 #include <linux/init.h>
26 #include <linux/ide.h>
27
28 #include <asm/io.h>
29 #include <asm/irq.h>
30
31 #include "ide_modes.h"
32
33 #undef DISPLAY_HPT366_TIMINGS
34
35 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
36 #include <linux/stat.h>
37 #include <linux/proc_fs.h>
38 #endif /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
39
40 const char *bad_ata66_4[] = {
41 "WDC AC310200R",
42 NULL
43 };
44
45 const char *bad_ata66_3[] = {
46 "WDC AC310200R",
47 NULL
48 };
49
50 const char *bad_ata33[] = {
51 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
52 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
53 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
54 "Maxtor 90510D4",
55 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
56 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
57 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
58 NULL
59 };
60
61 struct chipset_bus_clock_list_entry {
62 byte xfer_speed;
63 unsigned int chipset_settings;
64 };
65
66 struct chipset_bus_clock_list_entry forty_base [] = {
67
68 { XFER_UDMA_4 , 0x900fd943 },
69 { XFER_UDMA_3 , 0x900ad943 },
70 { XFER_UDMA_2 , 0x900bd943 },
71 { XFER_UDMA_1 , 0x9008d943 },
72 { XFER_UDMA_0 , 0x9008d943 },
73
74 { XFER_MW_DMA_2 , 0xa008d943 },
75 { XFER_MW_DMA_1 , 0xa010d955 },
76 { XFER_MW_DMA_0 , 0xa010d9fc },
77
78 { XFER_PIO_4 , 0xc008d963 },
79 { XFER_PIO_3 , 0xc010d974 },
80 { XFER_PIO_2 , 0xc010d997 },
81 { XFER_PIO_1 , 0xc010d9c7 },
82 { XFER_PIO_0 , 0xc018d9d9 },
83 { 0 , 0x0120d9d9 }
84 };
85
86 struct chipset_bus_clock_list_entry thirty_three_base [] = {
87
88 { XFER_UDMA_4 , 0x90c9a731 },
89 { XFER_UDMA_3 , 0x90cfa731 },
90 { XFER_UDMA_2 , 0x90caa731 },
91 { XFER_UDMA_1 , 0x90cba731 },
92 { XFER_UDMA_0 , 0x90c8a731 },
93
94 { XFER_MW_DMA_2 , 0xa0c8a731 },
95 { XFER_MW_DMA_1 , 0xa0c8a732 }, /* 0xa0c8a733 */
96 { XFER_MW_DMA_0 , 0xa0c8a797 },
97
98 { XFER_PIO_4 , 0xc0c8a731 },
99 { XFER_PIO_3 , 0xc0c8a742 },
100 { XFER_PIO_2 , 0xc0d0a753 },
101 { XFER_PIO_1 , 0xc0d0a7a3 }, /* 0xc0d0a793 */
102 { XFER_PIO_0 , 0xc0d0a7aa }, /* 0xc0d0a7a7 */
103 { 0 , 0x0120a7a7 }
104 };
105
106 struct chipset_bus_clock_list_entry twenty_five_base [] = {
107
108 { XFER_UDMA_4 , 0x90c98521 },
109 { XFER_UDMA_3 , 0x90cf8521 },
110 { XFER_UDMA_2 , 0x90cf8521 },
111 { XFER_UDMA_1 , 0x90cb8521 },
112 { XFER_UDMA_0 , 0x90cb8521 },
113
114 { XFER_MW_DMA_2 , 0xa0ca8521 },
115 { XFER_MW_DMA_1 , 0xa0ca8532 },
116 { XFER_MW_DMA_0 , 0xa0ca8575 },
117
118 { XFER_PIO_4 , 0xc0ca8521 },
119 { XFER_PIO_3 , 0xc0ca8532 },
120 { XFER_PIO_2 , 0xc0ca8542 },
121 { XFER_PIO_1 , 0xc0d08572 },
122 { XFER_PIO_0 , 0xc0d08585 },
123 { 0 , 0x01208585 }
124 };
125
126 #define HPT366_DEBUG_DRIVE_INFO 0
127 #define HPT366_ALLOW_ATA66_4 1
128 #define HPT366_ALLOW_ATA66_3 1
129
130 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
131 static int hpt366_get_info(char *, char **, off_t, int);
132 extern int (*hpt366_display_info)(char *, char **, off_t, int); /* ide-proc.c */
133 extern char *ide_media_verbose(ide_drive_t *);
134 static struct pci_dev *bmide_dev;
135 static struct pci_dev *bmide2_dev;
136
137 static int hpt366_get_info (char *buffer, char **addr, off_t offset, int count)
138 {
139 char *p = buffer;
140 u32 bibma = bmide_dev->resource[4].start;
141 u32 bibma2 = bmide2_dev->resource[4].start;
142 u8 c0 = 0, c1 = 0;
143
144 /*
145 * at that point bibma+0x2 et bibma+0xa are byte registers
146 * to investigate:
147 */
148 c0 = inb_p((unsigned short)bibma + 0x02);
149 if (bmide2_dev)
150 c1 = inb_p((unsigned short)bibma2 + 0x02);
151
152 p += sprintf(p, "\n HPT366 Chipset.\n");
153 p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
154 p += sprintf(p, " %sabled %sabled\n",
155 (c0&0x80) ? "dis" : " en",
156 (c1&0x80) ? "dis" : " en");
157 p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n");
158 p += sprintf(p, "DMA enabled: %s %s %s %s\n",
159 (c0&0x20) ? "yes" : "no ", (c0&0x40) ? "yes" : "no ",
160 (c1&0x20) ? "yes" : "no ", (c1&0x40) ? "yes" : "no " );
161
162 p += sprintf(p, "UDMA\n");
163 p += sprintf(p, "DMA\n");
164 p += sprintf(p, "PIO\n");
165
166 return p-buffer;/* => must be less than 4k! */
167 }
168 #endif /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
169
170 byte hpt366_proc = 0;
171
172 extern char *ide_xfer_verbose (byte xfer_rate);
173 byte hpt363_shared_irq = 0;
174 byte hpt363_shared_pin = 0;
175
176 static unsigned int pci_rev_check_hpt366 (struct pci_dev *dev)
177 {
178 unsigned int class_rev;
179 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
180 class_rev &= 0xff;
181 return ((int) (class_rev == 0x03) ? 1 : 0);
182 }
183
184 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
185 {
186 struct hd_driveid *id = drive->id;
187 #if HPT366_DEBUG_DRIVE_INFO
188 printk("check_in_drive_lists(%s, %p)\n", drive->name, list);
189 #endif /* HPT366_DEBUG_DRIVE_INFO */
190
191 while (*list) {
192 if (!strcmp(*list++,id->model)) {
193 #ifdef DEBUG
194 printk("%s: Broken ASIC, BackSpeeding (U)DMA for %s\n", drive->name, id->model);
195 #endif /* DEBUG */
196 return 1;
197 }
198 }
199 return 0;
200 }
201
202 static unsigned int pci_bus_clock_list (byte speed, struct chipset_bus_clock_list_entry * chipset_table)
203 {
204 #if HPT366_DEBUG_DRIVE_INFO
205 printk("pci_bus_clock_list(speed=0x%02x, table=%p)\n", speed, chipset_table);
206 #endif /* HPT366_DEBUG_DRIVE_INFO */
207 for ( ; chipset_table->xfer_speed ; chipset_table++)
208 if (chipset_table->xfer_speed == speed) {
209 #if HPT366_DEBUG_DRIVE_INFO
210 printk("pci_bus_clock_list: found match: 0x%08x\n", chipset_table->chipset_settings);
211 #endif /* HPT366_DEBUG_DRIVE_INFO */
212 return chipset_table->chipset_settings;
213 }
214 #if HPT366_DEBUG_DRIVE_INFO
215 printk("pci_bus_clock_list: using default: 0x%08x\n", 0x01208585);
216 #endif /* HPT366_DEBUG_DRIVE_INFO */
217 return 0x01208585;
218 }
219
220 static int hpt366_tune_chipset (ide_drive_t *drive, byte speed)
221 {
222 int err;
223 byte regtime = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
224 unsigned int reg1 = 0;
225 unsigned int reg2 = 0;
226
227 #if HPT366_DEBUG_DRIVE_INFO
228 printk("hpt366_tune_chipset(%s, speed=0x%02x)\n", drive->name, speed);
229 #endif /* HPT366_DEBUG_DRIVE_INFO */
230
231 pci_read_config_dword(HWIF(drive)->pci_dev, regtime, &reg1);
232 /* detect bus speed by looking at control reg timing: */
233 switch((reg1 >> 8) & 7) {
234 case 5:
235 reg2 = pci_bus_clock_list(speed, forty_base);
236 break;
237 case 9:
238 reg2 = pci_bus_clock_list(speed, twenty_five_base);
239 break;
240 default:
241 printk("hpt366: assuming 33Mhz PCI bus\n");
242 case 7:
243 reg2 = pci_bus_clock_list(speed, thirty_three_base);
244 break;
245 }
246 /*
247 * Disable on-chip PIO FIFO/buffer (to avoid problems handling I/O errors later)
248 */
249 if (speed >= XFER_MW_DMA_0) {
250 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
251 } else {
252 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
253 }
254 reg2 &= ~0x80000000;
255
256 pci_write_config_dword(HWIF(drive)->pci_dev, regtime, reg2);
257 err = ide_config_drive_speed(drive, speed);
258
259 if (!drive->init_speed)
260 drive->init_speed = speed;
261
262 #if HPT366_DEBUG_DRIVE_INFO
263 printk("%s: speed=0x%02x(%s), drive%d, old=0x%08x, new=0x%08x, err=0x%04x\n",
264 drive->name, speed, ide_xfer_verbose(speed),
265 drive->dn, reg1, reg2, err);
266 #endif /* HPT366_DEBUG_DRIVE_INFO */
267 drive->current_speed = speed;
268 return(err);
269 }
270
271 static void config_chipset_for_pio (ide_drive_t *drive)
272 {
273 unsigned short eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
274 unsigned short xfer_pio = drive->id->eide_pio_modes;
275 byte timing, speed, pio;
276
277 #if HPT366_DEBUG_DRIVE_INFO
278 printk("%s: config_chipset_for_pio\n", drive->name);
279 #endif /* HPT366_DEBUG_DRIVE_INFO */
280 pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
281
282 if (xfer_pio> 4)
283 xfer_pio = 0;
284
285 if (drive->id->eide_pio_iordy > 0) {
286 for (xfer_pio = 5;
287 xfer_pio>0 &&
288 drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
289 xfer_pio--);
290 } else {
291 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
292 (drive->id->eide_pio_modes & 2) ? 0x04 :
293 (drive->id->eide_pio_modes & 1) ? 0x03 :
294 (drive->id->tPIO & 2) ? 0x02 :
295 (drive->id->tPIO & 1) ? 0x01 : xfer_pio;
296 }
297
298 timing = (xfer_pio >= pio) ? xfer_pio : pio;
299
300 switch(timing) {
301 case 4: speed = XFER_PIO_4;break;
302 case 3: speed = XFER_PIO_3;break;
303 case 2: speed = XFER_PIO_2;break;
304 case 1: speed = XFER_PIO_1;break;
305 default:
306 speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW;
307 break;
308 }
309 #if HPT366_DEBUG_DRIVE_INFO
310 printk("%s: config_chipset_for_pio: speed=0x%04x\n", drive->name, speed);
311 #endif /* HPT366_DEBUG_DRIVE_INFO */
312 (void) hpt366_tune_chipset(drive, speed);
313 }
314
315 static void hpt366_tune_drive (ide_drive_t *drive, byte pio)
316 {
317 byte speed;
318 switch(pio) {
319 case 4: speed = XFER_PIO_4;break;
320 case 3: speed = XFER_PIO_3;break;
321 case 2: speed = XFER_PIO_2;break;
322 case 1: speed = XFER_PIO_1;break;
323 default: speed = XFER_PIO_0;break;
324 }
325 (void) hpt366_tune_chipset(drive, speed);
326 }
327
328 #ifdef CONFIG_BLK_DEV_IDEDMA
329 /*
330 * This allows the configuration of ide_pci chipset registers
331 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
332 * after the drive is reported by the OS. Initally for designed for
333 * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
334 *
335 * check_in_drive_lists(drive, bad_ata66_4)
336 * check_in_drive_lists(drive, bad_ata66_3)
337 * check_in_drive_lists(drive, bad_ata33)
338 *
339 */
340 static int config_chipset_for_dma (ide_drive_t *drive)
341 {
342 struct hd_driveid *id = drive->id;
343 byte speed = 0x00;
344 byte reg51h = 0;
345 int rval;
346
347 if ((id->dma_ultra & 0x0010) &&
348 (!check_in_drive_lists(drive, bad_ata66_4)) &&
349 (HPT366_ALLOW_ATA66_4) &&
350 (HWIF(drive)->udma_four)) {
351 speed = XFER_UDMA_4;
352 } else if ((id->dma_ultra & 0x0008) &&
353 (!check_in_drive_lists(drive, bad_ata66_3)) &&
354 (HPT366_ALLOW_ATA66_3) &&
355 (HWIF(drive)->udma_four)) {
356 speed = XFER_UDMA_3;
357 } else if (id->dma_ultra && (!check_in_drive_lists(drive, bad_ata33))) {
358 if (id->dma_ultra & 0x0004) {
359 speed = XFER_UDMA_2;
360 } else if (id->dma_ultra & 0x0002) {
361 speed = XFER_UDMA_1;
362 } else if (id->dma_ultra & 0x0001) {
363 speed = XFER_UDMA_0;
364 }
365 } else if (id->dma_mword & 0x0004) {
366 speed = XFER_MW_DMA_2;
367 } else if (id->dma_mword & 0x0002) {
368 speed = XFER_MW_DMA_1;
369 } else if (id->dma_mword & 0x0001) {
370 speed = XFER_MW_DMA_0;
371 } else if (id->dma_1word & 0x0004) {
372 speed = XFER_SW_DMA_2;
373 } else if (id->dma_1word & 0x0002) {
374 speed = XFER_SW_DMA_1;
375 } else if (id->dma_1word & 0x0001) {
376 speed = XFER_SW_DMA_0;
377 } else {
378 #if HPT366_DEBUG_DRIVE_INFO
379 printk("%s: config_chipset_for_dma: returning 'ide_dma_off_quietly'\n", drive->name);
380 #endif /* HPT366_DEBUG_DRIVE_INFO */
381 return ((int) ide_dma_off_quietly);
382 }
383
384 pci_read_config_byte(HWIF(drive)->pci_dev, 0x51, &reg51h);
385
386 #ifdef CONFIG_HPT366_FIP
387 /*
388 * Some drives prefer/allow for the method of handling interrupts.
389 */
390 if (!(reg51h & 0x80))
391 pci_write_config_byte(HWIF(drive)->pci_dev, 0x51, reg51h|0x80);
392 #else /* ! CONFIG_HPT366_FIP */
393 /*
394 * Disable the "fast interrupt" prediction.
395 * Instead, always wait for the real interrupt from the drive!
396 */
397 if (reg51h & 0x80)
398 pci_write_config_byte(HWIF(drive)->pci_dev, 0x51, reg51h & ~0x80);
399 #endif /* CONFIG_HPT366_FIP */
400 #if HPT366_DEBUG_DRIVE_INFO
401 printk("%s: config_chipset_for_dma: speed=0x%04x\n", drive->name, speed);
402 #endif /* HPT366_DEBUG_DRIVE_INFO */
403 (void) hpt366_tune_chipset(drive, speed);
404
405 rval = (int)( ((id->dma_ultra >> 11) & 3) ? ide_dma_on :
406 ((id->dma_ultra >> 8) & 7) ? ide_dma_on :
407 ((id->dma_mword >> 8) & 7) ? ide_dma_on :
408 ((id->dma_1word >> 8) & 7) ? ide_dma_on :
409 ide_dma_off_quietly);
410
411 #if HPT366_DEBUG_DRIVE_INFO
412 printk("%s: config_chipset_for_dma: returning %d (%s)\n", drive->name, rval, rval == ide_dma_on ? "dma_on" : "dma_off");
413 #endif /* HPT366_DEBUG_DRIVE_INFO */
414 return rval;
415 }
416
417 static int config_drive_xfer_rate (ide_drive_t *drive)
418 {
419 struct hd_driveid *id = drive->id;
420 ide_dma_action_t dma_func = ide_dma_on;
421
422 if (id && (id->capability & 1) && HWIF(drive)->autodma) {
423 /* Consult the list of known "bad" drives */
424 if (ide_dmaproc(ide_dma_bad_drive, drive)) {
425 dma_func = ide_dma_off;
426 goto fast_ata_pio;
427 }
428 dma_func = ide_dma_off_quietly;
429 if (id->field_valid & 4) {
430 if (id->dma_ultra & 0x001F) {
431 /* Force if Capable UltraDMA */
432 dma_func = config_chipset_for_dma(drive);
433 if ((id->field_valid & 2) &&
434 (dma_func != ide_dma_on))
435 goto try_dma_modes;
436 }
437 } else if (id->field_valid & 2) {
438 try_dma_modes:
439 if ((id->dma_mword & 0x0007) ||
440 (id->dma_1word & 0x0007)) {
441 /* Force if Capable regular DMA modes */
442 dma_func = config_chipset_for_dma(drive);
443 if (dma_func != ide_dma_on)
444 goto no_dma_set;
445 }
446 } else if (ide_dmaproc(ide_dma_good_drive, drive)) {
447 if (id->eide_dma_time > 150) {
448 goto no_dma_set;
449 }
450 /* Consult the list of known "good" drives */
451 dma_func = config_chipset_for_dma(drive);
452 if (dma_func != ide_dma_on)
453 goto no_dma_set;
454 } else {
455 goto fast_ata_pio;
456 }
457 } else if ((id->capability & 8) || (id->field_valid & 2)) {
458 fast_ata_pio:
459 dma_func = ide_dma_off_quietly;
460 no_dma_set:
461
462 config_chipset_for_pio(drive);
463 }
464 return HWIF(drive)->dmaproc(dma_func, drive);
465 }
466
467 /*
468 * hpt366_dmaproc() initiates/aborts (U)DMA read/write operations on a drive.
469 *
470 * This is specific to the HPT366 UDMA bios chipset
471 * by HighPoint|Triones Technologies, Inc.
472 */
473 int hpt366_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
474 {
475 byte reg50h = 0;
476
477 switch (func) {
478 case ide_dma_check:
479 return config_drive_xfer_rate(drive);
480 case ide_dma_lostirq:
481 #if 0
482 pci_read_config_byte(HWIF(drive)->pci_dev, 0x50, &reg50h);
483 pci_write_config_byte(HWIF(drive)->pci_dev, 0x50, reg50h|0x03);
484 pci_read_config_byte(HWIF(drive)->pci_dev, 0x50, &reg50h);
485 /* ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL); */
486 #endif
487 case ide_dma_timeout:
488 default:
489 break;
490 }
491 return ide_dmaproc(func, drive); /* use standard DMA stuff */
492 }
493 #endif /* CONFIG_BLK_DEV_IDEDMA */
494
495 unsigned int __init pci_init_hpt366 (struct pci_dev *dev, const char *name)
496 {
497 byte test = 0;
498
499 if (dev->resource[PCI_ROM_RESOURCE].start)
500 pci_write_config_byte(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
501
502 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &test);
503 if (test != 0x08)
504 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x08);
505
506 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &test);
507 if (test != 0x78)
508 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
509
510 pci_read_config_byte(dev, PCI_MIN_GNT, &test);
511 if (test != 0x08)
512 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
513
514 pci_read_config_byte(dev, PCI_MAX_LAT, &test);
515 if (test != 0x08)
516 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
517
518 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
519 if (!hpt366_proc) {
520 hpt366_proc = 1;
521 bmide_dev = dev;
522 if (pci_rev_check_hpt366(dev))
523 bmide2_dev = dev;
524 hpt366_display_info = &hpt366_get_info;
525 }
526 if ((hpt366_proc) && ((dev->devfn - bmide_dev->devfn) == 1)) {
527 bmide2_dev = dev;
528 }
529 #endif /* DISPLAY_HPT366_TIMINGS && CONFIG_PROC_FS */
530
531 return dev->irq;
532 }
533
534 unsigned int __init ata66_hpt366 (ide_hwif_t *hwif)
535 {
536 byte ata66 = 0;
537
538 pci_read_config_byte(hwif->pci_dev, 0x5a, &ata66);
539 #ifdef DEBUG
540 printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
541 ata66, (ata66 & 0x02) ? "33" : "66",
542 PCI_FUNC(hwif->pci_dev->devfn));
543 #endif /* DEBUG */
544 return ((ata66 & 0x02) ? 0 : 1);
545 }
546
547 void __init ide_init_hpt366 (ide_hwif_t *hwif)
548 {
549 if (pci_rev_check_hpt366(hwif->pci_dev)) return;
550
551 hwif->tuneproc = &hpt366_tune_drive;
552 hwif->speedproc = &hpt366_tune_chipset;
553
554 #ifdef CONFIG_BLK_DEV_IDEDMA
555 if (hwif->dma_base) {
556 hwif->dmaproc = &hpt366_dmaproc;
557 hwif->autodma = 1;
558 } else {
559 hwif->autodma = 0;
560 hwif->drives[0].autotune = 1;
561 hwif->drives[1].autotune = 1;
562 }
563 #else /* !CONFIG_BLK_DEV_IDEDMA */
564 hwif->drives[0].autotune = 1;
565 hwif->drives[1].autotune = 1;
566 hwif->autodma = 0;
567 #endif /* CONFIG_BLK_DEV_IDEDMA */
568 }
569
570 void ide_dmacapable_hpt366 (ide_hwif_t *hwif, unsigned long dmabase)
571 {
572 byte masterdma = 0, slavedma = 0;
573 byte dma_new = 0, dma_old = inb(dmabase+2);
574 unsigned long flags;
575
576 if (pci_rev_check_hpt366(hwif->pci_dev)) {
577 ide_setup_dma(hwif, dmabase, 8);
578 return;
579 }
580
581 __save_flags(flags); /* local CPU only */
582 __cli(); /* local CPU only */
583
584 dma_new = dma_old;
585 pci_read_config_byte(hwif->pci_dev, 0x43, &masterdma);
586 pci_read_config_byte(hwif->pci_dev, 0x47, &slavedma);
587
588 if (masterdma & 0x30) dma_new |= 0x20;
589 if (slavedma & 0x30) dma_new |= 0x40;
590 if (dma_new != dma_old) outb(dma_new, dmabase+2);
591
592 __restore_flags(flags); /* local CPU only */
593
594 ide_setup_dma(hwif, dmabase, 8);
595 }
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