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Merge with 2.3.99-pre9.
[linux-2.6/linux-mips.git] / arch / i386 / kernel / pci-pc.c
blob404a49868cceaf00a19a1e13f22e476e627d9f5a
1 /*
2 * Low-Level PCI Support for PC
3 *
4 * (c) 1999--2000 Martin Mares <mj@suse.cz>
5 */
6
7 #include <linux/config.h>
8 #include <linux/types.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/pci.h>
12 #include <linux/init.h>
13 #include <linux/ioport.h>
14
15 #include <asm/segment.h>
16 #include <asm/io.h>
17 #include <asm/smp.h>
18
19 #include "pci-i386.h"
20
21 unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2;
22
23 int pcibios_last_bus = -1;
24 struct pci_bus *pci_root_bus;
25 struct pci_ops *pci_root_ops;
26
27 /*
28 * Direct access to PCI hardware...
29 */
30
31 #ifdef CONFIG_PCI_DIRECT
32
33 /*
34 * Functions for accessing PCI configuration space with type 1 accesses
35 */
36
37 #define CONFIG_CMD(dev, where) (0x80000000 | (dev->bus->number << 16) | (dev->devfn << 8) | (where & ~3))
38
39 static int pci_conf1_read_config_byte(struct pci_dev *dev, int where, u8 *value)
40 {
41 outl(CONFIG_CMD(dev,where), 0xCF8);
42 *value = inb(0xCFC + (where&3));
43 return PCIBIOS_SUCCESSFUL;
44 }
45
46 static int pci_conf1_read_config_word(struct pci_dev *dev, int where, u16 *value)
47 {
48 outl(CONFIG_CMD(dev,where), 0xCF8);
49 *value = inw(0xCFC + (where&2));
50 return PCIBIOS_SUCCESSFUL;
51 }
52
53 static int pci_conf1_read_config_dword(struct pci_dev *dev, int where, u32 *value)
54 {
55 outl(CONFIG_CMD(dev,where), 0xCF8);
56 *value = inl(0xCFC);
57 return PCIBIOS_SUCCESSFUL;
58 }
59
60 static int pci_conf1_write_config_byte(struct pci_dev *dev, int where, u8 value)
61 {
62 outl(CONFIG_CMD(dev,where), 0xCF8);
63 outb(value, 0xCFC + (where&3));
64 return PCIBIOS_SUCCESSFUL;
65 }
66
67 static int pci_conf1_write_config_word(struct pci_dev *dev, int where, u16 value)
68 {
69 outl(CONFIG_CMD(dev,where), 0xCF8);
70 outw(value, 0xCFC + (where&2));
71 return PCIBIOS_SUCCESSFUL;
72 }
73
74 static int pci_conf1_write_config_dword(struct pci_dev *dev, int where, u32 value)
75 {
76 outl(CONFIG_CMD(dev,where), 0xCF8);
77 outl(value, 0xCFC);
78 return PCIBIOS_SUCCESSFUL;
79 }
80
81 #undef CONFIG_CMD
82
83 static struct pci_ops pci_direct_conf1 = {
84 pci_conf1_read_config_byte,
85 pci_conf1_read_config_word,
86 pci_conf1_read_config_dword,
87 pci_conf1_write_config_byte,
88 pci_conf1_write_config_word,
89 pci_conf1_write_config_dword
90 };
91
92 /*
93 * Functions for accessing PCI configuration space with type 2 accesses
94 */
95
96 #define IOADDR(devfn, where) ((0xC000 | ((devfn & 0x78) << 5)) + where)
97 #define FUNC(devfn) (((devfn & 7) << 1) | 0xf0)
98 #define SET(dev) if (dev->devfn & 0x80) return PCIBIOS_DEVICE_NOT_FOUND; \
99 outb(FUNC(dev->devfn), 0xCF8); \
100 outb(dev->bus->number, 0xCFA);
101
102 static int pci_conf2_read_config_byte(struct pci_dev *dev, int where, u8 *value)
103 {
104 SET(dev);
105 *value = inb(IOADDR(dev->devfn,where));
106 outb (0, 0xCF8);
107 return PCIBIOS_SUCCESSFUL;
108 }
109
110 static int pci_conf2_read_config_word(struct pci_dev *dev, int where, u16 *value)
111 {
112 SET(dev);
113 *value = inw(IOADDR(dev->devfn,where));
114 outb (0, 0xCF8);
115 return PCIBIOS_SUCCESSFUL;
116 }
117
118 static int pci_conf2_read_config_dword(struct pci_dev *dev, int where, u32 *value)
119 {
120 SET(dev);
121 *value = inl (IOADDR(dev->devfn,where));
122 outb (0, 0xCF8);
123 return PCIBIOS_SUCCESSFUL;
124 }
125
126 static int pci_conf2_write_config_byte(struct pci_dev *dev, int where, u8 value)
127 {
128 SET(dev);
129 outb (value, IOADDR(dev->devfn,where));
130 outb (0, 0xCF8);
131 return PCIBIOS_SUCCESSFUL;
132 }
133
134 static int pci_conf2_write_config_word(struct pci_dev *dev, int where, u16 value)
135 {
136 SET(dev);
137 outw (value, IOADDR(dev->devfn,where));
138 outb (0, 0xCF8);
139 return PCIBIOS_SUCCESSFUL;
140 }
141
142 static int pci_conf2_write_config_dword(struct pci_dev *dev, int where, u32 value)
143 {
144 SET(dev);
145 outl (value, IOADDR(dev->devfn,where));
146 outb (0, 0xCF8);
147 return PCIBIOS_SUCCESSFUL;
148 }
149
150 #undef SET
151 #undef IOADDR
152 #undef FUNC
153
154 static struct pci_ops pci_direct_conf2 = {
155 pci_conf2_read_config_byte,
156 pci_conf2_read_config_word,
157 pci_conf2_read_config_dword,
158 pci_conf2_write_config_byte,
159 pci_conf2_write_config_word,
160 pci_conf2_write_config_dword
161 };
162
163 /*
164 * Before we decide to use direct hardware access mechanisms, we try to do some
165 * trivial checks to ensure it at least _seems_ to be working -- we just test
166 * whether bus 00 contains a host bridge (this is similar to checking
167 * techniques used in XFree86, but ours should be more reliable since we
168 * attempt to make use of direct access hints provided by the PCI BIOS).
169 *
170 * This should be close to trivial, but it isn't, because there are buggy
171 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
172 */
173 static int __init pci_sanity_check(struct pci_ops *o)
174 {
175 u16 x;
176 struct pci_bus bus; /* Fake bus and device */
177 struct pci_dev dev;
178
179 if (pci_probe & PCI_NO_CHECKS)
180 return 1;
181 bus.number = 0;
182 dev.bus = &bus;
183 for(dev.devfn=0; dev.devfn < 0x100; dev.devfn++)
184 if ((!o->read_word(&dev, PCI_CLASS_DEVICE, &x) &&
185 (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)) ||
186 (!o->read_word(&dev, PCI_VENDOR_ID, &x) &&
187 (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ)))
188 return 1;
189 DBG("PCI: Sanity check failed\n");
190 return 0;
191 }
192
193 static struct pci_ops * __init pci_check_direct(void)
194 {
195 unsigned int tmp;
196 unsigned long flags;
197
198 __save_flags(flags); __cli();
199
200 /*
201 * Check if configuration type 1 works.
202 */
203 if (pci_probe & PCI_PROBE_CONF1) {
204 outb (0x01, 0xCFB);
205 tmp = inl (0xCF8);
206 outl (0x80000000, 0xCF8);
207 if (inl (0xCF8) == 0x80000000 &&
208 pci_sanity_check(&pci_direct_conf1)) {
209 outl (tmp, 0xCF8);
210 __restore_flags(flags);
211 printk("PCI: Using configuration type 1\n");
212 request_region(0xCF8, 8, "PCI conf1");
213 return &pci_direct_conf1;
214 }
215 outl (tmp, 0xCF8);
216 }
217
218 /*
219 * Check if configuration type 2 works.
220 */
221 if (pci_probe & PCI_PROBE_CONF2) {
222 outb (0x00, 0xCFB);
223 outb (0x00, 0xCF8);
224 outb (0x00, 0xCFA);
225 if (inb (0xCF8) == 0x00 && inb (0xCFA) == 0x00 &&
226 pci_sanity_check(&pci_direct_conf2)) {
227 __restore_flags(flags);
228 printk("PCI: Using configuration type 2\n");
229 request_region(0xCF8, 4, "PCI conf2");
230 return &pci_direct_conf2;
231 }
232 }
233
234 __restore_flags(flags);
235 return NULL;
236 }
237
238 #endif
239
240 /*
241 * BIOS32 and PCI BIOS handling.
242 */
243
244 #ifdef CONFIG_PCI_BIOS
245
246 #define PCIBIOS_PCI_FUNCTION_ID 0xb1XX
247 #define PCIBIOS_PCI_BIOS_PRESENT 0xb101
248 #define PCIBIOS_FIND_PCI_DEVICE 0xb102
249 #define PCIBIOS_FIND_PCI_CLASS_CODE 0xb103
250 #define PCIBIOS_GENERATE_SPECIAL_CYCLE 0xb106
251 #define PCIBIOS_READ_CONFIG_BYTE 0xb108
252 #define PCIBIOS_READ_CONFIG_WORD 0xb109
253 #define PCIBIOS_READ_CONFIG_DWORD 0xb10a
254 #define PCIBIOS_WRITE_CONFIG_BYTE 0xb10b
255 #define PCIBIOS_WRITE_CONFIG_WORD 0xb10c
256 #define PCIBIOS_WRITE_CONFIG_DWORD 0xb10d
257 #define PCIBIOS_GET_ROUTING_OPTIONS 0xb10e
258 #define PCIBIOS_SET_PCI_HW_INT 0xb10f
259
260 /* BIOS32 signature: "_32_" */
261 #define BIOS32_SIGNATURE (('_' << 0) + ('3' << 8) + ('2' << 16) + ('_' << 24))
262
263 /* PCI signature: "PCI " */
264 #define PCI_SIGNATURE (('P' << 0) + ('C' << 8) + ('I' << 16) + (' ' << 24))
265
266 /* PCI service signature: "$PCI" */
267 #define PCI_SERVICE (('$' << 0) + ('P' << 8) + ('C' << 16) + ('I' << 24))
268
269 /* PCI BIOS hardware mechanism flags */
270 #define PCIBIOS_HW_TYPE1 0x01
271 #define PCIBIOS_HW_TYPE2 0x02
272 #define PCIBIOS_HW_TYPE1_SPEC 0x10
273 #define PCIBIOS_HW_TYPE2_SPEC 0x20
274
275 /*
276 * This is the standard structure used to identify the entry point
277 * to the BIOS32 Service Directory, as documented in
278 * Standard BIOS 32-bit Service Directory Proposal
279 * Revision 0.4 May 24, 1993
280 * Phoenix Technologies Ltd.
281 * Norwood, MA
282 * and the PCI BIOS specification.
283 */
284
285 union bios32 {
286 struct {
287 unsigned long signature; /* _32_ */
288 unsigned long entry; /* 32 bit physical address */
289 unsigned char revision; /* Revision level, 0 */
290 unsigned char length; /* Length in paragraphs should be 01 */
291 unsigned char checksum; /* All bytes must add up to zero */
292 unsigned char reserved[5]; /* Must be zero */
293 } fields;
294 char chars[16];
295 };
296
297 /*
298 * Physical address of the service directory. I don't know if we're
299 * allowed to have more than one of these or not, so just in case
300 * we'll make pcibios_present() take a memory start parameter and store
301 * the array there.
302 */
303
304 static struct {
305 unsigned long address;
306 unsigned short segment;
307 } bios32_indirect = { 0, __KERNEL_CS };
308
309 /*
310 * Returns the entry point for the given service, NULL on error
311 */
312
313 static unsigned long bios32_service(unsigned long service)
314 {
315 unsigned char return_code; /* %al */
316 unsigned long address; /* %ebx */
317 unsigned long length; /* %ecx */
318 unsigned long entry; /* %edx */
319 unsigned long flags;
320
321 __save_flags(flags); __cli();
322 __asm__("lcall (%%edi); cld"
323 : "=a" (return_code),
324 "=b" (address),
325 "=c" (length),
326 "=d" (entry)
327 : "0" (service),
328 "1" (0),
329 "D" (&bios32_indirect));
330 __restore_flags(flags);
331
332 switch (return_code) {
333 case 0:
334 return address + entry;
335 case 0x80: /* Not present */
336 printk("bios32_service(0x%lx): not present\n", service);
337 return 0;
338 default: /* Shouldn't happen */
339 printk("bios32_service(0x%lx): returned 0x%x -- BIOS bug!\n",
340 service, return_code);
341 return 0;
342 }
343 }
344
345 static struct {
346 unsigned long address;
347 unsigned short segment;
348 } pci_indirect = { 0, __KERNEL_CS };
349
350 static int pci_bios_present;
351
352 static int __init check_pcibios(void)
353 {
354 u32 signature, eax, ebx, ecx;
355 u8 status, major_ver, minor_ver, hw_mech;
356 unsigned long flags, pcibios_entry;
357
358 if ((pcibios_entry = bios32_service(PCI_SERVICE))) {
359 pci_indirect.address = pcibios_entry + PAGE_OFFSET;
360
361 __save_flags(flags); __cli();
362 __asm__(
363 "lcall (%%edi); cld\n\t"
364 "jc 1f\n\t"
365 "xor %%ah, %%ah\n"
366 "1:"
367 : "=d" (signature),
368 "=a" (eax),
369 "=b" (ebx),
370 "=c" (ecx)
371 : "1" (PCIBIOS_PCI_BIOS_PRESENT),
372 "D" (&pci_indirect)
373 : "memory");
374 __restore_flags(flags);
375
376 status = (eax >> 8) & 0xff;
377 hw_mech = eax & 0xff;
378 major_ver = (ebx >> 8) & 0xff;
379 minor_ver = ebx & 0xff;
380 if (pcibios_last_bus < 0)
381 pcibios_last_bus = ecx & 0xff;
382 DBG("PCI: BIOS probe returned s=%02x hw=%02x ver=%02x.%02x l=%02x\n",
383 status, hw_mech, major_ver, minor_ver, pcibios_last_bus);
384 if (status || signature != PCI_SIGNATURE) {
385 printk (KERN_ERR "PCI: BIOS BUG #%x[%08x] found, report to <mj@suse.cz>\n",
386 status, signature);
387 return 0;
388 }
389 printk("PCI: PCI BIOS revision %x.%02x entry at 0x%lx, last bus=%d\n",
390 major_ver, minor_ver, pcibios_entry, pcibios_last_bus);
391 #ifdef CONFIG_PCI_DIRECT
392 if (!(hw_mech & PCIBIOS_HW_TYPE1))
393 pci_probe &= ~PCI_PROBE_CONF1;
394 if (!(hw_mech & PCIBIOS_HW_TYPE2))
395 pci_probe &= ~PCI_PROBE_CONF2;
396 #endif
397 return 1;
398 }
399 return 0;
400 }
401
402 static int __init pci_bios_find_device (unsigned short vendor, unsigned short device_id,
403 unsigned short index, unsigned char *bus, unsigned char *device_fn)
404 {
405 unsigned short bx;
406 unsigned short ret;
407
408 __asm__("lcall (%%edi); cld\n\t"
409 "jc 1f\n\t"
410 "xor %%ah, %%ah\n"
411 "1:"
412 : "=b" (bx),
413 "=a" (ret)
414 : "1" (PCIBIOS_FIND_PCI_DEVICE),
415 "c" (device_id),
416 "d" (vendor),
417 "S" ((int) index),
418 "D" (&pci_indirect));
419 *bus = (bx >> 8) & 0xff;
420 *device_fn = bx & 0xff;
421 return (int) (ret & 0xff00) >> 8;
422 }
423
424 static int pci_bios_read_config_byte(struct pci_dev *dev, int where, u8 *value)
425 {
426 unsigned long ret;
427 unsigned long bx = (dev->bus->number << 8) | dev->devfn;
428
429 __asm__("lcall (%%esi); cld\n\t"
430 "jc 1f\n\t"
431 "xor %%ah, %%ah\n"
432 "1:"
433 : "=c" (*value),
434 "=a" (ret)
435 : "1" (PCIBIOS_READ_CONFIG_BYTE),
436 "b" (bx),
437 "D" ((long) where),
438 "S" (&pci_indirect));
439 return (int) (ret & 0xff00) >> 8;
440 }
441
442 static int pci_bios_read_config_word(struct pci_dev *dev, int where, u16 *value)
443 {
444 unsigned long ret;
445 unsigned long bx = (dev->bus->number << 8) | dev->devfn;
446
447 __asm__("lcall (%%esi); cld\n\t"
448 "jc 1f\n\t"
449 "xor %%ah, %%ah\n"
450 "1:"
451 : "=c" (*value),
452 "=a" (ret)
453 : "1" (PCIBIOS_READ_CONFIG_WORD),
454 "b" (bx),
455 "D" ((long) where),
456 "S" (&pci_indirect));
457 return (int) (ret & 0xff00) >> 8;
458 }
459
460 static int pci_bios_read_config_dword(struct pci_dev *dev, int where, u32 *value)
461 {
462 unsigned long ret;
463 unsigned long bx = (dev->bus->number << 8) | dev->devfn;
464
465 __asm__("lcall (%%esi); cld\n\t"
466 "jc 1f\n\t"
467 "xor %%ah, %%ah\n"
468 "1:"
469 : "=c" (*value),
470 "=a" (ret)
471 : "1" (PCIBIOS_READ_CONFIG_DWORD),
472 "b" (bx),
473 "D" ((long) where),
474 "S" (&pci_indirect));
475 return (int) (ret & 0xff00) >> 8;
476 }
477
478 static int pci_bios_write_config_byte(struct pci_dev *dev, int where, u8 value)
479 {
480 unsigned long ret;
481 unsigned long bx = (dev->bus->number << 8) | dev->devfn;
482
483 __asm__("lcall (%%esi); cld\n\t"
484 "jc 1f\n\t"
485 "xor %%ah, %%ah\n"
486 "1:"
487 : "=a" (ret)
488 : "0" (PCIBIOS_WRITE_CONFIG_BYTE),
489 "c" (value),
490 "b" (bx),
491 "D" ((long) where),
492 "S" (&pci_indirect));
493 return (int) (ret & 0xff00) >> 8;
494 }
495
496 static int pci_bios_write_config_word(struct pci_dev *dev, int where, u16 value)
497 {
498 unsigned long ret;
499 unsigned long bx = (dev->bus->number << 8) | dev->devfn;
500
501 __asm__("lcall (%%esi); cld\n\t"
502 "jc 1f\n\t"
503 "xor %%ah, %%ah\n"
504 "1:"
505 : "=a" (ret)
506 : "0" (PCIBIOS_WRITE_CONFIG_WORD),
507 "c" (value),
508 "b" (bx),
509 "D" ((long) where),
510 "S" (&pci_indirect));
511 return (int) (ret & 0xff00) >> 8;
512 }
513
514 static int pci_bios_write_config_dword(struct pci_dev *dev, int where, u32 value)
515 {
516 unsigned long ret;
517 unsigned long bx = (dev->bus->number << 8) | dev->devfn;
518
519 __asm__("lcall (%%esi); cld\n\t"
520 "jc 1f\n\t"
521 "xor %%ah, %%ah\n"
522 "1:"
523 : "=a" (ret)
524 : "0" (PCIBIOS_WRITE_CONFIG_DWORD),
525 "c" (value),
526 "b" (bx),
527 "D" ((long) where),
528 "S" (&pci_indirect));
529 return (int) (ret & 0xff00) >> 8;
530 }
531
532 /*
533 * Function table for BIOS32 access
534 */
535
536 static struct pci_ops pci_bios_access = {
537 pci_bios_read_config_byte,
538 pci_bios_read_config_word,
539 pci_bios_read_config_dword,
540 pci_bios_write_config_byte,
541 pci_bios_write_config_word,
542 pci_bios_write_config_dword
543 };
544
545 /*
546 * Try to find PCI BIOS.
547 */
548
549 static struct pci_ops * __init pci_find_bios(void)
550 {
551 union bios32 *check;
552 unsigned char sum;
553 int i, length;
554
555 /*
556 * Follow the standard procedure for locating the BIOS32 Service
557 * directory by scanning the permissible address range from
558 * 0xe0000 through 0xfffff for a valid BIOS32 structure.
559 */
560
561 for (check = (union bios32 *) __va(0xe0000);
562 check <= (union bios32 *) __va(0xffff0);
563 ++check) {
564 if (check->fields.signature != BIOS32_SIGNATURE)
565 continue;
566 length = check->fields.length * 16;
567 if (!length)
568 continue;
569 sum = 0;
570 for (i = 0; i < length ; ++i)
571 sum += check->chars[i];
572 if (sum != 0)
573 continue;
574 if (check->fields.revision != 0) {
575 printk("PCI: unsupported BIOS32 revision %d at 0x%p, report to <mj@suse.cz>\n",
576 check->fields.revision, check);
577 continue;
578 }
579 DBG("PCI: BIOS32 Service Directory structure at 0x%p\n", check);
580 if (check->fields.entry >= 0x100000) {
581 printk("PCI: BIOS32 entry (0x%p) in high memory, cannot use.\n", check);
582 return NULL;
583 } else {
584 unsigned long bios32_entry = check->fields.entry;
585 DBG("PCI: BIOS32 Service Directory entry at 0x%lx\n", bios32_entry);
586 bios32_indirect.address = bios32_entry + PAGE_OFFSET;
587 if (check_pcibios())
588 return &pci_bios_access;
589 }
590 break; /* Hopefully more than one BIOS32 cannot happen... */
591 }
592
593 return NULL;
594 }
595
596 /*
597 * Sort the device list according to PCI BIOS. Nasty hack, but since some
598 * fool forgot to define the `correct' device order in the PCI BIOS specs
599 * and we want to be (possibly bug-to-bug ;-]) compatible with older kernels
600 * which used BIOS ordering, we are bound to do this...
601 */
602
603 static void __init pcibios_sort(void)
604 {
605 LIST_HEAD(sorted_devices);
606 struct list_head *ln;
607 struct pci_dev *dev, *d;
608 int idx, found;
609 unsigned char bus, devfn;
610
611 DBG("PCI: Sorting device list...\n");
612 while (!list_empty(&pci_devices)) {
613 ln = pci_devices.next;
614 dev = pci_dev_g(ln);
615 idx = found = 0;
616 while (pci_bios_find_device(dev->vendor, dev->device, idx, &bus, &devfn) == PCIBIOS_SUCCESSFUL) {
617 idx++;
618 for (ln=pci_devices.next; ln != &pci_devices; ln=ln->next) {
619 d = pci_dev_g(ln);
620 if (d->bus->number == bus && d->devfn == devfn) {
621 list_del(&d->global_list);
622 list_add_tail(&d->global_list, &sorted_devices);
623 if (d == dev)
624 found = 1;
625 break;
626 }
627 }
628 if (ln == &pci_devices) {
629 printk("PCI: BIOS reporting unknown device %02x:%02x\n", bus, devfn);
630 /*
631 * We must not continue scanning as several buggy BIOSes
632 * return garbage after the last device. Grr.
633 */
634 break;
635 }
636 }
637 if (!found) {
638 printk("PCI: Device %02x:%02x not found by BIOS\n",
639 dev->bus->number, dev->devfn);
640 list_del(&dev->global_list);
641 list_add_tail(&dev->global_list, &sorted_devices);
642 }
643 }
644 list_splice(&sorted_devices, &pci_devices);
645 }
646
647 /*
648 * BIOS Functions for IRQ Routing
649 */
650
651 struct irq_routing_options {
652 u16 size;
653 struct irq_info *table;
654 u16 segment;
655 } __attribute__((packed));
656
657 struct irq_routing_table * __init pcibios_get_irq_routing_table(void)
658 {
659 struct irq_routing_options opt;
660 struct irq_routing_table *rt = NULL;
661 int ret, map;
662 unsigned long page;
663
664 if (!pci_bios_present)
665 return NULL;
666 page = __get_free_page(GFP_KERNEL);
667 if (!page)
668 return NULL;
669 opt.table = (struct irq_info *) page;
670 opt.size = PAGE_SIZE;
671 opt.segment = __KERNEL_DS;
672
673 DBG("PCI: Fetching IRQ routing table... ");
674 __asm__("push %%es\n\t"
675 "push %%ds\n\t"
676 "pop %%es\n\t"
677 "lcall (%%esi); cld\n\t"
678 "pop %%es\n\t"
679 "jc 1f\n\t"
680 "xor %%ah, %%ah\n"
681 "1:"
682 : "=a" (ret),
683 "=b" (map)
684 : "0" (PCIBIOS_GET_ROUTING_OPTIONS),
685 "1" (0),
686 "D" ((long) &opt),
687 "S" (&pci_indirect));
688 DBG("OK ret=%d, size=%d, map=%x\n", ret, opt.size, map);
689 if (ret & 0xff00)
690 printk(KERN_ERR "PCI: Error %02x when fetching IRQ routing table.\n", (ret >> 8) & 0xff);
691 else if (opt.size) {
692 rt = kmalloc(sizeof(struct irq_routing_table) + opt.size, GFP_KERNEL);
693 if (rt) {
694 memset(rt, 0, sizeof(struct irq_routing_table));
695 rt->size = opt.size + sizeof(struct irq_routing_table);
696 rt->exclusive_irqs = map;
697 memcpy(rt->slots, (void *) page, opt.size);
698 printk("PCI: Using BIOS Interrupt Routing Table\n");
699 }
700 }
701 free_page(page);
702 return rt;
703 }
704
705
706 int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq)
707 {
708 int ret;
709
710 __asm__("lcall (%%esi); cld\n\t"
711 "jc 1f\n\t"
712 "xor %%ah, %%ah\n"
713 "1:"
714 : "=a" (ret)
715 : "0" (PCIBIOS_SET_PCI_HW_INT),
716 "b" ((dev->bus->number << 8) | dev->devfn),
717 "c" ((irq << 8) | (pin + 10)),
718 "S" (&pci_indirect));
719 return !(ret & 0xff00);
720 }
721
722 #endif
723
724 /*
725 * Several buggy motherboards address only 16 devices and mirror
726 * them to next 16 IDs. We try to detect this `feature' on all
727 * primary buses (those containing host bridges as they are
728 * expected to be unique) and remove the ghost devices.
729 */
730
731 static void __init pcibios_fixup_ghosts(struct pci_bus *b)
732 {
733 struct list_head *ln, *mn;
734 struct pci_dev *d, *e;
735 int mirror = PCI_DEVFN(16,0);
736 int seen_host_bridge = 0;
737 int i;
738
739 DBG("PCI: Scanning for ghost devices on bus %d\n", b->number);
740 for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
741 d = pci_dev_b(ln);
742 if ((d->class >> 8) == PCI_CLASS_BRIDGE_HOST)
743 seen_host_bridge++;
744 for (mn=ln->next; mn != &b->devices; mn=mn->next) {
745 e = pci_dev_b(mn);
746 if (e->devfn != d->devfn + mirror ||
747 e->vendor != d->vendor ||
748 e->device != d->device ||
749 e->class != d->class)
750 continue;
751 for(i=0; i<PCI_NUM_RESOURCES; i++)
752 if (e->resource[i].start != d->resource[i].start ||
753 e->resource[i].end != d->resource[i].end ||
754 e->resource[i].flags != d->resource[i].flags)
755 continue;
756 break;
757 }
758 if (mn == &b->devices)
759 return;
760 }
761 if (!seen_host_bridge)
762 return;
763 printk("PCI: Ignoring ghost devices on bus %02x\n", b->number);
764
765 ln = &b->devices;
766 while (ln->next != &b->devices) {
767 d = pci_dev_b(ln->next);
768 if (d->devfn >= mirror) {
769 list_del(&d->global_list);
770 list_del(&d->bus_list);
771 kfree(d);
772 } else
773 ln = ln->next;
774 }
775 }
776
777 /*
778 * Discover remaining PCI buses in case there are peer host bridges.
779 * We use the number of last PCI bus provided by the PCI BIOS.
780 */
781 static void __init pcibios_fixup_peer_bridges(void)
782 {
783 int n;
784 struct pci_bus bus;
785 struct pci_dev dev;
786 u16 l;
787
788 if (pcibios_last_bus <= 0 || pcibios_last_bus >= 0xff)
789 return;
790 DBG("PCI: Peer bridge fixup\n");
791 for (n=0; n <= pcibios_last_bus; n++) {
792 if (pci_bus_exists(&pci_root_buses, n))
793 continue;
794 bus.number = n;
795 bus.ops = pci_root_ops;
796 dev.bus = &bus;
797 for(dev.devfn=0; dev.devfn<256; dev.devfn += 8)
798 if (!pci_read_config_word(&dev, PCI_VENDOR_ID, &l) &&
799 l != 0x0000 && l != 0xffff) {
800 DBG("Found device at %02x:%02x [%04x]\n", n, dev.devfn, l);
801 printk("PCI: Discovered peer bus %02x\n", n);
802 pci_scan_bus(n, pci_root_ops, NULL);
803 break;
804 }
805 }
806 }
807
808 /*
809 * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
810 */
811
812 static void __init pci_fixup_i450nx(struct pci_dev *d)
813 {
814 /*
815 * i450NX -- Find and scan all secondary buses on all PXB's.
816 */
817 int pxb, reg;
818 u8 busno, suba, subb;
819 printk("PCI: Searching for i450NX host bridges on %s\n", d->slot_name);
820 reg = 0xd0;
821 for(pxb=0; pxb<2; pxb++) {
822 pci_read_config_byte(d, reg++, &busno);
823 pci_read_config_byte(d, reg++, &suba);
824 pci_read_config_byte(d, reg++, &subb);
825 DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
826 if (busno)
827 pci_scan_bus(busno, pci_root_ops, NULL); /* Bus A */
828 if (suba < subb)
829 pci_scan_bus(suba+1, pci_root_ops, NULL); /* Bus B */
830 }
831 pcibios_last_bus = -1;
832 }
833
834 static void __init pci_fixup_i450gx(struct pci_dev *d)
835 {
836 /*
837 * i450GX and i450KX -- Find and scan all secondary buses.
838 * (called separately for each PCI bridge found)
839 */
840 u8 busno;
841 pci_read_config_byte(d, 0x4a, &busno);
842 printk("PCI: i440KX/GX host bridge %s: secondary bus %02x\n", d->slot_name, busno);
843 pci_scan_bus(busno, pci_root_ops, NULL);
844 pcibios_last_bus = -1;
845 }
846
847 static void __init pci_fixup_serverworks(struct pci_dev *d)
848 {
849 /*
850 * ServerWorks host bridges -- Find and scan all secondary buses.
851 * Register 0x44 contains first, 0x45 last bus number routed there.
852 */
853 u8 busno;
854 pci_read_config_byte(d, 0x44, &busno);
855 printk("PCI: ServerWorks host bridge: secondary bus %02x\n", busno);
856 pci_scan_bus(busno, pci_root_ops, NULL);
857 pcibios_last_bus = -1;
858 }
859
860 static void __init pci_fixup_compaq(struct pci_dev *d)
861 {
862 /*
863 * Compaq host bridges -- Find and scan all secondary buses.
864 * This time registers 0xc8 and 0xc9.
865 */
866 u8 busno;
867 pci_read_config_byte(d, 0xc8, &busno);
868 printk("PCI: Compaq host bridge: secondary bus %02x\n", busno);
869 pci_scan_bus(busno, pci_root_ops, NULL);
870 pcibios_last_bus = -1;
871 }
872
873 static void __init pci_fixup_umc_ide(struct pci_dev *d)
874 {
875 /*
876 * UM8886BF IDE controller sets region type bits incorrectly,
877 * therefore they look like memory despite of them being I/O.
878 */
879 int i;
880
881 printk("PCI: Fixing base address flags for device %s\n", d->slot_name);
882 for(i=0; i<4; i++)
883 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
884 }
885
886 static void __init pci_fixup_ide_bases(struct pci_dev *d)
887 {
888 int i;
889
890 /*
891 * PCI IDE controllers use non-standard I/O port decoding, respect it.
892 */
893 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
894 return;
895 DBG("PCI: IDE base address fixup for %s\n", d->slot_name);
896 for(i=0; i<4; i++) {
897 struct resource *r = &d->resource[i];
898 if ((r->start & ~0x80) == 0x374) {
899 r->start |= 2;
900 r->end = r->start;
901 }
902 }
903 }
904
905 static void __init pci_fixup_ide_trash(struct pci_dev *d)
906 {
907 int i;
908
909 /*
910 * There exist PCI IDE controllers which have utter garbage
911 * in first four base registers. Ignore that.
912 */
913 DBG("PCI: IDE base address trash cleared for %s\n", d->slot_name);
914 for(i=0; i<4; i++)
915 d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0;
916 }
917
918 static void __init pci_fixup_latency(struct pci_dev *d)
919 {
920 /*
921 * SiS 5597 and 5598 chipsets require latency timer set to
922 * at most 32 to avoid lockups.
923 */
924 DBG("PCI: Setting max latency to 32\n");
925 pcibios_max_latency = 32;
926 }
927
928 struct pci_fixup pcibios_fixups[] = {
929 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx },
930 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx },
931 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HE, pci_fixup_serverworks },
932 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_LE, pci_fixup_serverworks },
933 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CMIC_HE, pci_fixup_serverworks },
934 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_6010, pci_fixup_compaq },
935 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide },
936 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_fixup_ide_trash },
937 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases },
938 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency },
939 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency },
940 { 0 }
941 };
942
943 /*
944 * Called after each bus is probed, but before its children
945 * are examined.
946 */
947
948 void __init pcibios_fixup_bus(struct pci_bus *b)
949 {
950 pcibios_fixup_ghosts(b);
951 pci_read_bridge_bases(b);
952 }
953
954 /*
955 * Initialization. Try all known PCI access methods. Note that we support
956 * using both PCI BIOS and direct access: in such cases, we use I/O ports
957 * to access config space, but we still keep BIOS order of cards to be
958 * compatible with 2.0.X. This should go away some day.
959 */
960
961 void __init pcibios_init(void)
962 {
963 struct pci_ops *bios = NULL;
964 struct pci_ops *dir = NULL;
965
966 #ifdef CONFIG_PCI_BIOS
967 if ((pci_probe & PCI_PROBE_BIOS) && ((bios = pci_find_bios()))) {
968 pci_probe |= PCI_BIOS_SORT;
969 pci_bios_present = 1;
970 }
971 #endif
972 #ifdef CONFIG_PCI_DIRECT
973 if (pci_probe & (PCI_PROBE_CONF1 | PCI_PROBE_CONF2))
974 dir = pci_check_direct();
975 #endif
976 if (dir)
977 pci_root_ops = dir;
978 else if (bios)
979 pci_root_ops = bios;
980 else {
981 printk("PCI: No PCI bus detected\n");
982 return;
983 }
984
985 printk("PCI: Probing PCI hardware\n");
986 pci_root_bus = pci_scan_bus(0, pci_root_ops, NULL);
987
988 pcibios_irq_init();
989 pcibios_fixup_peer_bridges();
990 pcibios_fixup_irqs();
991 pcibios_resource_survey();
992
993 #ifdef CONFIG_PCI_BIOS
994 if ((pci_probe & PCI_BIOS_SORT) && !(pci_probe & PCI_NO_SORT))
995 pcibios_sort();
996 #endif
997 }
998
999 char * __init pcibios_setup(char *str)
1000 {
1001 if (!strcmp(str, "off")) {
1002 pci_probe = 0;
1003 return NULL;
1004 }
1005 #ifdef CONFIG_PCI_BIOS
1006 else if (!strcmp(str, "bios")) {
1007 pci_probe = PCI_PROBE_BIOS;
1008 return NULL;
1009 } else if (!strcmp(str, "nobios")) {
1010 pci_probe &= ~PCI_PROBE_BIOS;
1011 return NULL;
1012 } else if (!strcmp(str, "nosort")) {
1013 pci_probe |= PCI_NO_SORT;
1014 return NULL;
1015 } else if (!strcmp(str, "biosirq")) {
1016 pci_probe |= PCI_BIOS_IRQ_SCAN;
1017 return NULL;
1018 }
1019 #endif
1020 #ifdef CONFIG_PCI_DIRECT
1021 else if (!strcmp(str, "conf1")) {
1022 pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS;
1023 return NULL;
1024 }
1025 else if (!strcmp(str, "conf2")) {
1026 pci_probe = PCI_PROBE_CONF2 | PCI_NO_CHECKS;
1027 return NULL;
1028 }
1029 #endif
1030 else if (!strcmp(str, "rom")) {
1031 pci_probe |= PCI_ASSIGN_ROMS;
1032 return NULL;
1033 } else if (!strncmp(str, "irqmask=", 8)) {
1034 pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
1035 return NULL;
1036 } else if (!strncmp(str, "lastbus=", 8)) {
1037 pcibios_last_bus = simple_strtol(str+8, NULL, 0);
1038 return NULL;
1039 }
1040 return str;
1041 }
1042
1043 int pcibios_enable_device(struct pci_dev *dev)
1044 {
1045 int err;
1046
1047 if ((err = pcibios_enable_resources(dev)) < 0)
1048 return err;
1049 if (!dev->irq) {
1050 u8 pin;
1051 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1052 if (pin && !pcibios_lookup_irq(dev, 1))
1053 printk(KERN_WARNING "PCI: No IRQ known for interrupt pin %c of device %s.%s\n",
1054 'A' + pin - 1, dev->slot_name,
1055 (pci_probe & PCI_BIOS_IRQ_SCAN) ? "" : " Please try using pci=biosirq.");
1056 }
1057 return 0;
1058 }
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