2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore for
18 * testing these extensively
22 #include <linux/irq.h>
23 #include <linux/interrupt.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/sched.h>
27 #include <linux/config.h>
28 #include <linux/smp_lock.h>
34 static spinlock_t ioapic_lock
= SPIN_LOCK_UNLOCKED
;
37 * # of IO-APICs and # of IRQ routing registers
40 int nr_ioapic_registers
[MAX_IO_APICS
];
42 /* I/O APIC entries */
43 struct mpc_config_ioapic mp_ioapics
[MAX_IO_APICS
];
45 /* # of MP IRQ source entries */
46 struct mpc_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
48 /* MP IRQ source entries */
49 int mp_irq_entries
= 0;
52 # define TARGET_CPUS cpu_online_map
54 # define TARGET_CPUS 0x01
57 * Rough estimation of how many shared IRQs there are, can
60 #define MAX_PLUS_SHARED_IRQS NR_IRQS
61 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
64 * This is performance-critical, we want to do it O(1)
66 * the indexing order of this array favors 1:1 mappings
67 * between pins and IRQs.
70 static struct irq_pin_list
{
72 } irq_2_pin
[PIN_MAP_SIZE
];
75 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
76 * shared ISA-space IRQs, so we have to support them. We are super
77 * fast in the common case, and fast for shared ISA-space IRQs.
79 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
81 static int first_free_entry
= NR_IRQS
;
82 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
85 entry
= irq_2_pin
+ entry
->next
;
87 if (entry
->pin
!= -1) {
88 entry
->next
= first_free_entry
;
89 entry
= irq_2_pin
+ entry
->next
;
90 if (++first_free_entry
>= PIN_MAP_SIZE
)
91 panic("io_apic.c: whoops");
97 #define __DO_ACTION(R, ACTION, FINAL) \
101 struct irq_pin_list *entry = irq_2_pin + irq; \
108 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
110 io_apic_modify(entry->apic, reg); \
113 entry = irq_2_pin + entry->next; \
118 #define DO_ACTION(name,R,ACTION, FINAL) \
120 static void name##_IO_APIC_irq (unsigned int irq) \
121 __DO_ACTION(R, ACTION, FINAL)
123 DO_ACTION( __mask
, 0, |= 0x00010000, io_apic_sync(entry
->apic
))/* mask = 1 */
124 DO_ACTION( __unmask
, 0, &= 0xfffeffff, ) /* mask = 0 */
126 static void mask_IO_APIC_irq (unsigned int irq
)
130 spin_lock_irqsave(&ioapic_lock
, flags
);
131 __mask_IO_APIC_irq(irq
);
132 spin_unlock_irqrestore(&ioapic_lock
, flags
);
135 static void unmask_IO_APIC_irq (unsigned int irq
)
139 spin_lock_irqsave(&ioapic_lock
, flags
);
140 __unmask_IO_APIC_irq(irq
);
141 spin_unlock_irqrestore(&ioapic_lock
, flags
);
144 void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
146 struct IO_APIC_route_entry entry
;
149 * Disable it in the IO-APIC irq-routing table:
151 memset(&entry
, 0, sizeof(entry
));
153 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry
) + 0));
154 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry
) + 1));
157 static void clear_IO_APIC (void)
161 for (apic
= 0; apic
< nr_ioapics
; apic
++)
162 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
163 clear_IO_APIC_pin(apic
, pin
);
167 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
168 * specific CPU-side IRQs.
172 int pirq_entries
[MAX_PIRQS
];
173 int pirqs_enabled
= 0;
174 int skip_ioapic_setup
= 0;
176 static int __init
ioapic_setup(char *str
)
178 extern int skip_ioapic_setup
; /* defined in arch/i386/kernel/smp.c */
180 skip_ioapic_setup
= 1;
184 __setup("noapic", ioapic_setup
);
186 static int __init
ioapic_pirq_setup(char *str
)
189 int ints
[MAX_PIRQS
+1];
191 get_options(str
, ARRAY_SIZE(ints
), ints
);
193 for (i
= 0; i
< MAX_PIRQS
; i
++)
194 pirq_entries
[i
] = -1;
197 printk(KERN_INFO
"PIRQ redirection, working around broken MP-BIOS.\n");
199 if (ints
[0] < MAX_PIRQS
)
202 for (i
= 0; i
< max
; i
++) {
203 printk(KERN_DEBUG
"... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
205 * PIRQs are mapped upside down, usually.
207 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
212 __setup("pirq=", ioapic_pirq_setup
);
215 * Find the IRQ entry number of a certain pin.
217 static int __init
find_irq_entry(int apic
, int pin
, int type
)
221 for (i
= 0; i
< mp_irq_entries
; i
++)
222 if ( (mp_irqs
[i
].mpc_irqtype
== type
) &&
223 (mp_irqs
[i
].mpc_dstapic
== mp_ioapics
[apic
].mpc_apicid
) &&
224 (mp_irqs
[i
].mpc_dstirq
== pin
))
232 * Find the pin to which IRQ0 (ISA) is connected
234 static int __init
find_timer_pin(int type
)
238 for (i
= 0; i
< mp_irq_entries
; i
++) {
239 int lbus
= mp_irqs
[i
].mpc_srcbus
;
241 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
242 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
243 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
) &&
244 (mp_irqs
[i
].mpc_irqtype
== type
) &&
245 (mp_irqs
[i
].mpc_srcbusirq
== 0x00))
247 return mp_irqs
[i
].mpc_dstirq
;
253 * Find a specific PCI IRQ entry.
254 * Not an __init, possibly needed by modules
256 static int __init
pin_2_irq(int idx
, int apic
, int pin
);
257 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pci_pin
)
259 int apic
, i
, best_guess
= -1;
261 for (i
= 0; i
< mp_irq_entries
; i
++) {
262 int lbus
= mp_irqs
[i
].mpc_srcbus
;
264 for (apic
= 0; apic
< nr_ioapics
; apic
++)
265 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
)
268 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_PCI
) &&
269 !mp_irqs
[i
].mpc_irqtype
&&
270 (bus
== mp_bus_id_to_pci_bus
[mp_irqs
[i
].mpc_srcbus
]) &&
271 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f))) {
272 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mpc_dstirq
);
274 if (!(apic
|| IO_APIC_IRQ(irq
)))
277 if (pci_pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3))
280 * Use the first all-but-pin matching entry as a
281 * best-guess fuzzy result for broken mptables.
291 * EISA Edge/Level control register, ELCR
293 static int __init
EISA_ELCR(unsigned int irq
)
296 unsigned int port
= 0x4d0 + (irq
>> 3);
297 return (inb(port
) >> (irq
& 7)) & 1;
299 printk(KERN_INFO
"Broken MPtable reports ISA irq %d\n", irq
);
303 /* EISA interrupts are always polarity zero and can be edge or level
304 * trigger depending on the ELCR value. If an interrupt is listed as
305 * EISA conforming in the MP table, that means its trigger type must
306 * be read in from the ELCR */
308 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
309 #define default_EISA_polarity(idx) (0)
311 /* ISA interrupts are always polarity zero edge triggered,
312 * when listed as conforming in the MP table. */
314 #define default_ISA_trigger(idx) (0)
315 #define default_ISA_polarity(idx) (0)
317 /* PCI interrupts are always polarity one level triggered,
318 * when listed as conforming in the MP table. */
320 #define default_PCI_trigger(idx) (1)
321 #define default_PCI_polarity(idx) (1)
323 /* MCA interrupts are always polarity zero level triggered,
324 * when listed as conforming in the MP table. */
326 #define default_MCA_trigger(idx) (1)
327 #define default_MCA_polarity(idx) (0)
329 static int __init
MPBIOS_polarity(int idx
)
331 int bus
= mp_irqs
[idx
].mpc_srcbus
;
335 * Determine IRQ line polarity (high active or low active):
337 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
339 case 0: /* conforms, ie. bus-type dependent polarity */
341 switch (mp_bus_id_to_type
[bus
])
343 case MP_BUS_ISA
: /* ISA pin */
345 polarity
= default_ISA_polarity(idx
);
348 case MP_BUS_EISA
: /* EISA pin */
350 polarity
= default_EISA_polarity(idx
);
353 case MP_BUS_PCI
: /* PCI pin */
355 polarity
= default_PCI_polarity(idx
);
358 case MP_BUS_MCA
: /* MCA pin */
360 polarity
= default_MCA_polarity(idx
);
365 printk(KERN_WARNING
"broken BIOS!!\n");
372 case 1: /* high active */
377 case 2: /* reserved */
379 printk(KERN_WARNING
"broken BIOS!!\n");
383 case 3: /* low active */
388 default: /* invalid */
390 printk(KERN_WARNING
"broken BIOS!!\n");
398 static int __init
MPBIOS_trigger(int idx
)
400 int bus
= mp_irqs
[idx
].mpc_srcbus
;
404 * Determine IRQ trigger mode (edge or level sensitive):
406 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
408 case 0: /* conforms, ie. bus-type dependent */
410 switch (mp_bus_id_to_type
[bus
])
412 case MP_BUS_ISA
: /* ISA pin */
414 trigger
= default_ISA_trigger(idx
);
417 case MP_BUS_EISA
: /* EISA pin */
419 trigger
= default_EISA_trigger(idx
);
422 case MP_BUS_PCI
: /* PCI pin */
424 trigger
= default_PCI_trigger(idx
);
427 case MP_BUS_MCA
: /* MCA pin */
429 trigger
= default_MCA_trigger(idx
);
434 printk(KERN_WARNING
"broken BIOS!!\n");
446 case 2: /* reserved */
448 printk(KERN_WARNING
"broken BIOS!!\n");
457 default: /* invalid */
459 printk(KERN_WARNING
"broken BIOS!!\n");
467 static inline int irq_polarity(int idx
)
469 return MPBIOS_polarity(idx
);
472 static inline int irq_trigger(int idx
)
474 return MPBIOS_trigger(idx
);
477 static int __init
pin_2_irq(int idx
, int apic
, int pin
)
480 int bus
= mp_irqs
[idx
].mpc_srcbus
;
483 * Debugging check, we are in big trouble if this message pops up!
485 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
486 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
488 switch (mp_bus_id_to_type
[bus
])
490 case MP_BUS_ISA
: /* ISA pin */
494 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
497 case MP_BUS_PCI
: /* PCI pin */
500 * PCI IRQs are mapped in order
504 irq
+= nr_ioapic_registers
[i
++];
510 printk(KERN_ERR
"unknown bus type %d.\n",bus
);
517 * PCI IRQ command line redirection. Yes, limits are hardcoded.
519 if ((pin
>= 16) && (pin
<= 23)) {
520 if (pirq_entries
[pin
-16] != -1) {
521 if (!pirq_entries
[pin
-16]) {
522 printk(KERN_DEBUG
"disabling PIRQ%d\n", pin
-16);
524 irq
= pirq_entries
[pin
-16];
525 printk(KERN_DEBUG
"using PIRQ%d -> IRQ %d\n",
533 static inline int IO_APIC_irq_trigger(int irq
)
537 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
538 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
539 idx
= find_irq_entry(apic
,pin
,mp_INT
);
540 if ((idx
!= -1) && (irq
== pin_2_irq(idx
,apic
,pin
)))
541 return irq_trigger(idx
);
545 * nonexistent IRQs are edge default
550 int irq_vector
[NR_IRQS
] = { FIRST_DEVICE_VECTOR
, 0 };
552 static int __init
assign_irq_vector(int irq
)
554 static int current_vector
= FIRST_DEVICE_VECTOR
, offset
= 0;
555 if (IO_APIC_VECTOR(irq
) > 0)
556 return IO_APIC_VECTOR(irq
);
559 if (current_vector
== SYSCALL_VECTOR
)
562 if (current_vector
> FIRST_SYSTEM_VECTOR
) {
564 current_vector
= FIRST_DEVICE_VECTOR
+ offset
;
567 if (current_vector
== FIRST_SYSTEM_VECTOR
)
568 panic("ran out of interrupt sources!");
570 IO_APIC_VECTOR(irq
) = current_vector
;
571 return current_vector
;
574 extern void (*interrupt
[NR_IRQS
])(void);
575 static struct hw_interrupt_type ioapic_level_irq_type
;
576 static struct hw_interrupt_type ioapic_edge_irq_type
;
578 void __init
setup_IO_APIC_irqs(void)
580 struct IO_APIC_route_entry entry
;
581 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
583 printk(KERN_DEBUG
"init IO_APIC IRQs\n");
585 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
586 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
589 * add it to the IO-APIC irq-routing table:
591 memset(&entry
,0,sizeof(entry
));
593 entry
.delivery_mode
= dest_LowestPrio
;
594 entry
.dest_mode
= 1; /* logical delivery */
595 entry
.mask
= 0; /* enable IRQ */
596 entry
.dest
.logical
.logical_dest
= TARGET_CPUS
;
598 idx
= find_irq_entry(apic
,pin
,mp_INT
);
601 printk(KERN_DEBUG
" IO-APIC (apicid-pin) %d-%d", mp_ioapics
[apic
].mpc_apicid
, pin
);
604 printk(", %d-%d", mp_ioapics
[apic
].mpc_apicid
, pin
);
608 entry
.trigger
= irq_trigger(idx
);
609 entry
.polarity
= irq_polarity(idx
);
611 if (irq_trigger(idx
)) {
614 entry
.dest
.logical
.logical_dest
= TARGET_CPUS
;
617 irq
= pin_2_irq(idx
, apic
, pin
);
618 add_pin_to_irq(irq
, apic
, pin
);
620 if (!apic
&& !IO_APIC_IRQ(irq
))
623 if (IO_APIC_IRQ(irq
)) {
624 vector
= assign_irq_vector(irq
);
625 entry
.vector
= vector
;
627 if (IO_APIC_irq_trigger(irq
))
628 irq_desc
[irq
].handler
= &ioapic_level_irq_type
;
630 irq_desc
[irq
].handler
= &ioapic_edge_irq_type
;
632 set_intr_gate(vector
, interrupt
[irq
]);
634 if (!apic
&& (irq
< 16))
635 disable_8259A_irq(irq
);
637 io_apic_write(apic
, 0x11+2*pin
, *(((int *)&entry
)+1));
638 io_apic_write(apic
, 0x10+2*pin
, *(((int *)&entry
)+0));
643 printk(" not connected.\n");
647 * Set up the 8259A-master output pin as broadcast to all
650 void __init
setup_ExtINT_IRQ0_pin(unsigned int pin
, int vector
)
652 struct IO_APIC_route_entry entry
;
654 memset(&entry
,0,sizeof(entry
));
656 disable_8259A_irq(0);
659 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
664 * We use logical delivery to get the timer IRQ
667 entry
.dest_mode
= 1; /* logical delivery */
668 entry
.mask
= 0; /* unmask IRQ now */
669 entry
.dest
.logical
.logical_dest
= TARGET_CPUS
;
670 entry
.delivery_mode
= dest_LowestPrio
;
673 entry
.vector
= vector
;
676 * The timer IRQ doesnt have to know that behind the
677 * scene we have a 8259A-master in AEOI mode ...
679 irq_desc
[0].handler
= &ioapic_edge_irq_type
;
682 * Add it to the IO-APIC irq-routing table:
684 io_apic_write(0, 0x11+2*pin
, *(((int *)&entry
)+1));
685 io_apic_write(0, 0x10+2*pin
, *(((int *)&entry
)+0));
690 void __init
UNEXPECTED_IO_APIC(void)
692 printk(KERN_WARNING
" WARNING: unexpected IO-APIC, please mail\n");
693 printk(KERN_WARNING
" to linux-smp@vger.rutgers.edu\n");
696 void __init
print_IO_APIC(void)
699 struct IO_APIC_reg_00 reg_00
;
700 struct IO_APIC_reg_01 reg_01
;
701 struct IO_APIC_reg_02 reg_02
;
703 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
704 for (i
= 0; i
< nr_ioapics
; i
++)
705 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
706 mp_ioapics
[i
].mpc_apicid
, nr_ioapic_registers
[i
]);
709 * We are a bit conservative about what we expect. We have to
710 * know about every hardware change ASAP.
712 printk(KERN_INFO
"testing the IO APIC.......................\n");
714 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
716 *(int *)®_00
= io_apic_read(apic
, 0);
717 *(int *)®_01
= io_apic_read(apic
, 1);
718 if (reg_01
.version
>= 0x10)
719 *(int *)®_02
= io_apic_read(apic
, 2);
722 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mpc_apicid
);
723 printk(KERN_DEBUG
".... register #00: %08X\n", *(int *)®_00
);
724 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.ID
);
725 if (reg_00
.__reserved_1
|| reg_00
.__reserved_2
)
726 UNEXPECTED_IO_APIC();
728 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
729 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.entries
);
730 if ( (reg_01
.entries
!= 0x0f) && /* older (Neptune) boards */
731 (reg_01
.entries
!= 0x17) && /* typical ISA+PCI boards */
732 (reg_01
.entries
!= 0x1b) && /* Compaq Proliant boards */
733 (reg_01
.entries
!= 0x1f) && /* dual Xeon boards */
734 (reg_01
.entries
!= 0x22) && /* bigger Xeon boards */
735 (reg_01
.entries
!= 0x2E) &&
736 (reg_01
.entries
!= 0x3F)
738 UNEXPECTED_IO_APIC();
740 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.version
);
741 if ( (reg_01
.version
!= 0x01) && /* 82489DX IO-APICs */
742 (reg_01
.version
!= 0x10) && /* oldest IO-APICs */
743 (reg_01
.version
!= 0x11) && /* Pentium/Pro IO-APICs */
744 (reg_01
.version
!= 0x13) /* Xeon IO-APICs */
746 UNEXPECTED_IO_APIC();
747 if (reg_01
.__reserved_1
|| reg_01
.__reserved_2
)
748 UNEXPECTED_IO_APIC();
750 if (reg_01
.version
>= 0x10) {
751 printk(KERN_DEBUG
".... register #02: %08X\n", *(int *)®_02
);
752 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.arbitration
);
753 if (reg_02
.__reserved_1
|| reg_02
.__reserved_2
)
754 UNEXPECTED_IO_APIC();
757 printk(KERN_DEBUG
".... IRQ redirection table:\n");
759 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
760 " Stat Dest Deli Vect: \n");
762 for (i
= 0; i
<= reg_01
.entries
; i
++) {
763 struct IO_APIC_route_entry entry
;
765 *(((int *)&entry
)+0) = io_apic_read(apic
, 0x10+i
*2);
766 *(((int *)&entry
)+1) = io_apic_read(apic
, 0x11+i
*2);
768 printk(KERN_DEBUG
" %02x %03X %02X ",
770 entry
.dest
.logical
.logical_dest
,
771 entry
.dest
.physical
.physical_dest
774 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
779 entry
.delivery_status
,
786 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
787 for (i
= 0; i
< NR_IRQS
; i
++) {
788 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
791 printk(KERN_DEBUG
"IRQ%d ", i
);
793 printk("-> %d", entry
->pin
);
796 entry
= irq_2_pin
+ entry
->next
;
801 printk(KERN_INFO
".................................... done.\n");
806 static void print_APIC_bitfield (int base
)
811 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
812 for (i
= 0; i
< 8; i
++) {
813 v
= apic_read(base
+ i
*0x10);
814 for (j
= 0; j
< 32; j
++) {
824 void /*__init*/ print_local_APIC(void * dummy
)
826 unsigned int v
, ver
, maxlvt
;
828 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
829 smp_processor_id(), hard_smp_processor_id());
830 v
= apic_read(APIC_ID
);
831 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, GET_APIC_ID(v
));
832 v
= apic_read(APIC_LVR
);
833 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
834 ver
= GET_APIC_VERSION(v
);
835 maxlvt
= get_maxlvt();
837 v
= apic_read(APIC_TASKPRI
);
838 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
840 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
841 v
= apic_read(APIC_ARBPRI
);
842 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
843 v
& APIC_ARBPRI_MASK
);
844 v
= apic_read(APIC_PROCPRI
);
845 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
848 v
= apic_read(APIC_EOI
);
849 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
850 v
= apic_read(APIC_LDR
);
851 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
852 v
= apic_read(APIC_DFR
);
853 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
854 v
= apic_read(APIC_SPIV
);
855 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
857 printk(KERN_DEBUG
"... APIC ISR field:\n");
858 print_APIC_bitfield(APIC_ISR
);
859 printk(KERN_DEBUG
"... APIC TMR field:\n");
860 print_APIC_bitfield(APIC_TMR
);
861 printk(KERN_DEBUG
"... APIC IRR field:\n");
862 print_APIC_bitfield(APIC_IRR
);
864 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
865 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
866 apic_write(APIC_ESR
, 0);
867 v
= apic_read(APIC_ESR
);
868 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
871 v
= apic_read(APIC_ICR
);
872 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
873 v
= apic_read(APIC_ICR2
);
874 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
876 v
= apic_read(APIC_LVTT
);
877 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
879 if (maxlvt
> 3) { /* PC is LVT#4. */
880 v
= apic_read(APIC_LVTPC
);
881 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
883 v
= apic_read(APIC_LVT0
);
884 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
885 v
= apic_read(APIC_LVT1
);
886 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
888 if (maxlvt
> 2) { /* ERR is LVT#3. */
889 v
= apic_read(APIC_LVTERR
);
890 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
893 v
= apic_read(APIC_TMICT
);
894 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
895 v
= apic_read(APIC_TMCCT
);
896 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
897 v
= apic_read(APIC_TDCR
);
898 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
902 void print_all_local_APICs (void)
904 smp_call_function(print_local_APIC
, NULL
, 1, 1);
905 print_local_APIC(NULL
);
908 void /*__init*/ print_PIC(void)
910 unsigned int v
, flags
;
912 printk(KERN_DEBUG
"\nprinting PIC contents\n");
914 v
= inb(0xa1) << 8 | inb(0x21);
915 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
917 v
= inb(0xa0) << 8 | inb(0x20);
918 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
924 v
= inb(0xa0) << 8 | inb(0x20);
927 __restore_flags(flags
);
928 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
930 v
= inb(0x4d1) << 8 | inb(0x4d0);
931 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
934 static void __init
enable_IO_APIC(void)
936 struct IO_APIC_reg_01 reg_01
;
939 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
940 irq_2_pin
[i
].pin
= -1;
941 irq_2_pin
[i
].next
= 0;
944 for (i
= 0; i
< MAX_PIRQS
; i
++)
945 pirq_entries
[i
] = -1;
948 * The number of IO-APIC IRQ registers (== #pins):
950 for (i
= 0; i
< nr_ioapics
; i
++) {
951 *(int *)®_01
= io_apic_read(i
, 1);
952 nr_ioapic_registers
[i
] = reg_01
.entries
+1;
956 * Do not trust the IO-APIC being empty at bootup
962 * Not an __init, needed by the reboot code
964 void disable_IO_APIC(void)
967 * Clear the IO-APIC before rebooting:
971 disconnect_bsp_APIC();
975 * function to set the IO-APIC physical IDs based on the
976 * values stored in the MPC table.
978 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
981 static void __init
setup_ioapic_ids_from_mpc (void)
983 struct IO_APIC_reg_00 reg_00
;
987 * Set the IOAPIC ID to the value stored in the MPC table.
989 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
991 /* Read the register 0 value */
992 *(int *)®_00
= io_apic_read(apic
, 0);
995 * Read the right value from the MPC table and
996 * write it into the ID register.
998 printk(KERN_INFO
"...changing IO-APIC physical APIC ID to %d ...",
999 mp_ioapics
[apic
].mpc_apicid
);
1002 * Sanity check, is the ID really free? Every APIC in the
1003 * system must have a unique ID or we get lots of nice
1004 * 'stuck on smp_invalidate_needed IPI wait' messages.
1006 if (phys_cpu_present_map
& (1<<mp_ioapics
[apic
].mpc_apicid
))
1007 panic("APIC ID %d already used",
1008 mp_ioapics
[apic
].mpc_apicid
);
1010 reg_00
.ID
= mp_ioapics
[apic
].mpc_apicid
;
1011 io_apic_write(apic
, 0, *(int *)®_00
);
1016 *(int *)®_00
= io_apic_read(apic
, 0);
1017 if (reg_00
.ID
!= mp_ioapics
[apic
].mpc_apicid
)
1018 panic("could not set ID!\n");
1025 * There is a nasty bug in some older SMP boards, their mptable lies
1026 * about the timer IRQ. We do the following to work around the situation:
1028 * - timer IRQ defaults to IO-APIC IRQ
1029 * - if this function detects that timer IRQs are defunct, then we fall
1030 * back to ISA timer IRQs
1032 static int __init
timer_irq_works(void)
1034 unsigned int t1
= jiffies
;
1037 /* Let ten ticks pass... */
1038 mdelay((10 * 1000) / HZ
);
1041 * Expect a few ticks at least, to be sure some possible
1042 * glue logic does not lock up after one or two first
1043 * ticks in a non-ExtINT mode. Also the local APIC
1044 * might have cached one ExtINT interrupt. Finally, at
1045 * least one tick may be lost due to delays.
1047 if (jiffies
- t1
> 4)
1053 extern atomic_t nmi_counter
[NR_CPUS
];
1055 static int __init
nmi_irq_works(void)
1057 irq_cpustat_t tmp
[NR_CPUS
];
1060 memcpy(tmp
, irq_stat
, sizeof(tmp
));
1064 for (j
= 0; j
< smp_num_cpus
; j
++) {
1065 cpu
= cpu_logical_map(j
);
1066 if (atomic_read(&nmi_counter(cpu
)) - atomic_read(&tmp
[cpu
].__nmi_counter
) <= 3) {
1067 printk(KERN_WARNING
"CPU#%d NMI appears to be stuck.\n", cpu
);
1075 * In the SMP+IOAPIC case it might happen that there are an unspecified
1076 * number of pending IRQ events unhandled. These cases are very rare,
1077 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1078 * better to do it this way as thus we do not have to be aware of
1079 * 'pending' interrupts in the IRQ path, except at this point.
1082 * Edge triggered needs to resend any interrupt
1083 * that was delayed but this is now handled in the device
1086 #define enable_edge_ioapic_irq unmask_IO_APIC_irq
1088 static void disable_edge_ioapic_irq (unsigned int irq
) { /* nothing */ }
1091 * Starting up a edge-triggered IO-APIC interrupt is
1092 * nasty - we need to make sure that we get the edge.
1093 * If it is already asserted for some reason, we need
1094 * return 1 to indicate that is was pending.
1096 * This is not complete - we should be able to fake
1097 * an edge even if it isn't on the 8259A...
1100 static unsigned int startup_edge_ioapic_irq(unsigned int irq
)
1102 int was_pending
= 0;
1103 unsigned long flags
;
1105 spin_lock_irqsave(&ioapic_lock
, flags
);
1107 disable_8259A_irq(irq
);
1108 if (i8259A_irq_pending(irq
))
1111 __unmask_IO_APIC_irq(irq
);
1112 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1117 #define shutdown_edge_ioapic_irq disable_edge_ioapic_irq
1120 * Once we have recorded IRQ_PENDING already, we can mask the
1121 * interrupt for real. This prevents IRQ storms from unhandled
1124 static void ack_edge_ioapic_irq(unsigned int irq
)
1126 if ((irq_desc
[irq
].status
& (IRQ_PENDING
| IRQ_DISABLED
))
1127 == (IRQ_PENDING
| IRQ_DISABLED
))
1128 mask_IO_APIC_irq(irq
);
1132 static void end_edge_ioapic_irq (unsigned int i
) { /* nothing */ }
1136 * Level triggered interrupts can just be masked,
1137 * and shutting down and starting up the interrupt
1138 * is the same as enabling and disabling them -- except
1139 * with a startup need to return a "was pending" value.
1141 * Level triggered interrupts are special because we
1142 * do not touch any IO-APIC register while handling
1143 * them. We ack the APIC in the end-IRQ handler, not
1144 * in the start-IRQ-handler. Protection against reentrance
1145 * from the same interrupt is still provided, both by the
1146 * generic IRQ layer and by the fact that an unacked local
1147 * APIC does not accept IRQs.
1149 static unsigned int startup_level_ioapic_irq (unsigned int irq
)
1151 unmask_IO_APIC_irq(irq
);
1153 return 0; /* don't check for pending */
1156 #define shutdown_level_ioapic_irq mask_IO_APIC_irq
1157 #define enable_level_ioapic_irq unmask_IO_APIC_irq
1158 #define disable_level_ioapic_irq mask_IO_APIC_irq
1160 static void end_level_ioapic_irq (unsigned int i
)
1165 static void mask_and_ack_level_ioapic_irq (unsigned int i
) { /* nothing */ }
1167 static void set_ioapic_affinity (unsigned int irq
, unsigned long mask
)
1169 unsigned long flags
;
1171 * Only the first 8 bits are valid.
1175 spin_lock_irqsave(&ioapic_lock
, flags
);
1176 __DO_ACTION(1, = mask
, )
1177 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1181 * Level and edge triggered IO-APIC interrupts need different handling,
1182 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1183 * handled with the level-triggered descriptor, but that one has slightly
1184 * more overhead. Level-triggered interrupts cannot be handled with the
1185 * edge-triggered handler, without risking IRQ storms and other ugly
1189 static struct hw_interrupt_type ioapic_edge_irq_type
= {
1191 startup_edge_ioapic_irq
,
1192 shutdown_edge_ioapic_irq
,
1193 enable_edge_ioapic_irq
,
1194 disable_edge_ioapic_irq
,
1195 ack_edge_ioapic_irq
,
1196 end_edge_ioapic_irq
,
1197 set_ioapic_affinity
,
1200 static struct hw_interrupt_type ioapic_level_irq_type
= {
1202 startup_level_ioapic_irq
,
1203 shutdown_level_ioapic_irq
,
1204 enable_level_ioapic_irq
,
1205 disable_level_ioapic_irq
,
1206 mask_and_ack_level_ioapic_irq
,
1207 end_level_ioapic_irq
,
1208 set_ioapic_affinity
,
1211 static inline void init_IO_APIC_traps(void)
1216 * NOTE! The local APIC isn't very good at handling
1217 * multiple interrupts at the same interrupt level.
1218 * As the interrupt level is determined by taking the
1219 * vector number and shifting that right by 4, we
1220 * want to spread these out a bit so that they don't
1221 * all fall in the same interrupt level.
1223 * Also, we've got to be careful not to trash gate
1224 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1226 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
1227 if (IO_APIC_IRQ(irq
) && !IO_APIC_VECTOR(irq
)) {
1229 * Hmm.. We don't have an entry for this,
1230 * so default to an old-fashioned 8259
1231 * interrupt if we can..
1234 make_8259A_irq(irq
);
1236 /* Strange. Oh, well.. */
1237 irq_desc
[irq
].handler
= &no_irq_type
;
1242 static void ack_lapic_irq (unsigned int irq
)
1247 static void end_lapic_irq (unsigned int i
) { /* nothing */ }
1249 static struct hw_interrupt_type lapic_irq_type
= {
1251 NULL
, /* startup_irq() not used for IRQ0 */
1252 NULL
, /* shutdown_irq() not used for IRQ0 */
1253 NULL
, /* enable_irq() not used for IRQ0 */
1254 NULL
, /* disable_irq() not used for IRQ0 */
1259 static void enable_NMI_through_LVT0 (void * dummy
)
1261 unsigned int v
, ver
;
1263 ver
= apic_read(APIC_LVR
);
1264 ver
= GET_APIC_VERSION(ver
);
1265 v
= APIC_DM_NMI
; /* unmask and set to NMI */
1266 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
1267 v
|= APIC_LVT_LEVEL_TRIGGER
;
1268 apic_write_around(APIC_LVT0
, v
);
1271 static void setup_nmi (void)
1274 * Dirty trick to enable the NMI watchdog ...
1275 * We put the 8259A master into AEOI mode and
1276 * unmask on all local APICs LVT0 as NMI.
1278 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1279 * is from Maciej W. Rozycki - so we do not have to EOI from
1280 * the NMI handler or the timer interrupt.
1282 printk(KERN_INFO
"activating NMI Watchdog ...");
1284 smp_call_function(enable_NMI_through_LVT0
, NULL
, 1, 1);
1285 enable_NMI_through_LVT0(NULL
);
1291 * This code may look a bit paranoid, but it's supposed to cooperate with
1292 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1293 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1294 * fanatically on his truly buggy board.
1296 static inline void check_timer(void)
1302 * get/set the timer IRQ vector:
1304 disable_8259A_irq(0);
1305 vector
= assign_irq_vector(0);
1306 set_intr_gate(vector
, interrupt
[0]);
1308 pin1
= find_timer_pin(mp_INT
);
1309 pin2
= find_timer_pin(mp_ExtINT
);
1311 printk(KERN_INFO
"..TIMER: vector=%d pin1=%d pin2=%d\n", vector
, pin1
, pin2
);
1315 * Ok, does IRQ0 through the IOAPIC work?
1317 unmask_IO_APIC_irq(0);
1318 if (timer_irq_works()) {
1320 disable_8259A_irq(0);
1323 enable_8259A_irq(0);
1328 clear_IO_APIC_pin(0, pin1
);
1329 printk(KERN_ERR
"..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1332 printk(KERN_INFO
"...trying to set up timer (IRQ0) through the 8259A ... ");
1334 printk("\n..... (found pin %d) ...", pin2
);
1336 * legacy devices should be connected to IO APIC #0
1338 setup_ExtINT_IRQ0_pin(pin2
, vector
);
1339 if (timer_irq_works()) {
1348 * Cleanup, just in case ...
1350 clear_IO_APIC_pin(0, pin2
);
1352 printk(" failed.\n");
1355 printk(KERN_WARNING
"timer doesnt work through the IO-APIC - disabling NMI Watchdog!\n");
1359 printk(KERN_INFO
"...trying to set up timer as Virtual Wire IRQ...");
1361 disable_8259A_irq(0);
1362 irq_desc
[0].handler
= &lapic_irq_type
;
1363 init_8259A(1); /* AEOI mode */
1364 apic_write_around(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
1365 enable_8259A_irq(0);
1367 if (timer_irq_works()) {
1368 printk(" works.\n");
1371 printk(" failed :(.\n");
1372 panic("IO-APIC + timer doesn't work! pester mingo@redhat.com");
1377 * IRQ's that are handled by the old PIC in all cases:
1378 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1379 * Linux doesn't really care, as it's not actually used
1380 * for any interrupt handling anyway.
1381 * - IRQ13 is the FPU error IRQ, and may be connected
1382 * directly from the FPU to the old PIC. Linux doesn't
1383 * really care, because Linux doesn't want to use IRQ13
1384 * anyway (exception 16 is the proper FPU error signal)
1386 * Additionally, something is definitely wrong with irq9
1389 #define PIC_IRQS ((1<<2)|(1<<13))
1391 void __init
setup_IO_APIC(void)
1395 io_apic_irqs
= ~PIC_IRQS
;
1396 printk("ENABLING IO-APIC IRQs\n");
1399 * Set up the IO-APIC IRQ routing table by parsing the MP-BIOS
1402 setup_ioapic_ids_from_mpc();
1404 setup_IO_APIC_irqs();
1405 init_IO_APIC_traps();
1412 * This initializes the IO-APIC and APIC hardware if this is
1415 void IO_APIC_init_uniprocessor (void)
1417 if (!smp_found_config
)
1422 setup_APIC_clocks();