include/asm-ia64/hw_irq.h

   1 #ifndef _ASM_IA64_HW_IRQ_H
   2 #define _ASM_IA64_HW_IRQ_H
   3
   4 /*
   5  * Copyright (C) 2001-2003 Hewlett-Packard Co
   6  *      David Mosberger-Tang <davidm@hpl.hp.com>
   7  */
   8
   9 #include <linux/interrupt.h>
  10 #include <linux/sched.h>
  11 #include <linux/types.h>
  12
  13 #include <asm/machvec.h>
  14 #include <asm/ptrace.h>
  15 #include <asm/smp.h>
  16
  17 typedef u8 ia64_vector;
  18
  19 /*
  20  * 0 special
  21  *
  22  * 1,3-14 are reserved from firmware
  23  *
  24  * 16-255 (vectored external interrupts) are available
  25  *
  26  * 15 spurious interrupt (see IVR)
  27  *
  28  * 16 lowest priority, 255 highest priority
  29  *
  30  * 15 classes of 16 interrupts each.
  31  */
  32 #define IA64_MIN_VECTORED_IRQ            16
  33 #define IA64_MAX_VECTORED_IRQ           255
  34 #define IA64_NUM_VECTORS                256
  35
  36 #define IA64_SPURIOUS_INT_VECTOR        0x0f
  37
  38 /*
  39  * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI.
  40  */
  41 #define IA64_PCE_VECTOR                 0x1e    /* platform corrected error interrupt vector */
  42 #define IA64_CMC_VECTOR                 0x1f    /* correctable machine-check interrupt vector */
  43 /*
  44  * Vectors 0x20-0x2f are reserved for legacy ISA IRQs.
  45  */
  46 #define IA64_FIRST_DEVICE_VECTOR        0x30
  47 #define IA64_LAST_DEVICE_VECTOR         0xe7
  48
  49 #define IA64_MCA_RENDEZ_VECTOR          0xe8    /* MCA rendez interrupt */
  50 #define IA64_PERFMON_VECTOR             0xee    /* performanc monitor interrupt vector */
  51 #define IA64_TIMER_VECTOR               0xef    /* use highest-prio group 15 interrupt for timer */
  52 #define IA64_MCA_WAKEUP_VECTOR          0xf0    /* MCA wakeup (must be >MCA_RENDEZ_VECTOR) */
  53 #define IA64_IPI_RESCHEDULE             0xfd    /* SMP reschedule */
  54 #define IA64_IPI_VECTOR                 0xfe    /* inter-processor interrupt vector */
  55
  56 /* Used for encoding redirected irqs */
  57
  58 #define IA64_IRQ_REDIRECTED             (1 << 31)
  59
  60 /* IA64 inter-cpu interrupt related definitions */
  61
  62 #define IA64_IPI_DEFAULT_BASE_ADDR      0xfee00000
  63
  64 /* Delivery modes for inter-cpu interrupts */
  65 enum {
  66         IA64_IPI_DM_INT =       0x0,    /* pend an external interrupt */
  67         IA64_IPI_DM_PMI =       0x2,    /* pend a PMI */
  68         IA64_IPI_DM_NMI =       0x4,    /* pend an NMI (vector 2) */
  69         IA64_IPI_DM_INIT =      0x5,    /* pend an INIT interrupt */
  70         IA64_IPI_DM_EXTINT =    0x7,    /* pend an 8259-compatible interrupt. */
  71 };
  72
  73 extern __u8 isa_irq_to_vector_map[16];
  74 #define isa_irq_to_vector(x)    isa_irq_to_vector_map[(x)]
  75
  76 extern unsigned long ipi_base_addr;
  77
  78 extern struct hw_interrupt_type irq_type_ia64_lsapic;   /* CPU-internal interrupt controller */
  79
  80 extern int ia64_alloc_vector (void);    /* allocate a free vector */
  81 extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect);
  82 extern void register_percpu_irq (ia64_vector vec, struct irqaction *action);
  83
  84 static inline void
  85 hw_resend_irq (struct hw_interrupt_type *h, unsigned int vector)
  86 {
  87         platform_send_ipi(smp_processor_id(), vector, IA64_IPI_DM_INT, 0);
  88 }
  89
  90 /*
  91  * Default implementations for the irq-descriptor API:
  92  */
  93
  94 extern irq_desc_t _irq_desc[NR_IRQS];
  95
  96 #ifndef CONFIG_IA64_GENERIC
  97 static inline irq_desc_t *
  98 __ia64_irq_desc (unsigned int irq)
  99 {
 100         return _irq_desc + irq;
 101 }
 102
 103 static inline ia64_vector
 104 __ia64_irq_to_vector (unsigned int irq)
 105 {
 106         return (ia64_vector) irq;
 107 }
 108
 109 static inline unsigned int
 110 __ia64_local_vector_to_irq (ia64_vector vec)
 111 {
 112         return (unsigned int) vec;
 113 }
 114 #endif
 115
 116 /*
 117  * Next follows the irq descriptor interface.  On IA-64, each CPU supports 256 interrupt
 118  * vectors.  On smaller systems, there is a one-to-one correspondence between interrupt
 119  * vectors and the Linux irq numbers.  However, larger systems may have multiple interrupt
 120  * domains meaning that the translation from vector number to irq number depends on the
 121  * interrupt domain that a CPU belongs to.  This API abstracts such platform-dependent
 122  * differences and provides a uniform means to translate between vector and irq numbers
 123  * and to obtain the irq descriptor for a given irq number.
 124  */
 125
 126 /* Return a pointer to the irq descriptor for IRQ.  */
 127 static inline irq_desc_t *
 128 irq_descp (int irq)
 129 {
 130         return platform_irq_desc(irq);
 131 }
 132
 133 /* Extract the IA-64 vector that corresponds to IRQ.  */
 134 static inline ia64_vector
 135 irq_to_vector (int irq)
 136 {
 137         return platform_irq_to_vector(irq);
 138 }
 139
 140 /*
 141  * Convert the local IA-64 vector to the corresponding irq number.  This translation is
 142  * done in the context of the interrupt domain that the currently executing CPU belongs
 143  * to.
 144  */
 145 static inline unsigned int
 146 local_vector_to_irq (ia64_vector vec)
 147 {
 148         return platform_local_vector_to_irq(vec);
 149 }
 150
 151 #endif /* _ASM_IA64_HW_IRQ_H */