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Merge with Linux 2.5.74.
[linux-2.6/linux-mips.git] / drivers / ide / pci / sc1200.c
blobaecc915b30ea31dbcd99d3b241f216fb52ef0da1
1 /*
2 * linux/drivers/ide/pci/sc1200.c Version 0.91 28-Jan-2003
3 *
4 * Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com>
5 * May be copied or modified under the terms of the GNU General Public License
6 *
7 * Development of this chipset driver was funded
8 * by the nice folks at National Semiconductor.
9 *
10 * Documentation:
11 * Available from National Semiconductor
12 */
13
14 #include <linux/config.h>
15 #include <linux/module.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/delay.h>
19 #include <linux/timer.h>
20 #include <linux/mm.h>
21 #include <linux/ioport.h>
22 #include <linux/blkdev.h>
23 #include <linux/hdreg.h>
24 #include <linux/interrupt.h>
25 #include <linux/pci.h>
26 #include <linux/init.h>
27 #include <linux/ide.h>
28 #include <linux/pm.h>
29 #include <asm/io.h>
30 #include <asm/irq.h>
31
32 #include "ide_modes.h"
33 #include "sc1200.h"
34
35 #define SC1200_REV_A 0x00
36 #define SC1200_REV_B1 0x01
37 #define SC1200_REV_B3 0x02
38 #define SC1200_REV_C1 0x03
39 #define SC1200_REV_D1 0x04
40
41 #define PCI_CLK_33 0x00
42 #define PCI_CLK_48 0x01
43 #define PCI_CLK_66 0x02
44 #define PCI_CLK_33A 0x03
45
46 static unsigned short sc1200_get_pci_clock (void)
47 {
48 unsigned char chip_id, silicon_revision;
49 unsigned int pci_clock;
50 /*
51 * Check the silicon revision, as not all versions of the chip
52 * have the register with the fast PCI bus timings.
53 */
54 chip_id = inb (0x903c);
55 silicon_revision = inb (0x903d);
56
57 // Read the fast pci clock frequency
58 if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) {
59 pci_clock = PCI_CLK_33;
60 } else {
61 // check clock generator configuration (cfcc)
62 // the clock is in bits 8 and 9 of this word
63
64 pci_clock = inw (0x901e);
65 pci_clock >>= 8;
66 pci_clock &= 0x03;
67 if (pci_clock == PCI_CLK_33A)
68 pci_clock = PCI_CLK_33;
69 }
70 return pci_clock;
71 }
72
73 #define DISPLAY_SC1200_TIMINGS
74
75 #if defined(DISPLAY_SC1200_TIMINGS) && defined(CONFIG_PROC_FS)
76 #include <linux/stat.h>
77 #include <linux/proc_fs.h>
78
79 static int sc1200_get_info(char *, char **, off_t, int);
80 extern int (*sc1200_display_info)(char *, char **, off_t, int); /* ide-proc.c */
81 extern char *ide_media_verbose(ide_drive_t *);
82 static u8 sc1200_proc = 0;
83
84 static struct pci_dev *bmide_dev;
85
86 static int sc1200_get_info (char *buffer, char **addr, off_t offset, int count)
87 {
88 char *p = buffer;
89 unsigned long bibma = pci_resource_start(bmide_dev, 4);
90 int len;
91 u8 c0 = 0, c1 = 0;
92
93 /*
94 * at that point bibma+0x2 et bibma+0xa are byte registers
95 * to investigate:
96 */
97
98 c0 = inb_p(bibma + 0x02);
99 c1 = inb_p(bibma + 0x0a);
100
101 p += sprintf(p, "\n National SCx200 Chipset.\n");
102 p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
103 p += sprintf(p, " %sabled %sabled\n",
104 (c0&0x80) ? "dis" : " en",
105 (c1&0x80) ? "dis" : " en");
106 p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n");
107 p += sprintf(p, "DMA enabled: %s %s %s %s\n",
108 (c0&0x20) ? "yes" : "no ", (c0&0x40) ? "yes" : "no ",
109 (c1&0x20) ? "yes" : "no ", (c1&0x40) ? "yes" : "no " );
110
111 p += sprintf(p, "UDMA\n");
112 p += sprintf(p, "DMA\n");
113 p += sprintf(p, "PIO\n");
114
115 len = (p - buffer) - offset;
116 *addr = buffer + offset;
117
118 return len > count ? count : len;
119 }
120 #endif /* DISPLAY_SC1200_TIMINGS && CONFIG_PROC_FS */
121
122 extern char *ide_xfer_verbose (byte xfer_rate);
123
124 /*
125 * Set a new transfer mode at the drive
126 */
127 int sc1200_set_xfer_mode (ide_drive_t *drive, byte mode)
128 {
129 printk("%s: sc1200_set_xfer_mode(%s)\n", drive->name, ide_xfer_verbose(mode));
130 return ide_config_drive_speed(drive, mode);
131 }
132
133 /*
134 * Here are the standard PIO mode 0-4 timings for each "format".
135 * Format-0 uses fast data reg timings, with slower command reg timings.
136 * Format-1 uses fast timings for all registers, but won't work with all drives.
137 */
138 static const unsigned int sc1200_pio_timings[4][5] =
139 {{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz
140 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz
141 {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021}, // format1, 48Mhz
142 {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz
143
144 /*
145 * After chip reset, the PIO timings are set to 0x00009172, which is not valid.
146 */
147 //#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)
148
149 static int sc1200_autoselect_dma_mode (ide_drive_t *drive)
150 {
151 int udma_ok = 1, mode = 0;
152 ide_hwif_t *hwif = HWIF(drive);
153 int unit = drive->select.b.unit;
154 ide_drive_t *mate = &hwif->drives[unit^1];
155 struct hd_driveid *id = drive->id;
156
157 /*
158 * The SC1200 specifies that two drives sharing a cable cannot
159 * mix UDMA/MDMA. It has to be one or the other, for the pair,
160 * though different timings can still be chosen for each drive.
161 * We could set the appropriate timing bits on the fly,
162 * but that might be a bit confusing. So, for now we statically
163 * handle this requirement by looking at our mate drive to see
164 * what it is capable of, before choosing a mode for our own drive.
165 */
166 if (mate->present) {
167 struct hd_driveid *mateid = mate->id;
168 if (mateid && (mateid->capability & 1) && !hwif->ide_dma_bad_drive(mate)) {
169 if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
170 udma_ok = 1;
171 else if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
172 udma_ok = 0;
173 else
174 udma_ok = 1;
175 }
176 }
177 /*
178 * Now see what the current drive is capable of,
179 * selecting UDMA only if the mate said it was ok.
180 */
181 if (id && (id->capability & 1) && hwif->autodma && !hwif->ide_dma_bad_drive(drive)) {
182 if (udma_ok && (id->field_valid & 4) && (id->dma_ultra & 7)) {
183 if (id->dma_ultra & 4)
184 mode = XFER_UDMA_2;
185 else if (id->dma_ultra & 2)
186 mode = XFER_UDMA_1;
187 else if (id->dma_ultra & 1)
188 mode = XFER_UDMA_0;
189 }
190 if (!mode && (id->field_valid & 2) && (id->dma_mword & 7)) {
191 if (id->dma_mword & 4)
192 mode = XFER_MW_DMA_2;
193 else if (id->dma_mword & 2)
194 mode = XFER_MW_DMA_1;
195 else if (id->dma_mword & 1)
196 mode = XFER_MW_DMA_0;
197 }
198 }
199 return mode;
200 }
201
202 /*
203 * sc1200_config_dma2() handles selection/setting of DMA/UDMA modes
204 * for both the chipset and drive.
205 */
206 static int sc1200_config_dma2 (ide_drive_t *drive, int mode)
207 {
208 ide_hwif_t *hwif = HWIF(drive);
209 int unit = drive->select.b.unit;
210 unsigned int reg, timings;
211 unsigned short pci_clock;
212 unsigned int basereg = hwif->channel ? 0x50 : 0x40;
213
214 /*
215 * Default to DMA-off in case we run into trouble here.
216 */
217 hwif->ide_dma_off_quietly(drive); /* turn off DMA while we fiddle */
218 outb(inb(hwif->dma_base+2)&~(unit?0x40:0x20), hwif->dma_base+2); /* clear DMA_capable bit */
219
220 /*
221 * Tell the drive to switch to the new mode; abort on failure.
222 */
223 if (!mode || sc1200_set_xfer_mode(drive, mode)) {
224 printk("SC1200: set xfer mode failure\n");
225 return 1; /* failure */
226 }
227
228 pci_clock = sc1200_get_pci_clock();
229
230 /*
231 * Now tune the chipset to match the drive:
232 *
233 * Note that each DMA mode has several timings associated with it.
234 * The correct timing depends on the fast PCI clock freq.
235 */
236 timings = 0;
237 switch (mode) {
238 case XFER_UDMA_0:
239 switch (pci_clock) {
240 case PCI_CLK_33: timings = 0x00921250; break;
241 case PCI_CLK_48: timings = 0x00932470; break;
242 case PCI_CLK_66: timings = 0x009436a1; break;
243 }
244 break;
245 case XFER_UDMA_1:
246 switch (pci_clock) {
247 case PCI_CLK_33: timings = 0x00911140; break;
248 case PCI_CLK_48: timings = 0x00922260; break;
249 case PCI_CLK_66: timings = 0x00933481; break;
250 }
251 break;
252 case XFER_UDMA_2:
253 switch (pci_clock) {
254 case PCI_CLK_33: timings = 0x00911030; break;
255 case PCI_CLK_48: timings = 0x00922140; break;
256 case PCI_CLK_66: timings = 0x00923261; break;
257 }
258 break;
259 case XFER_MW_DMA_0:
260 switch (pci_clock) {
261 case PCI_CLK_33: timings = 0x00077771; break;
262 case PCI_CLK_48: timings = 0x000bbbb2; break;
263 case PCI_CLK_66: timings = 0x000ffff3; break;
264 }
265 break;
266 case XFER_MW_DMA_1:
267 switch (pci_clock) {
268 case PCI_CLK_33: timings = 0x00012121; break;
269 case PCI_CLK_48: timings = 0x00024241; break;
270 case PCI_CLK_66: timings = 0x00035352; break;
271 }
272 break;
273 case XFER_MW_DMA_2:
274 switch (pci_clock) {
275 case PCI_CLK_33: timings = 0x00002020; break;
276 case PCI_CLK_48: timings = 0x00013131; break;
277 case PCI_CLK_66: timings = 0x00015151; break;
278 }
279 break;
280 }
281
282 if (timings == 0) {
283 printk("%s: sc1200_config_dma: huh? mode=%02x clk=%x \n", drive->name, mode, pci_clock);
284 return 1; /* failure */
285 }
286
287 if (unit == 0) { /* are we configuring drive0? */
288 pci_read_config_dword(hwif->pci_dev, basereg+4, &reg);
289 timings |= reg & 0x80000000; /* preserve PIO format bit */
290 pci_write_config_dword(hwif->pci_dev, basereg+4, timings);
291 } else {
292 pci_write_config_dword(hwif->pci_dev, basereg+12, timings);
293 }
294
295 outb(inb(hwif->dma_base+2)|(unit?0x40:0x20), hwif->dma_base+2); /* set DMA_capable bit */
296
297 /*
298 * Finally, turn DMA on in software, and exit.
299 */
300 return hwif->ide_dma_on(drive); /* success */
301 }
302
303 /*
304 * sc1200_config_dma() handles selection/setting of DMA/UDMA modes
305 * for both the chipset and drive.
306 */
307 static int sc1200_config_dma (ide_drive_t *drive)
308 {
309 return sc1200_config_dma2(drive, sc1200_autoselect_dma_mode(drive));
310 }
311
312
313 /* Replacement for the standard ide_dma_end action in
314 * dma_proc.
315 *
316 * returns 1 on error, 0 otherwise
317 */
318 int sc1200_ide_dma_end (ide_drive_t *drive)
319 {
320 ide_hwif_t *hwif = HWIF(drive);
321 unsigned long dma_base = hwif->dma_base;
322 byte dma_stat;
323
324 dma_stat = inb(dma_base+2); /* get DMA status */
325
326 if (!(dma_stat & 4))
327 printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n",
328 dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2));
329
330 outb(dma_stat|0x1b, dma_base+2); /* clear the INTR & ERROR bits */
331 outb(inb(dma_base)&~1, dma_base); /* !! DO THIS HERE !! stop DMA */
332
333 drive->waiting_for_dma = 0;
334 ide_destroy_dmatable(drive); /* purge DMA mappings */
335
336 return (dma_stat & 7) != 4; /* verify good DMA status */
337 }
338
339 /*
340 * sc1200_tuneproc() handles selection/setting of PIO modes
341 * for both the chipset and drive.
342 *
343 * All existing BIOSs for this chipset guarantee that all drives
344 * will have valid default PIO timings set up before we get here.
345 */
346 static void sc1200_tuneproc (ide_drive_t *drive, byte pio) /* mode=255 means "autotune" */
347 {
348 ide_hwif_t *hwif = HWIF(drive);
349 unsigned int format;
350 static byte modes[5] = {XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3, XFER_PIO_4};
351 int mode = -1;
352
353 switch (pio) {
354 case 200: mode = XFER_UDMA_0; break;
355 case 201: mode = XFER_UDMA_1; break;
356 case 202: mode = XFER_UDMA_2; break;
357 case 100: mode = XFER_MW_DMA_0; break;
358 case 101: mode = XFER_MW_DMA_1; break;
359 case 102: mode = XFER_MW_DMA_2; break;
360 }
361 if (mode != -1) {
362 printk("SC1200: %s: changing (U)DMA mode\n", drive->name);
363 (void)sc1200_config_dma2(drive, mode);
364 return;
365 }
366
367 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
368 printk("SC1200: %s: setting PIO mode%d\n", drive->name, pio);
369 if (!sc1200_set_xfer_mode(drive, modes[pio])) {
370 unsigned int basereg = hwif->channel ? 0x50 : 0x40;
371 pci_read_config_dword (hwif->pci_dev, basereg+4, &format);
372 format = (format >> 31) & 1;
373 if (format)
374 format += sc1200_get_pci_clock();
375 pci_write_config_dword(hwif->pci_dev, basereg + (drive->select.b.unit << 3), sc1200_pio_timings[format][pio]);
376 }
377 }
378
379 static ide_hwif_t *lookup_pci_dev (ide_hwif_t *prev, struct pci_dev *dev)
380 {
381 int h;
382
383 for (h = 0; h < MAX_HWIFS; h++) {
384 ide_hwif_t *hwif = &ide_hwifs[h];
385 if (prev) {
386 if (hwif == prev)
387 prev = NULL; // found previous, now look for next match
388 } else {
389 if (hwif && hwif->pci_dev == dev)
390 return hwif; // found next match
391 }
392 }
393 return NULL; // not found
394 }
395
396 typedef struct sc1200_saved_state_s {
397 __u32 regs[4];
398 } sc1200_saved_state_t;
399
400 static int sc1200_save_state (struct pci_dev *dev, u32 state)
401 {
402 ide_hwif_t *hwif = NULL;
403
404 printk("SC1200: save_state(%u)\n", state);
405 if (state != 0)
406 return 0; // we only save state when going from full power to less
407 //
408 // Loop over all interfaces that are part of this PCI device:
409 //
410 while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) {
411 sc1200_saved_state_t *ss;
412 unsigned int basereg, r;
413 //
414 // allocate a permanent save area, if not already allocated
415 //
416 ss = (sc1200_saved_state_t *)hwif->config_data;
417 if (ss == NULL) {
418 ss = kmalloc(sizeof(sc1200_saved_state_t), GFP_KERNEL);
419 if (ss == NULL)
420 return -ENOMEM;
421 (sc1200_saved_state_t *)hwif->config_data = ss;
422 }
423 ss = (sc1200_saved_state_t *)hwif->config_data;
424 //
425 // Save timing registers: this may be unnecessary if BIOS also does it
426 //
427 basereg = hwif->channel ? 0x50 : 0x40;
428 for (r = 0; r < 4; ++r) {
429 pci_read_config_dword (hwif->pci_dev, basereg + (r<<2), &ss->regs[r]);
430 }
431 }
432 return 0;
433 }
434
435 static int sc1200_suspend (struct pci_dev *dev, u32 state)
436 {
437 printk("SC1200: suspend(%u)\n", state);
438 /* You don't need to iterate over disks -- sysfs should have done that for you already */
439
440 pci_disable_device(dev);
441 pci_set_power_state(dev,state);
442 dev->current_state = state;
443 return 0;
444 }
445
446 static int sc1200_resume (struct pci_dev *dev)
447 {
448 ide_hwif_t *hwif = NULL;
449
450 printk("SC1200: resume\n");
451 pci_set_power_state(dev,0); // bring chip back from sleep state
452 dev->current_state = 0;
453 pci_enable_device(dev);
454 //
455 // loop over all interfaces that are part of this pci device:
456 //
457 while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) {
458 unsigned int basereg, r, d, format;
459 sc1200_saved_state_t *ss = (sc1200_saved_state_t *)hwif->config_data;
460 printk("%s: SC1200: resume\n", hwif->name);
461
462 //
463 // Restore timing registers: this may be unnecessary if BIOS also does it
464 //
465 basereg = hwif->channel ? 0x50 : 0x40;
466 if (ss != NULL) {
467 for (r = 0; r < 4; ++r) {
468 pci_write_config_dword(hwif->pci_dev, basereg + (r<<2), ss->regs[r]);
469 }
470 }
471 //
472 // Re-program drive PIO modes
473 //
474 pci_read_config_dword(hwif->pci_dev, basereg+4, &format);
475 format = (format >> 31) & 1;
476 if (format)
477 format += sc1200_get_pci_clock();
478 for (d = 0; d < 2; ++d) {
479 ide_drive_t *drive = &(hwif->drives[d]);
480 if (drive->present) {
481 unsigned int pio, timings;
482 pci_read_config_dword(hwif->pci_dev, basereg+(drive->select.b.unit << 3), &timings);
483 for (pio = 0; pio <= 4; ++pio) {
484 if (sc1200_pio_timings[format][pio] == timings)
485 break;
486 }
487 if (pio > 4)
488 pio = 255; /* autotune */
489 (void)sc1200_tuneproc(drive, pio);
490 }
491 }
492 //
493 // Re-program drive DMA modes
494 //
495 for (d = 0; d < MAX_DRIVES; ++d) {
496 ide_drive_t *drive = &(hwif->drives[d]);
497 if (drive->present && !hwif->ide_dma_bad_drive(drive)) {
498 int was_using_dma = drive->using_dma;
499 hwif->ide_dma_off_quietly(drive);
500 sc1200_config_dma(drive);
501 if (!was_using_dma && drive->using_dma) {
502 hwif->ide_dma_off_quietly(drive);
503 }
504 }
505 }
506 }
507 return 0;
508 }
509
510 /*
511 * Initialize the sc1200 bridge for reliable IDE DMA operation.
512 */
513 static unsigned int __init init_chipset_sc1200 (struct pci_dev *dev, const char *name)
514 {
515 #if defined(DISPLAY_SC1200_TIMINGS) && defined(CONFIG_PROC_FS)
516 if (!bmide_dev) {
517 sc1200_proc = 1;
518 bmide_dev = dev;
519 ide_pci_register_host_proc(&sc1200_procs[0]);
520 }
521 #endif /* DISPLAY_SC1200_TIMINGS && CONFIG_PROC_FS */
522 return 0;
523 }
524
525 /*
526 * This gets invoked by the IDE driver once for each channel,
527 * and performs channel-specific pre-initialization before drive probing.
528 */
529 static void __init init_hwif_sc1200 (ide_hwif_t *hwif)
530 {
531 if (hwif->mate)
532 hwif->serialized = hwif->mate->serialized = 1;
533 hwif->autodma = 0;
534 if (hwif->dma_base) {
535 hwif->ide_dma_check = &sc1200_config_dma;
536 hwif->ide_dma_end = &sc1200_ide_dma_end;
537 if (!noautodma)
538 hwif->autodma = 1;
539 hwif->tuneproc = &sc1200_tuneproc;
540 }
541 hwif->atapi_dma = 1;
542 hwif->ultra_mask = 0x07;
543 hwif->mwdma_mask = 0x07;
544
545 hwif->drives[0].autodma = hwif->autodma;
546 hwif->drives[1].autodma = hwif->autodma;
547 }
548
549 static void __init init_dma_sc1200 (ide_hwif_t *hwif, unsigned long dmabase)
550 {
551 ide_setup_dma(hwif, dmabase, 8);
552 }
553
554 extern void ide_setup_pci_device(struct pci_dev *, ide_pci_device_t *);
555
556
557 static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
558 {
559 ide_pci_device_t *d = &sc1200_chipsets[id->driver_data];
560 if (dev->device != d->device)
561 BUG();
562 ide_setup_pci_device(dev, d);
563 MOD_INC_USE_COUNT;
564 return 0;
565 }
566
567 static struct pci_device_id sc1200_pci_tbl[] __devinitdata = {
568 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SCx200_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
569 { 0, },
570 };
571
572 static struct pci_driver driver = {
573 .name = "SC1200 IDE",
574 .id_table = sc1200_pci_tbl,
575 .probe = sc1200_init_one,
576 .save_state = sc1200_save_state,
577 .suspend = sc1200_suspend,
578 .resume = sc1200_resume,
579 };
580
581 static int sc1200_ide_init(void)
582 {
583 return ide_pci_register_driver(&driver);
584 }
585
586 static void sc1200_ide_exit(void)
587 {
588 ide_pci_unregister_driver(&driver);
589 }
590
591 module_init(sc1200_ide_init);
592 module_exit(sc1200_ide_exit);
593
594 MODULE_AUTHOR("Mark Lord");
595 MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE");
596 MODULE_LICENSE("GPL");
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