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Merge with Linux 2.5.74.
[linux-2.6/linux-mips.git] / drivers / char / agp / nvidia-agp.c
blob776e831fcff6dbe3fc4381bdd7613fbc23931c13
1 /*
2 * Nvidia AGPGART routines.
3 * Based upon a 2.4 agpgart diff by the folks from NVIDIA, and hacked up
4 * to work in 2.5 by Dave Jones <davej@codemonkey.org.uk>
5 */
6
7 #include <linux/module.h>
8 #include <linux/pci.h>
9 #include <linux/init.h>
10 #include <linux/agp_backend.h>
11 #include <linux/gfp.h>
12 #include <linux/page-flags.h>
13 #include <linux/mm.h>
14 #include "agp.h"
15
16
17 /* registers */
18 #define NVIDIA_0_APBASE 0x10
19 #define NVIDIA_0_APSIZE 0x80
20 #define NVIDIA_1_WBC 0xf0
21 #define NVIDIA_2_GARTCTRL 0xd0
22 #define NVIDIA_2_APBASE 0xd8
23 #define NVIDIA_2_APLIMIT 0xdc
24 #define NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4)
25 #define NVIDIA_3_APBASE 0x50
26 #define NVIDIA_3_APLIMIT 0x54
27
28
29 static int agp_try_unsupported __initdata = 0;
30
31 static struct _nvidia_private {
32 struct pci_dev *dev_1;
33 struct pci_dev *dev_2;
34 struct pci_dev *dev_3;
35 volatile u32 *aperture;
36 int num_active_entries;
37 off_t pg_offset;
38 u32 wbc_mask;
39 } nvidia_private;
40
41
42 static int nvidia_fetch_size(void)
43 {
44 int i;
45 u8 size_value;
46 struct aper_size_info_8 *values;
47
48 pci_read_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE, &size_value);
49 size_value &= 0x0f;
50 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
51
52 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
53 if (size_value == values[i].size_value) {
54 agp_bridge->previous_size =
55 agp_bridge->current_size = (void *) (values + i);
56 agp_bridge->aperture_size_idx = i;
57 return values[i].size;
58 }
59 }
60
61 return 0;
62 }
63
64
65 static int nvidia_configure(void)
66 {
67 int i, num_dirs;
68 u32 apbase, aplimit;
69 struct aper_size_info_8 *current_size;
70 u32 temp;
71
72 current_size = A_SIZE_8(agp_bridge->current_size);
73
74 /* aperture size */
75 pci_write_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE,
76 current_size->size_value);
77
78 /* address to map to */
79 pci_read_config_dword(agp_bridge->dev, NVIDIA_0_APBASE, &apbase);
80 apbase &= PCI_BASE_ADDRESS_MEM_MASK;
81 agp_bridge->gart_bus_addr = apbase;
82 aplimit = apbase + (current_size->size * 1024 * 1024) - 1;
83 pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APBASE, apbase);
84 pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APLIMIT, aplimit);
85 pci_write_config_dword(nvidia_private.dev_3, NVIDIA_3_APBASE, apbase);
86 pci_write_config_dword(nvidia_private.dev_3, NVIDIA_3_APLIMIT, aplimit);
87
88 /* directory size is 64k */
89 num_dirs = current_size->size / 64;
90 nvidia_private.num_active_entries = current_size->num_entries;
91 nvidia_private.pg_offset = 0;
92 if (num_dirs == 0) {
93 num_dirs = 1;
94 nvidia_private.num_active_entries /= (64 / current_size->size);
95 nvidia_private.pg_offset = (apbase & (64 * 1024 * 1024 - 1) &
96 ~(current_size->size * 1024 * 1024 - 1)) / PAGE_SIZE;
97 }
98
99 /* attbase */
100 for(i = 0; i < 8; i++) {
101 pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_ATTBASE(i),
102 (agp_bridge->gatt_bus_addr + (i % num_dirs) * 64 * 1024) | 1);
103 }
104
105 /* gtlb control */
106 pci_read_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, &temp);
107 pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, temp | 0x11);
108
109 /* gart control */
110 pci_read_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, &temp);
111 pci_write_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, temp | 0x100);
112
113 /* map aperture */
114 nvidia_private.aperture =
115 (volatile u32 *) ioremap(apbase, 33 * PAGE_SIZE);
116
117 return 0;
118 }
119
120 static void nvidia_cleanup(void)
121 {
122 struct aper_size_info_8 *previous_size;
123 u32 temp;
124
125 /* gart control */
126 pci_read_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, &temp);
127 pci_write_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, temp & ~(0x100));
128
129 /* gtlb control */
130 pci_read_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, &temp);
131 pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, temp & ~(0x11));
132
133 /* unmap aperture */
134 iounmap((void *) nvidia_private.aperture);
135
136 /* restore previous aperture size */
137 previous_size = A_SIZE_8(agp_bridge->previous_size);
138 pci_write_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE,
139 previous_size->size_value);
140 }
141
142
143 /*
144 * Note we can't use the generic routines, even though they are 99% the same.
145 * Aperture sizes <64M still requires a full 64k GART directory, but
146 * only use the portion of the TLB entries that correspond to the apertures
147 * alignment inside the surrounding 64M block.
148 */
149 extern int agp_memory_reserved;
150
151 static int nvidia_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
152 {
153 int i, j;
154
155 if ((type != 0) || (mem->type != 0))
156 return -EINVAL;
157
158 if ((pg_start + mem->page_count) >
159 (nvidia_private.num_active_entries - agp_memory_reserved/PAGE_SIZE))
160 return -EINVAL;
161
162 for(j = pg_start; j < (pg_start + mem->page_count); j++) {
163 if (!PGE_EMPTY(agp_bridge, agp_bridge->gatt_table[nvidia_private.pg_offset + j]))
164 return -EBUSY;
165 }
166
167 if (mem->is_flushed == FALSE) {
168 global_cache_flush();
169 mem->is_flushed = TRUE;
170 }
171 for (i = 0, j = pg_start; i < mem->page_count; i++, j++)
172 agp_bridge->gatt_table[nvidia_private.pg_offset + j] =
173 agp_bridge->driver->mask_memory(mem->memory[i], mem->type);
174
175 agp_bridge->driver->tlb_flush(mem);
176 return 0;
177 }
178
179
180 static int nvidia_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
181 {
182 int i;
183
184 if ((type != 0) || (mem->type != 0))
185 return -EINVAL;
186
187 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
188 agp_bridge->gatt_table[nvidia_private.pg_offset + i] =
189 (unsigned long) agp_bridge->scratch_page;
190 }
191
192 agp_bridge->driver->tlb_flush(mem);
193 return 0;
194 }
195
196
197 static void nvidia_tlbflush(struct agp_memory *mem)
198 {
199 unsigned long end;
200 u32 wbc_reg, temp;
201 int i;
202
203 /* flush chipset */
204 if (nvidia_private.wbc_mask) {
205 pci_read_config_dword(nvidia_private.dev_1, NVIDIA_1_WBC, &wbc_reg);
206 wbc_reg |= nvidia_private.wbc_mask;
207 pci_write_config_dword(nvidia_private.dev_1, NVIDIA_1_WBC, wbc_reg);
208
209 end = jiffies + 3*HZ;
210 do {
211 pci_read_config_dword(nvidia_private.dev_1,
212 NVIDIA_1_WBC, &wbc_reg);
213 if ((signed)(end - jiffies) <= 0) {
214 printk(KERN_ERR
215 "TLB flush took more than 3 seconds.\n");
216 }
217 } while (wbc_reg & nvidia_private.wbc_mask);
218 }
219
220 /* flush TLB entries */
221 for(i = 0; i < 32 + 1; i++)
222 temp = nvidia_private.aperture[i * PAGE_SIZE / sizeof(u32)];
223 for(i = 0; i < 32 + 1; i++)
224 temp = nvidia_private.aperture[i * PAGE_SIZE / sizeof(u32)];
225 }
226
227
228 static struct aper_size_info_8 nvidia_generic_sizes[5] =
229 {
230 {512, 131072, 7, 0},
231 {256, 65536, 6, 8},
232 {128, 32768, 5, 12},
233 {64, 16384, 4, 14},
234 /* The 32M mode still requires a 64k gatt */
235 {32, 16384, 4, 15}
236 };
237
238
239 static struct gatt_mask nvidia_generic_masks[] =
240 {
241 { .mask = 1, .type = 0}
242 };
243
244
245 struct agp_bridge_driver nvidia_driver = {
246 .owner = THIS_MODULE,
247 .aperture_sizes = nvidia_generic_sizes,
248 .size_type = U8_APER_SIZE,
249 .num_aperture_sizes = 5,
250 .configure = nvidia_configure,
251 .fetch_size = nvidia_fetch_size,
252 .cleanup = nvidia_cleanup,
253 .tlb_flush = nvidia_tlbflush,
254 .mask_memory = agp_generic_mask_memory,
255 .masks = nvidia_generic_masks,
256 .agp_enable = agp_generic_enable,
257 .cache_flush = global_cache_flush,
258 .create_gatt_table = agp_generic_create_gatt_table,
259 .free_gatt_table = agp_generic_free_gatt_table,
260 .insert_memory = nvidia_insert_memory,
261 .remove_memory = nvidia_remove_memory,
262 .alloc_by_type = agp_generic_alloc_by_type,
263 .free_by_type = agp_generic_free_by_type,
264 .agp_alloc_page = agp_generic_alloc_page,
265 .agp_destroy_page = agp_generic_destroy_page,
266 };
267
268 static int __init agp_nvidia_probe(struct pci_dev *pdev,
269 const struct pci_device_id *ent)
270 {
271 struct agp_bridge_data *bridge;
272 u8 cap_ptr;
273
274 nvidia_private.dev_1 =
275 pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 1));
276 nvidia_private.dev_2 =
277 pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 2));
278 nvidia_private.dev_3 =
279 pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(30, 0));
280
281 if (!nvidia_private.dev_1 || !nvidia_private.dev_2 || !nvidia_private.dev_3) {
282 printk(KERN_INFO PFX "agpgart: Detected an NVIDIA "
283 "nForce/nForce2 chipset, but could not find "
284 "the secondary devices.\n");
285 return -ENODEV;
286 }
287
288 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
289 if (!cap_ptr)
290 return -ENODEV;
291
292 switch (pdev->device) {
293 case PCI_DEVICE_ID_NVIDIA_NFORCE:
294 printk(KERN_INFO PFX "Detected NVIDIA nForce chipset\n");
295 nvidia_private.wbc_mask = 0x00010000;
296 break;
297 case PCI_DEVICE_ID_NVIDIA_NFORCE2:
298 printk(KERN_INFO PFX "Detected NVIDIA nForce2 chipset\n");
299 nvidia_private.wbc_mask = 0x80000000;
300 break;
301 default:
302 if (!agp_try_unsupported) {
303 printk(KERN_ERR PFX
304 "Unsupported NVIDIA chipset (device id: %04x),"
305 " you might want to try agp_try_unsupported=1.\n",
306 pdev->device);
307 return -ENODEV;
308 }
309 printk(KERN_WARNING PFX
310 "Trying generic NVIDIA routines for device id: %04x\n",
311 pdev->device);
312 break;
313 }
314
315 bridge = agp_alloc_bridge();
316 if (!bridge)
317 return -ENOMEM;
318
319 bridge->driver = &nvidia_driver;
320 bridge->dev_private_data = &nvidia_private,
321 bridge->dev = pdev;
322 bridge->capndx = cap_ptr;
323
324 /* Fill in the mode register */
325 pci_read_config_dword(pdev,
326 bridge->capndx+PCI_AGP_STATUS,
327 &bridge->mode);
328
329 pci_set_drvdata(pdev, bridge);
330 return agp_add_bridge(bridge);
331 }
332
333 static void __devexit agp_nvidia_remove(struct pci_dev *pdev)
334 {
335 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
336
337 agp_remove_bridge(bridge);
338 agp_put_bridge(bridge);
339 }
340
341 static struct pci_device_id agp_nvidia_pci_table[] __initdata = {
342 {
343 .class = (PCI_CLASS_BRIDGE_HOST << 8),
344 .class_mask = ~0,
345 .vendor = PCI_VENDOR_ID_NVIDIA,
346 .device = PCI_ANY_ID,
347 .subvendor = PCI_ANY_ID,
348 .subdevice = PCI_ANY_ID,
349 },
350 { }
351 };
352
353 MODULE_DEVICE_TABLE(pci, agp_nvidia_pci_table);
354
355 static struct pci_driver agp_nvidia_pci_driver = {
356 .name = "agpgart-nvidia",
357 .id_table = agp_nvidia_pci_table,
358 .probe = agp_nvidia_probe,
359 .remove = agp_nvidia_remove,
360 };
361
362 static int __init agp_nvidia_init(void)
363 {
364 return pci_module_init(&agp_nvidia_pci_driver);
365 }
366
367 static void __exit agp_nvidia_cleanup(void)
368 {
369 pci_unregister_driver(&agp_nvidia_pci_driver);
370 }
371
372 module_init(agp_nvidia_init);
373 module_exit(agp_nvidia_cleanup);
374
375 MODULE_PARM(agp_try_unsupported, "1i");
376 MODULE_LICENSE("GPL and additional rights");
377 MODULE_AUTHOR("NVIDIA Corporation");
378
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