arch/sh/kernel/pci.c

   1 /* arch/sh/kernel/pci.c
   2  * $Id: pci.c,v 1.4 2003/05/25 01:29:24 lethal Exp $
   3  *
   4  * Copyright (c) 2002 M. R. Brown  <mrbrown@linux-sh.org>
   5  *
   6  *
   7  * These functions are collected here to reduce duplication of common
   8  * code amongst the many platform-specific PCI support code files.
   9  *
  10  * These routines require the following board-specific routines:
  11  * void pcibios_fixup();
  12  * void pcibios_fixup_irqs();
  13  *
  14  * See include/asm-sh/pci.h for more information.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/pci.h>
  19 #include <linux/init.h>
  20
  21 static int __init pcibios_init(void)
  22 {
  23         struct pci_channel *p;
  24         struct pci_bus *bus;
  25         int busno;
  26
  27 #ifdef CONFIG_PCI_AUTO
  28         /* assign resources */
  29         busno=0;
  30         for (p = board_pci_channels; p->pci_ops != NULL; p++) {
  31                 busno = pciauto_assign_resources(busno, p) + 1;
  32         }
  33 #endif
  34
  35         /* scan the buses */
  36         busno = 0;
  37         for (p= board_pci_channels; p->pci_ops != NULL; p++) {
  38                 bus = pci_scan_bus(busno, p->pci_ops, p);
  39                 busno = bus->subordinate+1;
  40         }
  41
  42         /* board-specific fixups */
  43         pcibios_fixup();
  44         pcibios_fixup_irqs();
  45
  46         return 0;
  47 }
  48
  49 subsys_initcall(pcibios_init);
  50
  51 void
  52 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
  53                         struct resource *res, int resource)
  54 {
  55         u32 new, check;
  56         int reg;
  57
  58         new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
  59         if (resource < 6) {
  60                 reg = PCI_BASE_ADDRESS_0 + 4*resource;
  61         } else if (resource == PCI_ROM_RESOURCE) {
  62                 res->flags |= PCI_ROM_ADDRESS_ENABLE;
  63                 new |= PCI_ROM_ADDRESS_ENABLE;
  64                 reg = dev->rom_base_reg;
  65         } else {
  66                 /* Somebody might have asked allocation of a non-standard resource */
  67                 return;
  68         }
  69
  70         pci_write_config_dword(dev, reg, new);
  71         pci_read_config_dword(dev, reg, &check);
  72         if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
  73                 printk(KERN_ERR "PCI: Error while updating region "
  74                        "%s/%d (%08x != %08x)\n", dev->slot_name, resource,
  75                        new, check);
  76         }
  77 }
  78
  79 void pcibios_align_resource(void *data, struct resource *res,
  80                             unsigned long size, unsigned long align)
  81                             __attribute__ ((weak));
  82
  83 /*
  84  * We need to avoid collisions with `mirrored' VGA ports
  85  * and other strange ISA hardware, so we always want the
  86  * addresses to be allocated in the 0x000-0x0ff region
  87  * modulo 0x400.
  88  */
  89 void pcibios_align_resource(void *data, struct resource *res,
  90                             unsigned long size, unsigned long align)
  91 {
  92         if (res->flags & IORESOURCE_IO) {
  93                 unsigned long start = res->start;
  94
  95                 if (start & 0x300) {
  96                         start = (start + 0x3ff) & ~0x3ff;
  97                         res->start = start;
  98                 }
  99         }
 100 }
 101
 102 int pcibios_enable_device(struct pci_dev *dev, int mask)
 103 {
 104         u16 cmd, old_cmd;
 105         int idx;
 106         struct resource *r;
 107
 108         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 109         old_cmd = cmd;
 110         for(idx=0; idx<6; idx++) {
 111                 r = &dev->resource[idx];
 112                 if (!r->start && r->end) {
 113                         printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", dev->slot_name);
 114                         return -EINVAL;
 115                 }
 116                 if (r->flags & IORESOURCE_IO)
 117                         cmd |= PCI_COMMAND_IO;
 118                 if (r->flags & IORESOURCE_MEM)
 119                         cmd |= PCI_COMMAND_MEMORY;
 120         }
 121         if (dev->resource[PCI_ROM_RESOURCE].start)
 122                 cmd |= PCI_COMMAND_MEMORY;
 123         if (cmd != old_cmd) {
 124                 printk(KERN_INFO "PCI: Enabling device %s (%04x -> %04x)\n", dev->dev.name, old_cmd, cmd);
 125                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 126         }
 127         return 0;
 128 }
 129
 130 /*
 131  *  If we set up a device for bus mastering, we need to check and set
 132  *  the latency timer as it may not be properly set.
 133  */
 134 unsigned int pcibios_max_latency = 255;
 135
 136 void pcibios_set_master(struct pci_dev *dev)
 137 {
 138         u8 lat;
 139         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 140         if (lat < 16)
 141                 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
 142         else if (lat > pcibios_max_latency)
 143                 lat = pcibios_max_latency;
 144         else
 145                 return;
 146         printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n", dev->dev.name, lat);
 147         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 148 }
 149
 150 void __init pcibios_update_irq(struct pci_dev *dev, int irq)
 151 {
 152         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 153 }