arch/sh/kernel/cpu/sh4/pci-sh7751.c

   1 /*
   2  *      Low-Level PCI Support for the SH7751
   3  *
   4  *  Dustin McIntire (dustin@sensoria.com)
   5  *      Derived from arch/i386/kernel/pci-*.c which bore the message:
   6  *      (c) 1999--2000 Martin Mares <mj@ucw.cz>
   7  *
   8  *  May be copied or modified under the terms of the GNU General Public
   9  *  License.  See linux/COPYING for more information.
  10  *
  11 */
  12
  13 #include <linux/config.h>
  14 #include <linux/types.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/pci.h>
  18 #include <linux/sched.h>
  19 #include <linux/ioport.h>
  20 #include <linux/errno.h>
  21 #include <linux/irq.h>
  22
  23 #include <asm/machvec.h>
  24 #include <asm/io.h>
  25 #include <asm/pci-sh7751.h>
  26
  27 struct pci_ops *pci_check_direct(void);
  28 void pcibios_resource_survey(void);
  29 static u8 pcibios_swizzle(struct pci_dev *dev, u8 *pin);
  30 static int pcibios_lookup_irq(struct pci_dev *dev, u8 slot, u8 pin);
  31
  32 unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1;
  33 int pcibios_last_bus = -1;
  34 struct pci_bus *pci_root_bus;
  35 struct pci_ops *pci_root_ops;
  36
  37 /*
  38  * Direct access to PCI hardware...
  39  */
  40
  41 #ifdef CONFIG_PCI_DIRECT
  42
  43
  44 #define CONFIG_CMD(bus, devfn, where) (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
  45
  46 #define PCI_REG(reg) (SH7751_PCIREG_BASE+reg)
  47
  48 /*
  49  * Functions for accessing PCI configuration space with type 1 accesses
  50  */
  51 static int pci_conf1_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
  52 {
  53         unsigned long flags;
  54         u32 word;
  55
  56         /*
  57          * PCIPDR may only be accessed as 32 bit words,
  58          * so we must do byte alignment by hand
  59          */
  60         local_irq_save(flags);
  61         outl(CONFIG_CMD(bus,devfn,where), PCI_REG(SH7751_PCIPAR));
  62         word = inl(PCI_REG(SH7751_PCIPDR));
  63         local_irq_restore(flags);
  64
  65         switch (size) {
  66         case 1:
  67                 switch (where & 0x3) {
  68                         case 3: *value = (u8)(word >> 24); break;
  69                         case 2: *value = (u8)(word >> 16); break;
  70                         case 1: *value = (u8)(word >> 8);  break;
  71                 }
  72                 break;
  73         case 2:
  74                 switch (where & 0x2) {
  75                         case 2: *value = (u16)(word >> 16); break;
  76                         case 1: *value = (u16)(word >> 8);  break;
  77                 }
  78                 break;
  79         case 4:
  80                 *value = word;
  81                 break;
  82         }
  83
  84         PCIDBG(4,"pci_conf1_read@0x%08x=0x%x\n", CONFIG_CMD(bus,devfn,where),*value);
  85
  86         return PCIBIOS_SUCCESSFUL;
  87 }
  88
  89 /*
  90  * Since SH7751 only does 32bit access we'll have to do a read,mask,write operation.
  91  * We'll allow an odd byte offset, though it should be illegal.
  92  */
  93 static int pci_conf1_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
  94 {
  95         u32 word,mask;
  96         unsigned long flags;
  97         u32 shift = (where & 3) * 8;
  98
  99         if(size == 1) {
 100                 mask = ((1 << 8) - 1) << shift;  // create the byte mask
 101         } else if(size == 2){
 102                 if(shift == 24)
 103                         return PCIBIOS_BAD_REGISTER_NUMBER;
 104                 mask = ((1 << 16) - 1) << shift;  // create the word mask
 105         }
 106
 107         local_irq_save(flags);
 108         outl(CONFIG_CMD(bus,devfn,where), PCI_REG(SH7751_PCIPAR));
 109
 110         if(size == 4){
 111                 outl(value, PCI_REG(SH7751_PCIPDR));
 112                 local_irq_restore(flags);
 113
 114                 PCIDBG(4,"pci_conf1_write@0x%08x=0x%x\n", CONFIG_CMD(bus,devfn,where),value);
 115
 116                 return PCIBIOS_SUCCESSFUL;
 117         }
 118
 119         word = inl(PCI_REG(SH7751_PCIPDR)) ;
 120         word &= ~mask;
 121         word |= value << shift;
 122         outl(word, PCI_REG(SH7751_PCIPDR));
 123         local_irq_restore(flags);
 124
 125         PCIDBG(4,"pci_conf1_write@0x%08x=0x%x\n", CONFIG_CMD(bus,devfn,where),word);
 126
 127         return PCIBIOS_SUCCESSFUL;
 128 }
 129
 130 #undef CONFIG_CMD
 131
 132 static struct pci_ops pci_direct_conf1 = {
 133         .read =         pci_conf1_read,
 134         .write =        pci_conf1_write,
 135 };
 136
 137 struct pci_ops * __init pci_check_direct(void)
 138 {
 139         unsigned int tmp, id;
 140
 141         /* check for SH7751 hardware */
 142         id = (SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID;
 143         if(inl(SH7751_PCIREG_BASE+SH7751_PCICONF0) != id) {
 144                 PCIDBG(2,"PCI: This is not an SH7751\n");
 145                 return NULL;
 146         }
 147         /*
 148          * Check if configuration works.
 149          */
 150         if (pci_probe & PCI_PROBE_CONF1) {
 151                 tmp = inl (PCI_REG(SH7751_PCIPAR));
 152                 outl (0x80000000, PCI_REG(SH7751_PCIPAR));
 153                 if (inl (PCI_REG(SH7751_PCIPAR)) == 0x80000000) {
 154                         outl (tmp, PCI_REG(SH7751_PCIPAR));
 155                         printk(KERN_INFO "PCI: Using configuration type 1\n");
 156                         request_region(PCI_REG(SH7751_PCIPAR), 8, "PCI conf1");
 157                         return &pci_direct_conf1;
 158                 }
 159                 outl (tmp, PCI_REG(SH7751_PCIPAR));
 160         }
 161
 162         PCIDBG(2,"PCI: pci_check_direct failed\n");
 163         return NULL;
 164 }
 165
 166 #endif
 167
 168 /*
 169  * BIOS32 and PCI BIOS handling.
 170  *
 171  * The BIOS version of the pci functions is not yet implemented but it is left
 172  * in for completeness.  Currently an error will be generated at compile time.
 173  */
 174
 175 #ifdef CONFIG_PCI_BIOS
 176
 177 #error PCI BIOS is not yet supported on SH7751
 178
 179 #endif /* CONFIG_PCI_BIOS */
 180
 181 /***************************************************************************************/
 182
 183 /*
 184  *  Handle bus scanning and fixups ....
 185  */
 186
 187
 188 /*
 189  * Discover remaining PCI buses in case there are peer host bridges.
 190  * We use the number of last PCI bus provided by the PCI BIOS.
 191  */
 192 static void __init pcibios_fixup_peer_bridges(void)
 193 {
 194         int n;
 195         struct pci_bus bus;
 196         struct pci_dev dev;
 197         u16 l;
 198
 199         if (pcibios_last_bus <= 0 || pcibios_last_bus >= 0xff)
 200                 return;
 201         PCIDBG(2,"PCI: Peer bridge fixup\n");
 202         for (n=0; n <= pcibios_last_bus; n++) {
 203                 if (pci_bus_exists(&pci_root_buses, n))
 204                         continue;
 205                 bus.number = n;
 206                 bus.ops = pci_root_ops;
 207                 dev.bus = &bus;
 208                 for(dev.devfn=0; dev.devfn<256; dev.devfn += 8)
 209                         if (!pci_read_config_word(&dev, PCI_VENDOR_ID, &l) &&
 210                             l != 0x0000 && l != 0xffff) {
 211                                 PCIDBG(3,"Found device at %02x:%02x [%04x]\n", n, dev.devfn, l);
 212                                 printk(KERN_INFO "PCI: Discovered peer bus %02x\n", n);
 213                                 pci_scan_bus(n, pci_root_ops, NULL);
 214                                 break;
 215                         }
 216         }
 217 }
 218
 219
 220 static void __init pci_fixup_ide_bases(struct pci_dev *d)
 221 {
 222         int i;
 223
 224         /*
 225          * PCI IDE controllers use non-standard I/O port decoding, respect it.
 226          */
 227         if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
 228                 return;
 229         PCIDBG(3,"PCI: IDE base address fixup for %s\n", d->slot_name);
 230         for(i=0; i<4; i++) {
 231                 struct resource *r = &d->resource[i];
 232                 if ((r->start & ~0x80) == 0x374) {
 233                         r->start |= 2;
 234                         r->end = r->start;
 235                 }
 236         }
 237 }
 238
 239
 240 /* Add future fixups here... */
 241 struct pci_fixup pcibios_fixups[] = {
 242         { PCI_FIXUP_HEADER,     PCI_ANY_ID,     PCI_ANY_ID,     pci_fixup_ide_bases },
 243         { 0 }
 244 };
 245
 246 /*
 247  *  Called after each bus is probed, but before its children
 248  *  are examined.
 249  */
 250
 251 void __init pcibios_fixup_bus(struct pci_bus *b)
 252 {
 253         pci_read_bridge_bases(b);
 254 }
 255
 256 /*
 257  * Initialization. Try all known PCI access methods. Note that we support
 258  * using both PCI BIOS and direct access: in such cases, we use I/O ports
 259  * to access config space.
 260  *
 261  * Note that the platform specific initialization (BSC registers, and memory
 262  * space mapping) will be called via the machine vectors (sh_mv.mv_pci_init()) if it
 263  * exitst and via the platform defined function pcibios_init_platform().
 264  * See pci_bigsur.c for implementation;
 265  *
 266  * The BIOS version of the pci functions is not yet implemented but it is left
 267  * in for completeness.  Currently an error will be genereated at compile time.
 268  */
 269
 270 void __init pcibios_init(void)
 271 {
 272         struct pci_ops *bios = NULL;
 273         struct pci_ops *dir = NULL;
 274
 275         PCIDBG(1,"PCI: Starting intialization.\n");
 276 #ifdef CONFIG_PCI_BIOS
 277         if ((pci_probe & PCI_PROBE_BIOS) && ((bios = pci_find_bios()))) {
 278                 pci_probe |= PCI_BIOS_SORT;
 279                 pci_bios_present = 1;
 280         }
 281 #endif
 282 #ifdef CONFIG_PCI_DIRECT
 283         if (pci_probe & PCI_PROBE_CONF1 )
 284                 dir = pci_check_direct();
 285 #endif
 286         if (dir) {
 287                 pci_root_ops = dir;
 288             if(!pcibios_init_platform())
 289                         PCIDBG(1,"PCI: Initialization failed\n");
 290             if (sh_mv.mv_init_pci != NULL)
 291             sh_mv.mv_init_pci();
 292         }
 293         else if (bios)
 294                 pci_root_ops = bios;
 295         else {
 296                 PCIDBG(1,"PCI: No PCI bus detected\n");
 297                 return;
 298         }
 299
 300         PCIDBG(1,"PCI: Probing PCI hardware\n");
 301         pci_root_bus = pci_scan_bus(0, pci_root_ops, NULL);
 302         //pci_assign_unassigned_resources();
 303         pci_fixup_irqs(pcibios_swizzle, pcibios_lookup_irq);
 304         pcibios_fixup_peer_bridges();
 305         pcibios_resource_survey();
 306
 307 #ifdef CONFIG_PCI_BIOS
 308         if ((pci_probe & PCI_BIOS_SORT) && !(pci_probe & PCI_NO_SORT))
 309                 pcibios_sort();
 310 #endif
 311 }
 312
 313 char * __init pcibios_setup(char *str)
 314 {
 315         if (!strcmp(str, "off")) {
 316                 pci_probe = 0;
 317                 return NULL;
 318         }
 319 #ifdef CONFIG_PCI_BIOS
 320         else if (!strcmp(str, "bios")) {
 321                 pci_probe = PCI_PROBE_BIOS;
 322                 return NULL;
 323         } else if (!strcmp(str, "nobios")) {
 324                 pci_probe &= ~PCI_PROBE_BIOS;
 325                 return NULL;
 326         } else if (!strcmp(str, "nosort")) {
 327                 pci_probe |= PCI_NO_SORT;
 328                 return NULL;
 329         } else if (!strcmp(str, "biosirq")) {
 330                 pci_probe |= PCI_BIOS_IRQ_SCAN;
 331                 return NULL;
 332         }
 333 #endif
 334 #ifdef CONFIG_PCI_DIRECT
 335         else if (!strcmp(str, "conf1")) {
 336                 pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS;
 337                 return NULL;
 338         }
 339 #endif
 340         else if (!strcmp(str, "rom")) {
 341                 pci_probe |= PCI_ASSIGN_ROMS;
 342                 return NULL;
 343         } else if (!strncmp(str, "lastbus=", 8)) {
 344                 pcibios_last_bus = simple_strtol(str+8, NULL, 0);
 345                 return NULL;
 346         }
 347         return str;
 348 }
 349
 350 /*
 351  *    Allocate the bridge and device resources
 352  */
 353
 354 static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
 355 {
 356         struct list_head *ln;
 357         struct pci_bus *bus;
 358         struct pci_dev *dev;
 359         int idx;
 360         struct resource *r, *pr;
 361
 362         PCIDBG(2,"PCI: pcibios_allocate_bus_reasources called\n" );
 363         /* Depth-First Search on bus tree */
 364         for (ln=bus_list->next; ln != bus_list; ln=ln->next) {
 365                 bus = pci_bus_b(ln);
 366                 if ((dev = bus->self)) {
 367                         for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
 368                                 r = &dev->resource[idx];
 369                                 if (!r->start)
 370                                         continue;
 371                                 pr = pci_find_parent_resource(dev, r);
 372                                 if (!pr || request_resource(pr, r) < 0)
 373                                         printk(KERN_ERR "PCI: Cannot allocate resource region %d of bridge %s\n", idx, dev->slot_name);
 374                         }
 375                 }
 376                 pcibios_allocate_bus_resources(&bus->children);
 377         }
 378 }
 379
 380 static void __init pcibios_allocate_resources(int pass)
 381 {
 382         struct pci_dev *dev;
 383         int idx, disabled;
 384         u16 command;
 385         struct resource *r, *pr;
 386
 387         PCIDBG(2,"PCI: pcibios_allocate_resources pass %d called\n", pass);
 388         pci_for_each_dev(dev) {
 389                 pci_read_config_word(dev, PCI_COMMAND, &command);
 390                 for(idx = 0; idx < 6; idx++) {
 391                         r = &dev->resource[idx];
 392                         if (r->parent)          /* Already allocated */
 393                                 continue;
 394                         if (!r->start)          /* Address not assigned at all */
 395                                 continue;
 396                         if (r->flags & IORESOURCE_IO)
 397                                 disabled = !(command & PCI_COMMAND_IO);
 398                         else
 399                                 disabled = !(command & PCI_COMMAND_MEMORY);
 400                         if (pass == disabled) {
 401                                 PCIDBG(3,"PCI: Resource %08lx-%08lx (f=%lx, d=%d, p=%d)\n",
 402                                     r->start, r->end, r->flags, disabled, pass);
 403                                 pr = pci_find_parent_resource(dev, r);
 404                                 if (!pr || request_resource(pr, r) < 0) {
 405                                         printk(KERN_ERR "PCI: Cannot allocate resource region %d of device %s\n", idx, dev->slot_name);
 406                                         /* We'll assign a new address later */
 407                                         r->end -= r->start;
 408                                         r->start = 0;
 409                                 }
 410                         }
 411                 }
 412                 if (!pass) {
 413                         r = &dev->resource[PCI_ROM_RESOURCE];
 414                         if (r->flags & PCI_ROM_ADDRESS_ENABLE) {
 415                                 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
 416                                 u32 reg;
 417                                 PCIDBG(3,"PCI: Switching off ROM of %s\n", dev->slot_name);
 418                                 r->flags &= ~PCI_ROM_ADDRESS_ENABLE;
 419                                 pci_read_config_dword(dev, dev->rom_base_reg, &reg);
 420                                 pci_write_config_dword(dev, dev->rom_base_reg, reg & ~PCI_ROM_ADDRESS_ENABLE);
 421                         }
 422                 }
 423         }
 424 }
 425
 426 static void __init pcibios_assign_resources(void)
 427 {
 428         struct pci_dev *dev;
 429         int idx;
 430         struct resource *r;
 431
 432         PCIDBG(2,"PCI: pcibios_assign_resources called\n");
 433         pci_for_each_dev(dev) {
 434                 int class = dev->class >> 8;
 435
 436                 /* Don't touch classless devices and host bridges */
 437                 if (!class || class == PCI_CLASS_BRIDGE_HOST)
 438                         continue;
 439
 440                 for(idx=0; idx<6; idx++) {
 441                         r = &dev->resource[idx];
 442
 443                         /*
 444                          *  Don't touch IDE controllers and I/O ports of video cards!
 445                          */
 446                         if ((class == PCI_CLASS_STORAGE_IDE && idx < 4) ||
 447                             (class == PCI_CLASS_DISPLAY_VGA && (r->flags & IORESOURCE_IO)))
 448                                 continue;
 449
 450                         /*
 451                          *  We shall assign a new address to this resource, either because
 452                          *  the BIOS forgot to do so or because we have decided the old
 453                          *  address was unusable for some reason.
 454                          */
 455                         if (!r->start && r->end)
 456                                 pci_assign_resource(dev, idx);
 457                 }
 458
 459                 if (pci_probe & PCI_ASSIGN_ROMS) {
 460                         r = &dev->resource[PCI_ROM_RESOURCE];
 461                         r->end -= r->start;
 462                         r->start = 0;
 463                         if (r->end)
 464                                 pci_assign_resource(dev, PCI_ROM_RESOURCE);
 465                 }
 466         }
 467 }
 468
 469 void __init pcibios_resource_survey(void)
 470 {
 471         PCIDBG(1,"PCI: Allocating resources\n");
 472         pcibios_allocate_bus_resources(&pci_root_buses);
 473         pcibios_allocate_resources(0);
 474         pcibios_allocate_resources(1);
 475         pcibios_assign_resources();
 476 }
 477
 478
 479 /***************************************************************************************/
 480 /*
 481  *      IRQ functions
 482  */
 483 static u8 __init pcibios_swizzle(struct pci_dev *dev, u8 *pin)
 484 {
 485         /* no swizzling */
 486         return PCI_SLOT(dev->devfn);
 487 }
 488
 489 static int pcibios_lookup_irq(struct pci_dev *dev, u8 slot, u8 pin)
 490 {
 491         int irq = -1;
 492
 493         /* now lookup the actual IRQ on a platform specific basis (pci-'platform'.c) */
 494         irq = pcibios_map_platform_irq(slot,pin);
 495         if( irq < 0 ) {
 496             PCIDBG(3,"PCI: Error mapping IRQ on device %s\n", dev->name);
 497                 return irq;
 498         }
 499
 500         PCIDBG(2,"Setting IRQ for slot %s to %d\n", dev->slot_name, irq);
 501
 502         return irq;
 503 }