1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
5 This file is part of GDB, GAS, and the GNU binutils.
7 GDB, GAS, and the GNU binutils are free software; you can redistribute
8 them and/or modify them under the terms of the GNU General Public
9 License as published by the Free Software Foundation; either version
10 2, or (at your option) any later version.
12 GDB, GAS, and the GNU binutils are distributed in the hope that they
13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21 #include <linux/posix_types.h>
25 /* This file holds the PowerPC opcode table. The opcode table
26 includes almost all of the extended instruction mnemonics. This
27 permits the disassembler to use them, and simplifies the assembler
28 logic, at the cost of increasing the table size. The table is
29 strictly constant data, so the compiler should be able to put it in
32 This file also holds the operand table. All knowledge about
33 inserting operands into instructions and vice-versa is kept in this
36 /* Local insertion and extraction functions. */
38 static unsigned long insert_bat
PARAMS ((unsigned long, long, const char **));
39 static long extract_bat
PARAMS ((unsigned long, int *));
40 static unsigned long insert_bba
PARAMS ((unsigned long, long, const char **));
41 static long extract_bba
PARAMS ((unsigned long, int *));
42 static unsigned long insert_bd
PARAMS ((unsigned long, long, const char **));
43 static long extract_bd
PARAMS ((unsigned long, int *));
44 static unsigned long insert_bdm
PARAMS ((unsigned long, long, const char **));
45 static long extract_bdm
PARAMS ((unsigned long, int *));
46 static unsigned long insert_bdp
PARAMS ((unsigned long, long, const char **));
47 static long extract_bdp
PARAMS ((unsigned long, int *));
48 static unsigned long insert_bo
PARAMS ((unsigned long, long, const char **));
49 static long extract_bo
PARAMS ((unsigned long, int *));
50 static unsigned long insert_boe
PARAMS ((unsigned long, long, const char **));
51 static long extract_boe
PARAMS ((unsigned long, int *));
52 static unsigned long insert_ds
PARAMS ((unsigned long, long, const char **));
53 static long extract_ds
PARAMS ((unsigned long, int *));
54 static unsigned long insert_li
PARAMS ((unsigned long, long, const char **));
55 static long extract_li
PARAMS ((unsigned long, int *));
56 static unsigned long insert_mbe
PARAMS ((unsigned long, long, const char **));
57 static long extract_mbe
PARAMS ((unsigned long, int *));
58 static unsigned long insert_mb6
PARAMS ((unsigned long, long, const char **));
59 static long extract_mb6
PARAMS ((unsigned long, int *));
60 static unsigned long insert_nb
PARAMS ((unsigned long, long, const char **));
61 static long extract_nb
PARAMS ((unsigned long, int *));
62 static unsigned long insert_nsi
PARAMS ((unsigned long, long, const char **));
63 static long extract_nsi
PARAMS ((unsigned long, int *));
64 static unsigned long insert_ral
PARAMS ((unsigned long, long, const char **));
65 static unsigned long insert_ram
PARAMS ((unsigned long, long, const char **));
66 static unsigned long insert_ras
PARAMS ((unsigned long, long, const char **));
67 static unsigned long insert_rbs
PARAMS ((unsigned long, long, const char **));
68 static long extract_rbs
PARAMS ((unsigned long, int *));
69 static unsigned long insert_sh6
PARAMS ((unsigned long, long, const char **));
70 static long extract_sh6
PARAMS ((unsigned long, int *));
71 static unsigned long insert_spr
PARAMS ((unsigned long, long, const char **));
72 static long extract_spr
PARAMS ((unsigned long, int *));
73 static unsigned long insert_tbr
PARAMS ((unsigned long, long, const char **));
74 static long extract_tbr
PARAMS ((unsigned long, int *));
76 /* The operands table.
78 The fields are bits, shift, signed, insert, extract, flags. */
80 const struct powerpc_operand powerpc_operands
[] =
82 /* The zero index is used to indicate the end of the list of
87 /* The BA field in an XL form instruction. */
89 #define BA_MASK (0x1f << 16)
90 { 5, 16, 0, 0, PPC_OPERAND_CR
},
92 /* The BA field in an XL form instruction when it must be the same
93 as the BT field in the same instruction. */
95 { 5, 16, insert_bat
, extract_bat
, PPC_OPERAND_FAKE
},
97 /* The BB field in an XL form instruction. */
99 #define BB_MASK (0x1f << 11)
100 { 5, 11, 0, 0, PPC_OPERAND_CR
},
102 /* The BB field in an XL form instruction when it must be the same
103 as the BA field in the same instruction. */
105 { 5, 11, insert_bba
, extract_bba
, PPC_OPERAND_FAKE
},
107 /* The BD field in a B form instruction. The lower two bits are
110 { 16, 0, insert_bd
, extract_bd
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
112 /* The BD field in a B form instruction when absolute addressing is
115 { 16, 0, insert_bd
, extract_bd
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
117 /* The BD field in a B form instruction when the - modifier is used.
118 This sets the y bit of the BO field appropriately. */
120 { 16, 0, insert_bdm
, extract_bdm
,
121 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
123 /* The BD field in a B form instruction when the - modifier is used
124 and absolute address is used. */
126 { 16, 0, insert_bdm
, extract_bdm
,
127 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
129 /* The BD field in a B form instruction when the + modifier is used.
130 This sets the y bit of the BO field appropriately. */
132 { 16, 0, insert_bdp
, extract_bdp
,
133 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
135 /* The BD field in a B form instruction when the + modifier is used
136 and absolute addressing is used. */
138 { 16, 0, insert_bdp
, extract_bdp
,
139 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
141 /* The BF field in an X or XL form instruction. */
143 { 3, 23, 0, 0, PPC_OPERAND_CR
},
145 /* An optional BF field. This is used for comparison instructions,
146 in which an omitted BF field is taken as zero. */
148 { 3, 23, 0, 0, PPC_OPERAND_CR
| PPC_OPERAND_OPTIONAL
},
150 /* The BFA field in an X or XL form instruction. */
152 { 3, 18, 0, 0, PPC_OPERAND_CR
},
154 /* The BI field in a B form or XL form instruction. */
156 #define BI_MASK (0x1f << 16)
157 { 5, 16, 0, 0, PPC_OPERAND_CR
},
159 /* The BO field in a B form instruction. Certain values are
162 #define BO_MASK (0x1f << 21)
163 { 5, 21, insert_bo
, extract_bo
, 0 },
165 /* The BO field in a B form instruction when the + or - modifier is
166 used. This is like the BO field, but it must be even. */
168 { 5, 21, insert_boe
, extract_boe
, 0 },
170 /* The BT field in an X or XL form instruction. */
172 { 5, 21, 0, 0, PPC_OPERAND_CR
},
174 /* The condition register number portion of the BI field in a B form
175 or XL form instruction. This is used for the extended
176 conditional branch mnemonics, which set the lower two bits of the
177 BI field. This field is optional. */
179 { 3, 18, 0, 0, PPC_OPERAND_CR
| PPC_OPERAND_OPTIONAL
},
181 /* The D field in a D form instruction. This is a displacement off
182 a register, and implies that the next operand is a register in
185 { 16, 0, 0, 0, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
187 /* The DS field in a DS form instruction. This is like D, but the
188 lower two bits are forced to zero. */
190 { 16, 0, insert_ds
, extract_ds
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
192 /* The FL1 field in a POWER SC form instruction. */
196 /* The FL2 field in a POWER SC form instruction. */
200 /* The FLM field in an XFL form instruction. */
204 /* The FRA field in an X or A form instruction. */
206 #define FRA_MASK (0x1f << 16)
207 { 5, 16, 0, 0, PPC_OPERAND_FPR
},
209 /* The FRB field in an X or A form instruction. */
211 #define FRB_MASK (0x1f << 11)
212 { 5, 11, 0, 0, PPC_OPERAND_FPR
},
214 /* The FRC field in an A form instruction. */
216 #define FRC_MASK (0x1f << 6)
217 { 5, 6, 0, 0, PPC_OPERAND_FPR
},
219 /* The FRS field in an X form instruction or the FRT field in a D, X
220 or A form instruction. */
223 { 5, 21, 0, 0, PPC_OPERAND_FPR
},
225 /* The FXM field in an XFX instruction. */
227 #define FXM_MASK (0xff << 12)
230 /* The L field in a D or X form instruction. */
232 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL
},
234 /* The LEV field in a POWER SC form instruction. */
238 /* The LI field in an I form instruction. The lower two bits are
241 { 26, 0, insert_li
, extract_li
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
243 /* The LI field in an I form instruction when used as an absolute
246 { 26, 0, insert_li
, extract_li
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
248 /* The MB field in an M form instruction. */
250 #define MB_MASK (0x1f << 6)
253 /* The ME field in an M form instruction. */
255 #define ME_MASK (0x1f << 1)
258 /* The MB and ME fields in an M form instruction expressed a single
259 operand which is a bitmask indicating which bits to select. This
260 is a two operand form using PPC_OPERAND_NEXT. See the
261 description in opcode/ppc.h for what this means. */
263 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_NEXT
},
264 { 32, 0, insert_mbe
, extract_mbe
, 0 },
266 /* The MB or ME field in an MD or MDS form instruction. The high
267 bit is wrapped to the low end. */
270 #define MB6_MASK (0x3f << 5)
271 { 6, 5, insert_mb6
, extract_mb6
, 0 },
273 /* The NB field in an X form instruction. The value 32 is stored as
276 { 6, 11, insert_nb
, extract_nb
, 0 },
278 /* The NSI field in a D form instruction. This is the same as the
279 SI field, only negated. */
281 { 16, 0, insert_nsi
, extract_nsi
,
282 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
284 /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
286 #define RA_MASK (0x1f << 16)
287 { 5, 16, 0, 0, PPC_OPERAND_GPR
},
289 /* The RA field in a D or X form instruction which is an updating
290 load, which means that the RA field may not be zero and may not
291 equal the RT field. */
293 { 5, 16, insert_ral
, 0, PPC_OPERAND_GPR
},
295 /* The RA field in an lmw instruction, which has special value
298 { 5, 16, insert_ram
, 0, PPC_OPERAND_GPR
},
300 /* The RA field in a D or X form instruction which is an updating
301 store or an updating floating point load, which means that the RA
302 field may not be zero. */
304 { 5, 16, insert_ras
, 0, PPC_OPERAND_GPR
},
306 /* The RB field in an X, XO, M, or MDS form instruction. */
308 #define RB_MASK (0x1f << 11)
309 { 5, 11, 0, 0, PPC_OPERAND_GPR
},
311 /* The RB field in an X form instruction when it must be the same as
312 the RS field in the instruction. This is used for extended
313 mnemonics like mr. */
315 { 5, 1, insert_rbs
, extract_rbs
, PPC_OPERAND_FAKE
},
317 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
318 instruction or the RT field in a D, DS, X, XFX or XO form
322 #define RT_MASK (0x1f << 21)
323 { 5, 21, 0, 0, PPC_OPERAND_GPR
},
325 /* The SH field in an X or M form instruction. */
327 #define SH_MASK (0x1f << 11)
330 /* The SH field in an MD form instruction. This is split. */
332 #define SH6_MASK ((0x1f << 11) | (1 << 1))
333 { 6, 1, insert_sh6
, extract_sh6
, 0 },
335 /* The SI field in a D form instruction. */
337 { 16, 0, 0, 0, PPC_OPERAND_SIGNED
},
339 /* The SI field in a D form instruction when we accept a wide range
340 of positive values. */
341 #define SISIGNOPT (50)
342 { 16, 0, 0, 0, PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
344 /* The SPR field in an XFX form instruction. This is flipped--the
345 lower 5 bits are stored in the upper 5 and vice- versa. */
347 #define SPR_MASK (0x3ff << 11)
348 { 10, 11, insert_spr
, extract_spr
, 0 },
350 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
352 #define SPRBAT_MASK (0x3 << 17)
355 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
357 #define SPRG_MASK (0x3 << 16)
360 /* The SR field in an X form instruction. */
364 /* The SV field in a POWER SC form instruction. */
368 /* The TBR field in an XFX form instruction. This is like the SPR
369 field, but it is optional. */
371 { 10, 11, insert_tbr
, extract_tbr
, PPC_OPERAND_OPTIONAL
},
373 /* The TO field in a D or X form instruction. */
375 #define TO_MASK (0x1f << 21)
378 /* The U field in an X form instruction. */
382 /* The UI field in a D form instruction. */
387 /* The functions used to insert and extract complicated operands. */
389 /* The BA field in an XL form instruction when it must be the same as
390 the BT field in the same instruction. This operand is marked FAKE.
391 The insertion function just copies the BT field into the BA field,
392 and the extraction function just checks that the fields are the
397 insert_bat(unsigned long insn
, long value
, const char **errmsg
)
399 return insn
| (((insn
>> 21) & 0x1f) << 16);
403 extract_bat(unsigned long insn
, int *invalid
)
405 if (invalid
!= (int *) NULL
406 && ((insn
>> 21) & 0x1f) != ((insn
>> 16) & 0x1f))
411 /* The BB field in an XL form instruction when it must be the same as
412 the BA field in the same instruction. This operand is marked FAKE.
413 The insertion function just copies the BA field into the BB field,
414 and the extraction function just checks that the fields are the
419 insert_bba(unsigned long insn
, long value
, const char **errmsg
)
421 return insn
| (((insn
>> 16) & 0x1f) << 11);
425 extract_bba(unsigned long insn
, int *invalid
)
427 if (invalid
!= (int *) NULL
428 && ((insn
>> 16) & 0x1f) != ((insn
>> 11) & 0x1f))
433 /* The BD field in a B form instruction. The lower two bits are
438 insert_bd(unsigned long insn
, long value
, const char **errmsg
)
440 return insn
| (value
& 0xfffc);
445 extract_bd(unsigned long insn
, int *invalid
)
447 if ((insn
& 0x8000) != 0)
448 return (insn
& 0xfffc) - 0x10000;
450 return insn
& 0xfffc;
453 /* The BD field in a B form instruction when the - modifier is used.
454 This modifier means that the branch is not expected to be taken.
455 We must set the y bit of the BO field to 1 if the offset is
456 negative. When extracting, we require that the y bit be 1 and that
457 the offset be positive, since if the y bit is 0 we just want to
458 print the normal form of the instruction. */
462 insert_bdm(unsigned long insn
, long value
, const char **errmsg
)
464 if ((value
& 0x8000) != 0)
466 return insn
| (value
& 0xfffc);
470 extract_bdm(unsigned long insn
, int *invalid
)
472 if (invalid
!= (int *) NULL
473 && ((insn
& (1 << 21)) == 0
474 || (insn
& (1 << 15)) == 0))
476 if ((insn
& 0x8000) != 0)
477 return (insn
& 0xfffc) - 0x10000;
479 return insn
& 0xfffc;
482 /* The BD field in a B form instruction when the + modifier is used.
483 This is like BDM, above, except that the branch is expected to be
488 insert_bdp(unsigned long insn
, long value
, const char **errmsg
)
490 if ((value
& 0x8000) == 0)
492 return insn
| (value
& 0xfffc);
496 extract_bdp(unsigned long insn
, int *invalid
)
498 if (invalid
!= (int *) NULL
499 && ((insn
& (1 << 21)) == 0
500 || (insn
& (1 << 15)) != 0))
502 if ((insn
& 0x8000) != 0)
503 return (insn
& 0xfffc) - 0x10000;
505 return insn
& 0xfffc;
508 /* Check for legal values of a BO field. */
511 valid_bo (long value
)
513 /* Certain encodings have bits that are required to be zero. These
514 are (z must be zero, y may be anything):
521 switch (value
& 0x14)
527 return (value
& 0x2) == 0;
529 return (value
& 0x8) == 0;
531 return value
== 0x14;
535 /* The BO field in a B form instruction. Warn about attempts to set
536 the field to an illegal value. */
539 insert_bo(unsigned long insn
, long value
, const char **errmsg
)
541 if (errmsg
!= (const char **) NULL
542 && ! valid_bo (value
))
543 *errmsg
= "invalid conditional option";
544 return insn
| ((value
& 0x1f) << 21);
548 extract_bo(unsigned long insn
, int *invalid
)
552 value
= (insn
>> 21) & 0x1f;
553 if (invalid
!= (int *) NULL
554 && ! valid_bo (value
))
559 /* The BO field in a B form instruction when the + or - modifier is
560 used. This is like the BO field, but it must be even. When
561 extracting it, we force it to be even. */
564 insert_boe(unsigned long insn
, long value
, const char **errmsg
)
566 if (errmsg
!= (const char **) NULL
)
568 if (! valid_bo (value
))
569 *errmsg
= "invalid conditional option";
570 else if ((value
& 1) != 0)
571 *errmsg
= "attempt to set y bit when using + or - modifier";
573 return insn
| ((value
& 0x1f) << 21);
577 extract_boe(unsigned long insn
, int *invalid
)
581 value
= (insn
>> 21) & 0x1f;
582 if (invalid
!= (int *) NULL
583 && ! valid_bo (value
))
588 /* The DS field in a DS form instruction. This is like D, but the
589 lower two bits are forced to zero. */
593 insert_ds(unsigned long insn
, long value
, const char **errmsg
)
595 return insn
| (value
& 0xfffc);
600 extract_ds(unsigned long insn
, int *invalid
)
602 if ((insn
& 0x8000) != 0)
603 return (insn
& 0xfffc) - 0x10000;
605 return insn
& 0xfffc;
608 /* The LI field in an I form instruction. The lower two bits are
613 insert_li(unsigned long insn
, long value
, const char **errmsg
)
615 return insn
| (value
& 0x3fffffc);
620 extract_li(unsigned long insn
, int *invalid
)
622 if ((insn
& 0x2000000) != 0)
623 return (insn
& 0x3fffffc) - 0x4000000;
625 return insn
& 0x3fffffc;
628 /* The MB and ME fields in an M form instruction expressed as a single
629 operand which is itself a bitmask. The extraction function always
630 marks it as invalid, since we never want to recognize an
631 instruction which uses a field of this type. */
634 insert_mbe(unsigned long insn
, long value
, const char **errmsg
)
643 if (errmsg
!= (const char **) NULL
)
644 *errmsg
= "illegal bitmask";
649 while ((uval
& 1) == 0)
657 while ((uval
& 1) != 0)
665 if (errmsg
!= (const char **) NULL
)
666 *errmsg
= "illegal bitmask";
669 return insn
| (mb
<< 6) | (me
<< 1);
673 extract_mbe(unsigned long insn
, int *invalid
)
679 if (invalid
!= (int *) NULL
)
683 mb
= (insn
>> 6) & 0x1f;
684 me
= (insn
>> 1) & 0x1f;
685 for (i
= mb
; i
< me
; i
++)
686 ret
|= 1 << (31 - i
);
690 /* The MB or ME field in an MD or MDS form instruction. The high bit
691 is wrapped to the low end. */
695 insert_mb6(unsigned long insn
, long value
, const char **errmsg
)
697 return insn
| ((value
& 0x1f) << 6) | (value
& 0x20);
702 extract_mb6(unsigned long insn
, int *invalid
)
704 return ((insn
>> 6) & 0x1f) | (insn
& 0x20);
707 /* The NB field in an X form instruction. The value 32 is stored as
711 insert_nb(unsigned long insn
, long value
, const char **errmsg
)
713 if (value
< 0 || value
> 32)
714 *errmsg
= "value out of range";
717 return insn
| ((value
& 0x1f) << 11);
722 extract_nb(unsigned long insn
, int *invalid
)
726 ret
= (insn
>> 11) & 0x1f;
732 /* The NSI field in a D form instruction. This is the same as the SI
733 field, only negated. The extraction function always marks it as
734 invalid, since we never want to recognize an instruction which uses
735 a field of this type. */
739 insert_nsi(unsigned long insn
, long value
, const char **errmsg
)
741 return insn
| ((- value
) & 0xffff);
745 extract_nsi(unsigned long insn
, int *invalid
)
747 if (invalid
!= (int *) NULL
)
749 if ((insn
& 0x8000) != 0)
750 return - ((insn
& 0xffff) - 0x10000);
752 return - (insn
& 0xffff);
755 /* The RA field in a D or X form instruction which is an updating
756 load, which means that the RA field may not be zero and may not
757 equal the RT field. */
760 insert_ral(unsigned long insn
, long value
, const char **errmsg
)
763 || value
== ((insn
>> 21) & 0x1f))
764 *errmsg
= "invalid register operand when updating";
765 return insn
| ((value
& 0x1f) << 16);
768 /* The RA field in an lmw instruction, which has special value
772 insert_ram(unsigned long insn
, long value
, const char **errmsg
)
774 if (value
>= ((insn
>> 21) & 0x1f))
775 *errmsg
= "index register in load range";
776 return insn
| ((value
& 0x1f) << 16);
779 /* The RA field in a D or X form instruction which is an updating
780 store or an updating floating point load, which means that the RA
781 field may not be zero. */
784 insert_ras(unsigned long insn
, long value
, const char **errmsg
)
787 *errmsg
= "invalid register operand when updating";
788 return insn
| ((value
& 0x1f) << 16);
791 /* The RB field in an X form instruction when it must be the same as
792 the RS field in the instruction. This is used for extended
793 mnemonics like mr. This operand is marked FAKE. The insertion
794 function just copies the BT field into the BA field, and the
795 extraction function just checks that the fields are the same. */
799 insert_rbs(unsigned long insn
, long value
, const char **errmsg
)
801 return insn
| (((insn
>> 21) & 0x1f) << 11);
805 extract_rbs(unsigned long insn
, int *invalid
)
807 if (invalid
!= (int *) NULL
808 && ((insn
>> 21) & 0x1f) != ((insn
>> 11) & 0x1f))
813 /* The SH field in an MD form instruction. This is split. */
817 insert_sh6(unsigned long insn
, long value
, const char **errmsg
)
819 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
824 extract_sh6(unsigned long insn
, int *invalid
)
826 return ((insn
>> 11) & 0x1f) | ((insn
<< 4) & 0x20);
829 /* The SPR field in an XFX form instruction. This is flipped--the
830 lower 5 bits are stored in the upper 5 and vice- versa. */
833 insert_spr(unsigned long insn
, long value
, const char **errmsg
)
835 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
839 extract_spr(unsigned long insn
, int *invalid
)
841 return ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
844 /* The TBR field in an XFX instruction. This is just like SPR, but it
845 is optional. When TBR is omitted, it must be inserted as 268 (the
846 magic number of the TB register). These functions treat 0
847 (indicating an omitted optional operand) as 268. This means that
848 ``mftb 4,0'' is not handled correctly. This does not matter very
849 much, since the architecture manual does not define mftb as
850 accepting any values other than 268 or 269. */
855 insert_tbr(unsigned long insn
, long value
, const char **errmsg
)
859 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
863 extract_tbr(unsigned long insn
, int *invalid
)
867 ret
= ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
873 /* Macros used to form opcodes. */
875 /* The main opcode. */
876 #define OP(x) (((x) & 0x3f) << 26)
877 #define OP_MASK OP (0x3f)
879 /* The main opcode combined with a trap code in the TO field of a D
880 form instruction. Used for extended mnemonics for the trap
882 #define OPTO(x,to) (OP (x) | (((to) & 0x1f) << 21))
883 #define OPTO_MASK (OP_MASK | TO_MASK)
885 /* The main opcode combined with a comparison size bit in the L field
886 of a D form or X form instruction. Used for extended mnemonics for
887 the comparison instructions. */
888 #define OPL(x,l) (OP (x) | (((l) & 1) << 21))
889 #define OPL_MASK OPL (0x3f,1)
891 /* An A form instruction. */
892 #define A(op, xop, rc) (OP (op) | (((xop) & 0x1f) << 1) | ((rc) & 1))
893 #define A_MASK A (0x3f, 0x1f, 1)
895 /* An A_MASK with the FRB field fixed. */
896 #define AFRB_MASK (A_MASK | FRB_MASK)
898 /* An A_MASK with the FRC field fixed. */
899 #define AFRC_MASK (A_MASK | FRC_MASK)
901 /* An A_MASK with the FRA and FRC fields fixed. */
902 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
904 /* A B form instruction. */
905 #define B(op, aa, lk) (OP (op) | (((aa) & 1) << 1) | ((lk) & 1))
906 #define B_MASK B (0x3f, 1, 1)
908 /* A B form instruction setting the BO field. */
909 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | (((bo) & 0x1f) << 21))
910 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
912 /* A BBO_MASK with the y bit of the BO field removed. This permits
913 matching a conditional branch regardless of the setting of the y
915 #define Y_MASK (1 << 21)
916 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
918 /* A B form instruction setting the BO field and the condition bits of
920 #define BBOCB(op, bo, cb, aa, lk) \
921 (BBO ((op), (bo), (aa), (lk)) | (((cb) & 0x3) << 16))
922 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
924 /* A BBOCB_MASK with the y bit of the BO field removed. */
925 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
927 /* A BBOYCB_MASK in which the BI field is fixed. */
928 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
930 /* The main opcode mask with the RA field clear. */
931 #define DRA_MASK (OP_MASK | RA_MASK)
933 /* A DS form instruction. */
934 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
935 #define DS_MASK DSO (0x3f, 3)
937 /* An M form instruction. */
938 #define M(op, rc) (OP (op) | ((rc) & 1))
939 #define M_MASK M (0x3f, 1)
941 /* An M form instruction with the ME field specified. */
942 #define MME(op, me, rc) (M ((op), (rc)) | (((me) & 0x1f) << 1))
944 /* An M_MASK with the MB and ME fields fixed. */
945 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
947 /* An M_MASK with the SH and ME fields fixed. */
948 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
950 /* An MD form instruction. */
951 #define MD(op, xop, rc) (OP (op) | (((xop) & 0x7) << 2) | ((rc) & 1))
952 #define MD_MASK MD (0x3f, 0x7, 1)
954 /* An MD_MASK with the MB field fixed. */
955 #define MDMB_MASK (MD_MASK | MB6_MASK)
957 /* An MD_MASK with the SH field fixed. */
958 #define MDSH_MASK (MD_MASK | SH6_MASK)
960 /* An MDS form instruction. */
961 #define MDS(op, xop, rc) (OP (op) | (((xop) & 0xf) << 1) | ((rc) & 1))
962 #define MDS_MASK MDS (0x3f, 0xf, 1)
964 /* An MDS_MASK with the MB field fixed. */
965 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
967 /* An SC form instruction. */
968 #define SC(op, sa, lk) (OP (op) | (((sa) & 1) << 1) | ((lk) & 1))
969 #define SC_MASK (OP_MASK | (0x3ff << 16) | (1 << 1) | 1)
971 /* An X form instruction. */
972 #define X(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
974 /* An X form instruction with the RC bit specified. */
975 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
977 /* The mask for an X form instruction. */
978 #define X_MASK XRC (0x3f, 0x3ff, 1)
980 /* An X_MASK with the RA field fixed. */
981 #define XRA_MASK (X_MASK | RA_MASK)
983 /* An X_MASK with the RB field fixed. */
984 #define XRB_MASK (X_MASK | RB_MASK)
986 /* An X_MASK with the RT field fixed. */
987 #define XRT_MASK (X_MASK | RT_MASK)
989 /* An X_MASK with the RA and RB fields fixed. */
990 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
992 /* An X_MASK with the RT and RA fields fixed. */
993 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
995 /* An X form comparison instruction. */
996 #define XCMPL(op, xop, l) (X ((op), (xop)) | (((l) & 1) << 21))
998 /* The mask for an X form comparison instruction. */
999 #define XCMP_MASK (X_MASK | (1 << 22))
1001 /* The mask for an X form comparison instruction with the L field
1003 #define XCMPL_MASK (XCMP_MASK | (1 << 21))
1005 /* An X form trap instruction with the TO field specified. */
1006 #define XTO(op, xop, to) (X ((op), (xop)) | (((to) & 0x1f) << 21))
1007 #define XTO_MASK (X_MASK | TO_MASK)
1009 /* An XFL form instruction. */
1010 #define XFL(op, xop, rc) (OP (op) | (((xop) & 0x3ff) << 1) | ((rc) & 1))
1011 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (1 << 25) | (1 << 16))
1013 /* An XL form instruction with the LK field set to 0. */
1014 #define XL(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
1016 /* An XL form instruction which uses the LK field. */
1017 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1019 /* The mask for an XL form instruction. */
1020 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1022 /* An XL form instruction which explicitly sets the BO field. */
1023 #define XLO(op, bo, xop, lk) \
1024 (XLLK ((op), (xop), (lk)) | (((bo) & 0x1f) << 21))
1025 #define XLO_MASK (XL_MASK | BO_MASK)
1027 /* An XL form instruction which explicitly sets the y bit of the BO
1029 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | (((y) & 1) << 21))
1030 #define XLYLK_MASK (XL_MASK | Y_MASK)
1032 /* An XL form instruction which sets the BO field and the condition
1033 bits of the BI field. */
1034 #define XLOCB(op, bo, cb, xop, lk) \
1035 (XLO ((op), (bo), (xop), (lk)) | (((cb) & 3) << 16))
1036 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1038 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1039 #define XLBB_MASK (XL_MASK | BB_MASK)
1040 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1041 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1043 /* An XL_MASK with the BO and BB fields fixed. */
1044 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1046 /* An XL_MASK with the BO, BI and BB fields fixed. */
1047 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1049 /* An XO form instruction. */
1050 #define XO(op, xop, oe, rc) \
1051 (OP (op) | (((xop) & 0x1ff) << 1) | (((oe) & 1) << 10) | ((rc) & 1))
1052 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1054 /* An XO_MASK with the RB field fixed. */
1055 #define XORB_MASK (XO_MASK | RB_MASK)
1057 /* An XS form instruction. */
1058 #define XS(op, xop, rc) (OP (op) | (((xop) & 0x1ff) << 2) | ((rc) & 1))
1059 #define XS_MASK XS (0x3f, 0x1ff, 1)
1061 /* A mask for the FXM version of an XFX form instruction. */
1062 #define XFXFXM_MASK (X_MASK | (1 << 20) | (1 << 11))
1064 /* An XFX form instruction with the FXM field filled in. */
1065 #define XFXM(op, xop, fxm) \
1066 (X ((op), (xop)) | (((fxm) & 0xff) << 12))
1068 /* An XFX form instruction with the SPR field filled in. */
1069 #define XSPR(op, xop, spr) \
1070 (X ((op), (xop)) | (((spr) & 0x1f) << 16) | (((spr) & 0x3e0) << 6))
1071 #define XSPR_MASK (X_MASK | SPR_MASK)
1073 /* An XFX form instruction with the SPR field filled in except for the
1075 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1077 /* An XFX form instruction with the SPR field filled in except for the
1079 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1081 /* The BO encodings used in extended conditional branch mnemonics. */
1082 #define BODNZF (0x0)
1083 #define BODNZFP (0x1)
1085 #define BODZFP (0x3)
1088 #define BODNZT (0x8)
1089 #define BODNZTP (0x9)
1091 #define BODZTP (0xb)
1094 #define BODNZ (0x10)
1095 #define BODNZP (0x11)
1097 #define BODZP (0x13)
1100 /* The BI condition bit encodings used in extended conditional branch
1107 /* The TO encodings used in extended trap mnemonics. */
1124 /* Smaller names for the flags so each entry in the opcodes table will
1125 fit on a single line. */
1127 #define PPC PPC_OPCODE_PPC
1128 #define POWER PPC_OPCODE_POWER
1129 #define POWER2 PPC_OPCODE_POWER2
1130 #define B32 PPC_OPCODE_32
1131 #define B64 PPC_OPCODE_64
1132 #define M601 PPC_OPCODE_601
1134 /* The opcode table.
1136 The format of the opcode table is:
1138 NAME OPCODE MASK FLAGS { OPERANDS }
1140 NAME is the name of the instruction.
1141 OPCODE is the instruction opcode.
1142 MASK is the opcode mask; this is used to tell the disassembler
1143 which bits in the actual opcode must match OPCODE.
1144 FLAGS are flags indicated what processors support the instruction.
1145 OPERANDS is the list of operands.
1147 The disassembler reads the table in order and prints the first
1148 instruction which matches, so this table is sorted to put more
1149 specific instructions before more general instructions. It is also
1150 sorted by major opcode. */
1152 const struct powerpc_opcode powerpc_opcodes
[] = {
1153 { "tdlgti", OPTO(2,TOLGT
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1154 { "tdllti", OPTO(2,TOLLT
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1155 { "tdeqi", OPTO(2,TOEQ
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1156 { "tdlgei", OPTO(2,TOLGE
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1157 { "tdlnli", OPTO(2,TOLNL
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1158 { "tdllei", OPTO(2,TOLLE
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1159 { "tdlngi", OPTO(2,TOLNG
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1160 { "tdgti", OPTO(2,TOGT
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1161 { "tdgei", OPTO(2,TOGE
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1162 { "tdnli", OPTO(2,TONL
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1163 { "tdlti", OPTO(2,TOLT
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1164 { "tdlei", OPTO(2,TOLE
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1165 { "tdngi", OPTO(2,TONG
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1166 { "tdnei", OPTO(2,TONE
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1167 { "tdi", OP(2), OP_MASK
, PPC
|B64
, { TO
, RA
, SI
} },
1169 { "twlgti", OPTO(3,TOLGT
), OPTO_MASK
, PPC
, { RA
, SI
} },
1170 { "tlgti", OPTO(3,TOLGT
), OPTO_MASK
, POWER
, { RA
, SI
} },
1171 { "twllti", OPTO(3,TOLLT
), OPTO_MASK
, PPC
, { RA
, SI
} },
1172 { "tllti", OPTO(3,TOLLT
), OPTO_MASK
, POWER
, { RA
, SI
} },
1173 { "tweqi", OPTO(3,TOEQ
), OPTO_MASK
, PPC
, { RA
, SI
} },
1174 { "teqi", OPTO(3,TOEQ
), OPTO_MASK
, POWER
, { RA
, SI
} },
1175 { "twlgei", OPTO(3,TOLGE
), OPTO_MASK
, PPC
, { RA
, SI
} },
1176 { "tlgei", OPTO(3,TOLGE
), OPTO_MASK
, POWER
, { RA
, SI
} },
1177 { "twlnli", OPTO(3,TOLNL
), OPTO_MASK
, PPC
, { RA
, SI
} },
1178 { "tlnli", OPTO(3,TOLNL
), OPTO_MASK
, POWER
, { RA
, SI
} },
1179 { "twllei", OPTO(3,TOLLE
), OPTO_MASK
, PPC
, { RA
, SI
} },
1180 { "tllei", OPTO(3,TOLLE
), OPTO_MASK
, POWER
, { RA
, SI
} },
1181 { "twlngi", OPTO(3,TOLNG
), OPTO_MASK
, PPC
, { RA
, SI
} },
1182 { "tlngi", OPTO(3,TOLNG
), OPTO_MASK
, POWER
, { RA
, SI
} },
1183 { "twgti", OPTO(3,TOGT
), OPTO_MASK
, PPC
, { RA
, SI
} },
1184 { "tgti", OPTO(3,TOGT
), OPTO_MASK
, POWER
, { RA
, SI
} },
1185 { "twgei", OPTO(3,TOGE
), OPTO_MASK
, PPC
, { RA
, SI
} },
1186 { "tgei", OPTO(3,TOGE
), OPTO_MASK
, POWER
, { RA
, SI
} },
1187 { "twnli", OPTO(3,TONL
), OPTO_MASK
, PPC
, { RA
, SI
} },
1188 { "tnli", OPTO(3,TONL
), OPTO_MASK
, POWER
, { RA
, SI
} },
1189 { "twlti", OPTO(3,TOLT
), OPTO_MASK
, PPC
, { RA
, SI
} },
1190 { "tlti", OPTO(3,TOLT
), OPTO_MASK
, POWER
, { RA
, SI
} },
1191 { "twlei", OPTO(3,TOLE
), OPTO_MASK
, PPC
, { RA
, SI
} },
1192 { "tlei", OPTO(3,TOLE
), OPTO_MASK
, POWER
, { RA
, SI
} },
1193 { "twngi", OPTO(3,TONG
), OPTO_MASK
, PPC
, { RA
, SI
} },
1194 { "tngi", OPTO(3,TONG
), OPTO_MASK
, POWER
, { RA
, SI
} },
1195 { "twnei", OPTO(3,TONE
), OPTO_MASK
, PPC
, { RA
, SI
} },
1196 { "tnei", OPTO(3,TONE
), OPTO_MASK
, POWER
, { RA
, SI
} },
1197 { "twi", OP(3), OP_MASK
, PPC
, { TO
, RA
, SI
} },
1198 { "ti", OP(3), OP_MASK
, POWER
, { TO
, RA
, SI
} },
1200 { "mulli", OP(7), OP_MASK
, PPC
, { RT
, RA
, SI
} },
1201 { "muli", OP(7), OP_MASK
, POWER
, { RT
, RA
, SI
} },
1203 { "subfic", OP(8), OP_MASK
, PPC
, { RT
, RA
, SI
} },
1204 { "sfi", OP(8), OP_MASK
, POWER
, { RT
, RA
, SI
} },
1206 { "dozi", OP(9), OP_MASK
, POWER
|M601
, { RT
, RA
, SI
} },
1208 { "cmplwi", OPL(10,0), OPL_MASK
, PPC
, { OBF
, RA
, UI
} },
1209 { "cmpldi", OPL(10,1), OPL_MASK
, PPC
|B64
, { OBF
, RA
, UI
} },
1210 { "cmpli", OP(10), OP_MASK
, PPC
, { BF
, L
, RA
, UI
} },
1211 { "cmpli", OP(10), OP_MASK
, POWER
, { BF
, RA
, UI
} },
1213 { "cmpwi", OPL(11,0), OPL_MASK
, PPC
, { OBF
, RA
, SI
} },
1214 { "cmpdi", OPL(11,1), OPL_MASK
, PPC
|B64
, { OBF
, RA
, SI
} },
1215 { "cmpi", OP(11), OP_MASK
, PPC
, { BF
, L
, RA
, SI
} },
1216 { "cmpi", OP(11), OP_MASK
, POWER
, { BF
, RA
, SI
} },
1218 { "addic", OP(12), OP_MASK
, PPC
, { RT
, RA
, SI
} },
1219 { "ai", OP(12), OP_MASK
, POWER
, { RT
, RA
, SI
} },
1220 { "subic", OP(12), OP_MASK
, PPC
, { RT
, RA
, NSI
} },
1222 { "addic.", OP(13), OP_MASK
, PPC
, { RT
, RA
, SI
} },
1223 { "ai.", OP(13), OP_MASK
, POWER
, { RT
, RA
, SI
} },
1224 { "subic.", OP(13), OP_MASK
, PPC
, { RT
, RA
, NSI
} },
1226 { "li", OP(14), DRA_MASK
, PPC
, { RT
, SI
} },
1227 { "lil", OP(14), DRA_MASK
, POWER
, { RT
, SI
} },
1228 { "addi", OP(14), OP_MASK
, PPC
, { RT
, RA
, SI
} },
1229 { "cal", OP(14), OP_MASK
, POWER
, { RT
, D
, RA
} },
1230 { "subi", OP(14), OP_MASK
, PPC
, { RT
, RA
, NSI
} },
1231 { "la", OP(14), OP_MASK
, PPC
, { RT
, D
, RA
} },
1233 { "lis", OP(15), DRA_MASK
, PPC
, { RT
, SISIGNOPT
} },
1234 { "liu", OP(15), DRA_MASK
, POWER
, { RT
, SISIGNOPT
} },
1235 { "addis", OP(15), OP_MASK
, PPC
, { RT
,RA
,SISIGNOPT
} },
1236 { "cau", OP(15), OP_MASK
, POWER
, { RT
,RA
,SISIGNOPT
} },
1237 { "subis", OP(15), OP_MASK
, PPC
, { RT
, RA
, NSI
} },
1239 { "bdnz-", BBO(16,BODNZ
,0,0), BBOYBI_MASK
, PPC
, { BDM
} },
1240 { "bdnz+", BBO(16,BODNZ
,0,0), BBOYBI_MASK
, PPC
, { BDP
} },
1241 { "bdnz", BBO(16,BODNZ
,0,0), BBOYBI_MASK
, PPC
, { BD
} },
1242 { "bdn", BBO(16,BODNZ
,0,0), BBOYBI_MASK
, POWER
, { BD
} },
1243 { "bdnzl-", BBO(16,BODNZ
,0,1), BBOYBI_MASK
, PPC
, { BDM
} },
1244 { "bdnzl+", BBO(16,BODNZ
,0,1), BBOYBI_MASK
, PPC
, { BDP
} },
1245 { "bdnzl", BBO(16,BODNZ
,0,1), BBOYBI_MASK
, PPC
, { BD
} },
1246 { "bdnl", BBO(16,BODNZ
,0,1), BBOYBI_MASK
, POWER
, { BD
} },
1247 { "bdnza-", BBO(16,BODNZ
,1,0), BBOYBI_MASK
, PPC
, { BDMA
} },
1248 { "bdnza+", BBO(16,BODNZ
,1,0), BBOYBI_MASK
, PPC
, { BDPA
} },
1249 { "bdnza", BBO(16,BODNZ
,1,0), BBOYBI_MASK
, PPC
, { BDA
} },
1250 { "bdna", BBO(16,BODNZ
,1,0), BBOYBI_MASK
, POWER
, { BDA
} },
1251 { "bdnzla-", BBO(16,BODNZ
,1,1), BBOYBI_MASK
, PPC
, { BDMA
} },
1252 { "bdnzla+", BBO(16,BODNZ
,1,1), BBOYBI_MASK
, PPC
, { BDPA
} },
1253 { "bdnzla", BBO(16,BODNZ
,1,1), BBOYBI_MASK
, PPC
, { BDA
} },
1254 { "bdnla", BBO(16,BODNZ
,1,1), BBOYBI_MASK
, POWER
, { BDA
} },
1255 { "bdz-", BBO(16,BODZ
,0,0), BBOYBI_MASK
, PPC
, { BDM
} },
1256 { "bdz+", BBO(16,BODZ
,0,0), BBOYBI_MASK
, PPC
, { BDP
} },
1257 { "bdz", BBO(16,BODZ
,0,0), BBOYBI_MASK
, PPC
|POWER
, { BD
} },
1258 { "bdzl-", BBO(16,BODZ
,0,1), BBOYBI_MASK
, PPC
, { BDM
} },
1259 { "bdzl+", BBO(16,BODZ
,0,1), BBOYBI_MASK
, PPC
, { BDP
} },
1260 { "bdzl", BBO(16,BODZ
,0,1), BBOYBI_MASK
, PPC
|POWER
, { BD
} },
1261 { "bdza-", BBO(16,BODZ
,1,0), BBOYBI_MASK
, PPC
, { BDMA
} },
1262 { "bdza+", BBO(16,BODZ
,1,0), BBOYBI_MASK
, PPC
, { BDPA
} },
1263 { "bdza", BBO(16,BODZ
,1,0), BBOYBI_MASK
, PPC
|POWER
, { BDA
} },
1264 { "bdzla-", BBO(16,BODZ
,1,1), BBOYBI_MASK
, PPC
, { BDMA
} },
1265 { "bdzla+", BBO(16,BODZ
,1,1), BBOYBI_MASK
, PPC
, { BDPA
} },
1266 { "bdzla", BBO(16,BODZ
,1,1), BBOYBI_MASK
, PPC
|POWER
, { BDA
} },
1267 { "blt-", BBOCB(16,BOT
,CBLT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1268 { "blt+", BBOCB(16,BOT
,CBLT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1269 { "blt", BBOCB(16,BOT
,CBLT
,0,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1270 { "bltl-", BBOCB(16,BOT
,CBLT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1271 { "bltl+", BBOCB(16,BOT
,CBLT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1272 { "bltl", BBOCB(16,BOT
,CBLT
,0,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1273 { "blta-", BBOCB(16,BOT
,CBLT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1274 { "blta+", BBOCB(16,BOT
,CBLT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1275 { "blta", BBOCB(16,BOT
,CBLT
,1,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1276 { "bltla-", BBOCB(16,BOT
,CBLT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1277 { "bltla+", BBOCB(16,BOT
,CBLT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1278 { "bltla", BBOCB(16,BOT
,CBLT
,1,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1279 { "bgt-", BBOCB(16,BOT
,CBGT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1280 { "bgt+", BBOCB(16,BOT
,CBGT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1281 { "bgt", BBOCB(16,BOT
,CBGT
,0,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1282 { "bgtl-", BBOCB(16,BOT
,CBGT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1283 { "bgtl+", BBOCB(16,BOT
,CBGT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1284 { "bgtl", BBOCB(16,BOT
,CBGT
,0,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1285 { "bgta-", BBOCB(16,BOT
,CBGT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1286 { "bgta+", BBOCB(16,BOT
,CBGT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1287 { "bgta", BBOCB(16,BOT
,CBGT
,1,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1288 { "bgtla-", BBOCB(16,BOT
,CBGT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1289 { "bgtla+", BBOCB(16,BOT
,CBGT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1290 { "bgtla", BBOCB(16,BOT
,CBGT
,1,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1291 { "beq-", BBOCB(16,BOT
,CBEQ
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1292 { "beq+", BBOCB(16,BOT
,CBEQ
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1293 { "beq", BBOCB(16,BOT
,CBEQ
,0,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1294 { "beql-", BBOCB(16,BOT
,CBEQ
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1295 { "beql+", BBOCB(16,BOT
,CBEQ
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1296 { "beql", BBOCB(16,BOT
,CBEQ
,0,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1297 { "beqa-", BBOCB(16,BOT
,CBEQ
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1298 { "beqa+", BBOCB(16,BOT
,CBEQ
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1299 { "beqa", BBOCB(16,BOT
,CBEQ
,1,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1300 { "beqla-", BBOCB(16,BOT
,CBEQ
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1301 { "beqla+", BBOCB(16,BOT
,CBEQ
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1302 { "beqla", BBOCB(16,BOT
,CBEQ
,1,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1303 { "bso-", BBOCB(16,BOT
,CBSO
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1304 { "bso+", BBOCB(16,BOT
,CBSO
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1305 { "bso", BBOCB(16,BOT
,CBSO
,0,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1306 { "bsol-", BBOCB(16,BOT
,CBSO
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1307 { "bsol+", BBOCB(16,BOT
,CBSO
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1308 { "bsol", BBOCB(16,BOT
,CBSO
,0,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1309 { "bsoa-", BBOCB(16,BOT
,CBSO
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1310 { "bsoa+", BBOCB(16,BOT
,CBSO
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1311 { "bsoa", BBOCB(16,BOT
,CBSO
,1,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1312 { "bsola-", BBOCB(16,BOT
,CBSO
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1313 { "bsola+", BBOCB(16,BOT
,CBSO
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1314 { "bsola", BBOCB(16,BOT
,CBSO
,1,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1315 { "bun-", BBOCB(16,BOT
,CBSO
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1316 { "bun+", BBOCB(16,BOT
,CBSO
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1317 { "bun", BBOCB(16,BOT
,CBSO
,0,0), BBOYCB_MASK
, PPC
, { CR
, BD
} },
1318 { "bunl-", BBOCB(16,BOT
,CBSO
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1319 { "bunl+", BBOCB(16,BOT
,CBSO
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1320 { "bunl", BBOCB(16,BOT
,CBSO
,0,1), BBOYCB_MASK
, PPC
, { CR
, BD
} },
1321 { "buna-", BBOCB(16,BOT
,CBSO
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1322 { "buna+", BBOCB(16,BOT
,CBSO
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1323 { "buna", BBOCB(16,BOT
,CBSO
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDA
} },
1324 { "bunla-", BBOCB(16,BOT
,CBSO
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1325 { "bunla+", BBOCB(16,BOT
,CBSO
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1326 { "bunla", BBOCB(16,BOT
,CBSO
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDA
} },
1327 { "bge-", BBOCB(16,BOF
,CBLT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1328 { "bge+", BBOCB(16,BOF
,CBLT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1329 { "bge", BBOCB(16,BOF
,CBLT
,0,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1330 { "bgel-", BBOCB(16,BOF
,CBLT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1331 { "bgel+", BBOCB(16,BOF
,CBLT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1332 { "bgel", BBOCB(16,BOF
,CBLT
,0,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1333 { "bgea-", BBOCB(16,BOF
,CBLT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1334 { "bgea+", BBOCB(16,BOF
,CBLT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1335 { "bgea", BBOCB(16,BOF
,CBLT
,1,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1336 { "bgela-", BBOCB(16,BOF
,CBLT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1337 { "bgela+", BBOCB(16,BOF
,CBLT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1338 { "bgela", BBOCB(16,BOF
,CBLT
,1,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1339 { "bnl-", BBOCB(16,BOF
,CBLT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1340 { "bnl+", BBOCB(16,BOF
,CBLT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1341 { "bnl", BBOCB(16,BOF
,CBLT
,0,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1342 { "bnll-", BBOCB(16,BOF
,CBLT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1343 { "bnll+", BBOCB(16,BOF
,CBLT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1344 { "bnll", BBOCB(16,BOF
,CBLT
,0,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1345 { "bnla-", BBOCB(16,BOF
,CBLT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1346 { "bnla+", BBOCB(16,BOF
,CBLT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1347 { "bnla", BBOCB(16,BOF
,CBLT
,1,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1348 { "bnlla-", BBOCB(16,BOF
,CBLT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1349 { "bnlla+", BBOCB(16,BOF
,CBLT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1350 { "bnlla", BBOCB(16,BOF
,CBLT
,1,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1351 { "ble-", BBOCB(16,BOF
,CBGT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1352 { "ble+", BBOCB(16,BOF
,CBGT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1353 { "ble", BBOCB(16,BOF
,CBGT
,0,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1354 { "blel-", BBOCB(16,BOF
,CBGT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1355 { "blel+", BBOCB(16,BOF
,CBGT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1356 { "blel", BBOCB(16,BOF
,CBGT
,0,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1357 { "blea-", BBOCB(16,BOF
,CBGT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1358 { "blea+", BBOCB(16,BOF
,CBGT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1359 { "blea", BBOCB(16,BOF
,CBGT
,1,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1360 { "blela-", BBOCB(16,BOF
,CBGT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1361 { "blela+", BBOCB(16,BOF
,CBGT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1362 { "blela", BBOCB(16,BOF
,CBGT
,1,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1363 { "bng-", BBOCB(16,BOF
,CBGT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1364 { "bng+", BBOCB(16,BOF
,CBGT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1365 { "bng", BBOCB(16,BOF
,CBGT
,0,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1366 { "bngl-", BBOCB(16,BOF
,CBGT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1367 { "bngl+", BBOCB(16,BOF
,CBGT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1368 { "bngl", BBOCB(16,BOF
,CBGT
,0,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1369 { "bnga-", BBOCB(16,BOF
,CBGT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1370 { "bnga+", BBOCB(16,BOF
,CBGT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1371 { "bnga", BBOCB(16,BOF
,CBGT
,1,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1372 { "bngla-", BBOCB(16,BOF
,CBGT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1373 { "bngla+", BBOCB(16,BOF
,CBGT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1374 { "bngla", BBOCB(16,BOF
,CBGT
,1,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1375 { "bne-", BBOCB(16,BOF
,CBEQ
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1376 { "bne+", BBOCB(16,BOF
,CBEQ
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1377 { "bne", BBOCB(16,BOF
,CBEQ
,0,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1378 { "bnel-", BBOCB(16,BOF
,CBEQ
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1379 { "bnel+", BBOCB(16,BOF
,CBEQ
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1380 { "bnel", BBOCB(16,BOF
,CBEQ
,0,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1381 { "bnea-", BBOCB(16,BOF
,CBEQ
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1382 { "bnea+", BBOCB(16,BOF
,CBEQ
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1383 { "bnea", BBOCB(16,BOF
,CBEQ
,1,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1384 { "bnela-", BBOCB(16,BOF
,CBEQ
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1385 { "bnela+", BBOCB(16,BOF
,CBEQ
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1386 { "bnela", BBOCB(16,BOF
,CBEQ
,1,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1387 { "bns-", BBOCB(16,BOF
,CBSO
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1388 { "bns+", BBOCB(16,BOF
,CBSO
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1389 { "bns", BBOCB(16,BOF
,CBSO
,0,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1390 { "bnsl-", BBOCB(16,BOF
,CBSO
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1391 { "bnsl+", BBOCB(16,BOF
,CBSO
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1392 { "bnsl", BBOCB(16,BOF
,CBSO
,0,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1393 { "bnsa-", BBOCB(16,BOF
,CBSO
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1394 { "bnsa+", BBOCB(16,BOF
,CBSO
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1395 { "bnsa", BBOCB(16,BOF
,CBSO
,1,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1396 { "bnsla-", BBOCB(16,BOF
,CBSO
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1397 { "bnsla+", BBOCB(16,BOF
,CBSO
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1398 { "bnsla", BBOCB(16,BOF
,CBSO
,1,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1399 { "bnu-", BBOCB(16,BOF
,CBSO
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1400 { "bnu+", BBOCB(16,BOF
,CBSO
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1401 { "bnu", BBOCB(16,BOF
,CBSO
,0,0), BBOYCB_MASK
, PPC
, { CR
, BD
} },
1402 { "bnul-", BBOCB(16,BOF
,CBSO
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1403 { "bnul+", BBOCB(16,BOF
,CBSO
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1404 { "bnul", BBOCB(16,BOF
,CBSO
,0,1), BBOYCB_MASK
, PPC
, { CR
, BD
} },
1405 { "bnua-", BBOCB(16,BOF
,CBSO
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1406 { "bnua+", BBOCB(16,BOF
,CBSO
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1407 { "bnua", BBOCB(16,BOF
,CBSO
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDA
} },
1408 { "bnula-", BBOCB(16,BOF
,CBSO
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1409 { "bnula+", BBOCB(16,BOF
,CBSO
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1410 { "bnula", BBOCB(16,BOF
,CBSO
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDA
} },
1411 { "bdnzt-", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPC
, { BI
, BDM
} },
1412 { "bdnzt+", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPC
, { BI
, BDP
} },
1413 { "bdnzt", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPC
, { BI
, BD
} },
1414 { "bdnztl-", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPC
, { BI
, BDM
} },
1415 { "bdnztl+", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPC
, { BI
, BDP
} },
1416 { "bdnztl", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPC
, { BI
, BD
} },
1417 { "bdnzta-", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1418 { "bdnzta+", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1419 { "bdnzta", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPC
, { BI
, BDA
} },
1420 { "bdnztla-",BBO(16,BODNZT
,1,1), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1421 { "bdnztla+",BBO(16,BODNZT
,1,1), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1422 { "bdnztla", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPC
, { BI
, BDA
} },
1423 { "bdnzf-", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPC
, { BI
, BDM
} },
1424 { "bdnzf+", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPC
, { BI
, BDP
} },
1425 { "bdnzf", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPC
, { BI
, BD
} },
1426 { "bdnzfl-", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPC
, { BI
, BDM
} },
1427 { "bdnzfl+", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPC
, { BI
, BDP
} },
1428 { "bdnzfl", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPC
, { BI
, BD
} },
1429 { "bdnzfa-", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1430 { "bdnzfa+", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1431 { "bdnzfa", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPC
, { BI
, BDA
} },
1432 { "bdnzfla-",BBO(16,BODNZF
,1,1), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1433 { "bdnzfla+",BBO(16,BODNZF
,1,1), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1434 { "bdnzfla", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPC
, { BI
, BDA
} },
1435 { "bt-", BBO(16,BOT
,0,0), BBOY_MASK
, PPC
, { BI
, BDM
} },
1436 { "bt+", BBO(16,BOT
,0,0), BBOY_MASK
, PPC
, { BI
, BDP
} },
1437 { "bt", BBO(16,BOT
,0,0), BBOY_MASK
, PPC
, { BI
, BD
} },
1438 { "bbt", BBO(16,BOT
,0,0), BBOY_MASK
, POWER
, { BI
, BD
} },
1439 { "btl-", BBO(16,BOT
,0,1), BBOY_MASK
, PPC
, { BI
, BDM
} },
1440 { "btl+", BBO(16,BOT
,0,1), BBOY_MASK
, PPC
, { BI
, BDP
} },
1441 { "btl", BBO(16,BOT
,0,1), BBOY_MASK
, PPC
, { BI
, BD
} },
1442 { "bbtl", BBO(16,BOT
,0,1), BBOY_MASK
, POWER
, { BI
, BD
} },
1443 { "bta-", BBO(16,BOT
,1,0), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1444 { "bta+", BBO(16,BOT
,1,0), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1445 { "bta", BBO(16,BOT
,1,0), BBOY_MASK
, PPC
, { BI
, BDA
} },
1446 { "bbta", BBO(16,BOT
,1,0), BBOY_MASK
, POWER
, { BI
, BDA
} },
1447 { "btla-", BBO(16,BOT
,1,1), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1448 { "btla+", BBO(16,BOT
,1,1), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1449 { "btla", BBO(16,BOT
,1,1), BBOY_MASK
, PPC
, { BI
, BDA
} },
1450 { "bbtla", BBO(16,BOT
,1,1), BBOY_MASK
, POWER
, { BI
, BDA
} },
1451 { "bf-", BBO(16,BOF
,0,0), BBOY_MASK
, PPC
, { BI
, BDM
} },
1452 { "bf+", BBO(16,BOF
,0,0), BBOY_MASK
, PPC
, { BI
, BDP
} },
1453 { "bf", BBO(16,BOF
,0,0), BBOY_MASK
, PPC
, { BI
, BD
} },
1454 { "bbf", BBO(16,BOF
,0,0), BBOY_MASK
, POWER
, { BI
, BD
} },
1455 { "bfl-", BBO(16,BOF
,0,1), BBOY_MASK
, PPC
, { BI
, BDM
} },
1456 { "bfl+", BBO(16,BOF
,0,1), BBOY_MASK
, PPC
, { BI
, BDP
} },
1457 { "bfl", BBO(16,BOF
,0,1), BBOY_MASK
, PPC
, { BI
, BD
} },
1458 { "bbfl", BBO(16,BOF
,0,1), BBOY_MASK
, POWER
, { BI
, BD
} },
1459 { "bfa-", BBO(16,BOF
,1,0), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1460 { "bfa+", BBO(16,BOF
,1,0), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1461 { "bfa", BBO(16,BOF
,1,0), BBOY_MASK
, PPC
, { BI
, BDA
} },
1462 { "bbfa", BBO(16,BOF
,1,0), BBOY_MASK
, POWER
, { BI
, BDA
} },
1463 { "bfla-", BBO(16,BOF
,1,1), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1464 { "bfla+", BBO(16,BOF
,1,1), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1465 { "bfla", BBO(16,BOF
,1,1), BBOY_MASK
, PPC
, { BI
, BDA
} },
1466 { "bbfla", BBO(16,BOF
,1,1), BBOY_MASK
, POWER
, { BI
, BDA
} },
1467 { "bdzt-", BBO(16,BODZT
,0,0), BBOY_MASK
, PPC
, { BI
, BDM
} },
1468 { "bdzt+", BBO(16,BODZT
,0,0), BBOY_MASK
, PPC
, { BI
, BDP
} },
1469 { "bdzt", BBO(16,BODZT
,0,0), BBOY_MASK
, PPC
, { BI
, BD
} },
1470 { "bdztl-", BBO(16,BODZT
,0,1), BBOY_MASK
, PPC
, { BI
, BDM
} },
1471 { "bdztl+", BBO(16,BODZT
,0,1), BBOY_MASK
, PPC
, { BI
, BDP
} },
1472 { "bdztl", BBO(16,BODZT
,0,1), BBOY_MASK
, PPC
, { BI
, BD
} },
1473 { "bdzta-", BBO(16,BODZT
,1,0), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1474 { "bdzta+", BBO(16,BODZT
,1,0), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1475 { "bdzta", BBO(16,BODZT
,1,0), BBOY_MASK
, PPC
, { BI
, BDA
} },
1476 { "bdztla-", BBO(16,BODZT
,1,1), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1477 { "bdztla+", BBO(16,BODZT
,1,1), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1478 { "bdztla", BBO(16,BODZT
,1,1), BBOY_MASK
, PPC
, { BI
, BDA
} },
1479 { "bdzf-", BBO(16,BODZF
,0,0), BBOY_MASK
, PPC
, { BI
, BDM
} },
1480 { "bdzf+", BBO(16,BODZF
,0,0), BBOY_MASK
, PPC
, { BI
, BDP
} },
1481 { "bdzf", BBO(16,BODZF
,0,0), BBOY_MASK
, PPC
, { BI
, BD
} },
1482 { "bdzfl-", BBO(16,BODZF
,0,1), BBOY_MASK
, PPC
, { BI
, BDM
} },
1483 { "bdzfl+", BBO(16,BODZF
,0,1), BBOY_MASK
, PPC
, { BI
, BDP
} },
1484 { "bdzfl", BBO(16,BODZF
,0,1), BBOY_MASK
, PPC
, { BI
, BD
} },
1485 { "bdzfa-", BBO(16,BODZF
,1,0), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1486 { "bdzfa+", BBO(16,BODZF
,1,0), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1487 { "bdzfa", BBO(16,BODZF
,1,0), BBOY_MASK
, PPC
, { BI
, BDA
} },
1488 { "bdzfla-", BBO(16,BODZF
,1,1), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1489 { "bdzfla+", BBO(16,BODZF
,1,1), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1490 { "bdzfla", BBO(16,BODZF
,1,1), BBOY_MASK
, PPC
, { BI
, BDA
} },
1491 { "bc-", B(16,0,0), B_MASK
, PPC
, { BOE
, BI
, BDM
} },
1492 { "bc+", B(16,0,0), B_MASK
, PPC
, { BOE
, BI
, BDP
} },
1493 { "bc", B(16,0,0), B_MASK
, PPC
|POWER
, { BO
, BI
, BD
} },
1494 { "bcl-", B(16,0,1), B_MASK
, PPC
, { BOE
, BI
, BDM
} },
1495 { "bcl+", B(16,0,1), B_MASK
, PPC
, { BOE
, BI
, BDP
} },
1496 { "bcl", B(16,0,1), B_MASK
, PPC
|POWER
, { BO
, BI
, BD
} },
1497 { "bca-", B(16,1,0), B_MASK
, PPC
, { BOE
, BI
, BDMA
} },
1498 { "bca+", B(16,1,0), B_MASK
, PPC
, { BOE
, BI
, BDPA
} },
1499 { "bca", B(16,1,0), B_MASK
, PPC
|POWER
, { BO
, BI
, BDA
} },
1500 { "bcla-", B(16,1,1), B_MASK
, PPC
, { BOE
, BI
, BDMA
} },
1501 { "bcla+", B(16,1,1), B_MASK
, PPC
, { BOE
, BI
, BDPA
} },
1502 { "bcla", B(16,1,1), B_MASK
, PPC
|POWER
, { BO
, BI
, BDA
} },
1504 { "sc", SC(17,1,0), 0xffffffff, PPC
, { 0 } },
1505 { "svc", SC(17,0,0), SC_MASK
, POWER
, { LEV
, FL1
, FL2
} },
1506 { "svcl", SC(17,0,1), SC_MASK
, POWER
, { LEV
, FL1
, FL2
} },
1507 { "svca", SC(17,1,0), SC_MASK
, POWER
, { SV
} },
1508 { "svcla", SC(17,1,1), SC_MASK
, POWER
, { SV
} },
1510 { "b", B(18,0,0), B_MASK
, PPC
|POWER
, { LI
} },
1511 { "bl", B(18,0,1), B_MASK
, PPC
|POWER
, { LI
} },
1512 { "ba", B(18,1,0), B_MASK
, PPC
|POWER
, { LIA
} },
1513 { "bla", B(18,1,1), B_MASK
, PPC
|POWER
, { LIA
} },
1515 { "mcrf", XL(19,0), XLBB_MASK
|(3<<21)|(3<<16), PPC
|POWER
, { BF
, BFA
} },
1517 { "blr", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PPC
, { 0 } },
1518 { "br", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, POWER
, { 0 } },
1519 { "blrl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PPC
, { 0 } },
1520 { "brl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, POWER
, { 0 } },
1521 { "bdnzlr", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPC
, { 0 } },
1522 { "bdnzlr-", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPC
, { 0 } },
1523 { "bdnzlr+", XLO(19,BODNZP
,16,0), XLBOBIBB_MASK
, PPC
, { 0 } },
1524 { "bdnzlrl", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPC
, { 0 } },
1525 { "bdnzlrl-",XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPC
, { 0 } },
1526 { "bdnzlrl+",XLO(19,BODNZP
,16,1), XLBOBIBB_MASK
, PPC
, { 0 } },
1527 { "bdzlr", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPC
, { 0 } },
1528 { "bdzlr-", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPC
, { 0 } },
1529 { "bdzlr+", XLO(19,BODZP
,16,0), XLBOBIBB_MASK
, PPC
, { 0 } },
1530 { "bdzlrl", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPC
, { 0 } },
1531 { "bdzlrl-", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPC
, { 0 } },
1532 { "bdzlrl+", XLO(19,BODZP
,16,1), XLBOBIBB_MASK
, PPC
, { 0 } },
1533 { "bltlr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1534 { "bltlr-", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1535 { "bltlr+", XLOCB(19,BOTP
,CBLT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1536 { "bltr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, POWER
, { CR
} },
1537 { "bltlrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1538 { "bltlrl-", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1539 { "bltlrl+", XLOCB(19,BOTP
,CBLT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1540 { "bltrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, POWER
, { CR
} },
1541 { "bgtlr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1542 { "bgtlr-", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1543 { "bgtlr+", XLOCB(19,BOTP
,CBGT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1544 { "bgtr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, POWER
, { CR
} },
1545 { "bgtlrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1546 { "bgtlrl-", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1547 { "bgtlrl+", XLOCB(19,BOTP
,CBGT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1548 { "bgtrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, POWER
, { CR
} },
1549 { "beqlr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1550 { "beqlr-", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1551 { "beqlr+", XLOCB(19,BOTP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1552 { "beqr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, POWER
, { CR
} },
1553 { "beqlrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1554 { "beqlrl-", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1555 { "beqlrl+", XLOCB(19,BOTP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1556 { "beqrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, POWER
, { CR
} },
1557 { "bsolr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1558 { "bsolr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1559 { "bsolr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1560 { "bsor", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, POWER
, { CR
} },
1561 { "bsolrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1562 { "bsolrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1563 { "bsolrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1564 { "bsorl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, POWER
, { CR
} },
1565 { "bunlr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1566 { "bunlr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1567 { "bunlr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1568 { "bunlrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1569 { "bunlrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1570 { "bunlrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1571 { "bgelr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1572 { "bgelr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1573 { "bgelr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1574 { "bger", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, POWER
, { CR
} },
1575 { "bgelrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1576 { "bgelrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1577 { "bgelrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1578 { "bgerl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, POWER
, { CR
} },
1579 { "bnllr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1580 { "bnllr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1581 { "bnllr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1582 { "bnlr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, POWER
, { CR
} },
1583 { "bnllrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1584 { "bnllrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1585 { "bnllrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1586 { "bnlrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, POWER
, { CR
} },
1587 { "blelr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1588 { "blelr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1589 { "blelr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1590 { "bler", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, POWER
, { CR
} },
1591 { "blelrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1592 { "blelrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1593 { "blelrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1594 { "blerl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, POWER
, { CR
} },
1595 { "bnglr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1596 { "bnglr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1597 { "bnglr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1598 { "bngr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, POWER
, { CR
} },
1599 { "bnglrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1600 { "bnglrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1601 { "bnglrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1602 { "bngrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, POWER
, { CR
} },
1603 { "bnelr", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1604 { "bnelr-", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1605 { "bnelr+", XLOCB(19,BOFP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1606 { "bner", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, POWER
, { CR
} },
1607 { "bnelrl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1608 { "bnelrl-", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1609 { "bnelrl+", XLOCB(19,BOFP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1610 { "bnerl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, POWER
, { CR
} },
1611 { "bnslr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1612 { "bnslr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1613 { "bnslr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1614 { "bnsr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, POWER
, { CR
} },
1615 { "bnslrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1616 { "bnslrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1617 { "bnslrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1618 { "bnsrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, POWER
, { CR
} },
1619 { "bnulr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1620 { "bnulr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1621 { "bnulr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1622 { "bnulrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1623 { "bnulrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1624 { "bnulrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1625 { "btlr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1626 { "btlr-", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1627 { "btlr+", XLO(19,BOTP
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1628 { "bbtr", XLO(19,BOT
,16,0), XLBOBB_MASK
, POWER
, { BI
} },
1629 { "btlrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1630 { "btlrl-", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1631 { "btlrl+", XLO(19,BOTP
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1632 { "bbtrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, POWER
, { BI
} },
1633 { "bflr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1634 { "bflr-", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1635 { "bflr+", XLO(19,BOFP
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1636 { "bbfr", XLO(19,BOF
,16,0), XLBOBB_MASK
, POWER
, { BI
} },
1637 { "bflrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1638 { "bflrl-", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1639 { "bflrl+", XLO(19,BOFP
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1640 { "bbfrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, POWER
, { BI
} },
1641 { "bdnztlr", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1642 { "bdnztlr-",XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1643 { "bdnztlr+",XLO(19,BODNZTP
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1644 { "bdnztlrl",XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1645 { "bdnztlrl-",XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1646 { "bdnztlrl+",XLO(19,BODNZTP
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1647 { "bdnzflr", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1648 { "bdnzflr-",XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1649 { "bdnzflr+",XLO(19,BODNZFP
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1650 { "bdnzflrl",XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1651 { "bdnzflrl-",XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1652 { "bdnzflrl+",XLO(19,BODNZFP
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1653 { "bdztlr", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1654 { "bdztlr-", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1655 { "bdztlr+", XLO(19,BODZTP
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1656 { "bdztlrl", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1657 { "bdztlrl-",XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1658 { "bdztlrl+",XLO(19,BODZTP
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1659 { "bdzflr", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1660 { "bdzflr-", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1661 { "bdzflr+", XLO(19,BODZFP
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1662 { "bdzflrl", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1663 { "bdzflrl-",XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1664 { "bdzflrl+",XLO(19,BODZFP
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1665 { "bclr", XLLK(19,16,0), XLYBB_MASK
, PPC
, { BO
, BI
} },
1666 { "bclrl", XLLK(19,16,1), XLYBB_MASK
, PPC
, { BO
, BI
} },
1667 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK
, PPC
, { BOE
, BI
} },
1668 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK
, PPC
, { BOE
, BI
} },
1669 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK
, PPC
, { BOE
, BI
} },
1670 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK
, PPC
, { BOE
, BI
} },
1671 { "bcr", XLLK(19,16,0), XLBB_MASK
, POWER
, { BO
, BI
} },
1672 { "bcrl", XLLK(19,16,1), XLBB_MASK
, POWER
, { BO
, BI
} },
1674 { "crnot", XL(19,33), XL_MASK
, PPC
, { BT
, BA
, BBA
} },
1675 { "crnor", XL(19,33), XL_MASK
, PPC
|POWER
, { BT
, BA
, BB
} },
1677 { "rfi", XL(19,50), 0xffffffff, PPC
|POWER
, { 0 } },
1678 { "rfci", XL(19,51), 0xffffffff, PPC
, { 0 } },
1680 { "rfsvc", XL(19,82), 0xffffffff, POWER
, { 0 } },
1682 { "crandc", XL(19,129), XL_MASK
, PPC
|POWER
, { BT
, BA
, BB
} },
1684 { "isync", XL(19,150), 0xffffffff, PPC
, { 0 } },
1685 { "ics", XL(19,150), 0xffffffff, POWER
, { 0 } },
1687 { "crclr", XL(19,193), XL_MASK
, PPC
, { BT
, BAT
, BBA
} },
1688 { "crxor", XL(19,193), XL_MASK
, PPC
|POWER
, { BT
, BA
, BB
} },
1690 { "crnand", XL(19,225), XL_MASK
, PPC
|POWER
, { BT
, BA
, BB
} },
1692 { "crand", XL(19,257), XL_MASK
, PPC
|POWER
, { BT
, BA
, BB
} },
1694 { "crset", XL(19,289), XL_MASK
, PPC
, { BT
, BAT
, BBA
} },
1695 { "creqv", XL(19,289), XL_MASK
, PPC
|POWER
, { BT
, BA
, BB
} },
1697 { "crorc", XL(19,417), XL_MASK
, PPC
|POWER
, { BT
, BA
, BB
} },
1699 { "crmove", XL(19,449), XL_MASK
, PPC
, { BT
, BA
, BBA
} },
1700 { "cror", XL(19,449), XL_MASK
, PPC
|POWER
, { BT
, BA
, BB
} },
1702 { "bctr", XLO(19,BOU
,528,0), XLBOBIBB_MASK
, PPC
|POWER
, { 0 } },
1703 { "bctrl", XLO(19,BOU
,528,1), XLBOBIBB_MASK
, PPC
|POWER
, { 0 } },
1704 { "bltctr", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1705 { "bltctr-", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1706 { "bltctr+", XLOCB(19,BOTP
,CBLT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1707 { "bltctrl", XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1708 { "bltctrl-",XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1709 { "bltctrl+",XLOCB(19,BOTP
,CBLT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1710 { "bgtctr", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1711 { "bgtctr-", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1712 { "bgtctr+", XLOCB(19,BOTP
,CBGT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1713 { "bgtctrl", XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1714 { "bgtctrl-",XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1715 { "bgtctrl+",XLOCB(19,BOTP
,CBGT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1716 { "beqctr", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1717 { "beqctr-", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1718 { "beqctr+", XLOCB(19,BOTP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1719 { "beqctrl", XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1720 { "beqctrl-",XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1721 { "beqctrl+",XLOCB(19,BOTP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1722 { "bsoctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1723 { "bsoctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1724 { "bsoctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1725 { "bsoctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1726 { "bsoctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1727 { "bsoctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1728 { "bunctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1729 { "bunctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1730 { "bunctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1731 { "bunctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1732 { "bunctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1733 { "bunctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1734 { "bgectr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1735 { "bgectr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1736 { "bgectr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1737 { "bgectrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1738 { "bgectrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1739 { "bgectrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1740 { "bnlctr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1741 { "bnlctr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1742 { "bnlctr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1743 { "bnlctrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1744 { "bnlctrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1745 { "bnlctrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1746 { "blectr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1747 { "blectr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1748 { "blectr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1749 { "blectrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1750 { "blectrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1751 { "blectrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1752 { "bngctr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1753 { "bngctr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1754 { "bngctr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1755 { "bngctrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1756 { "bngctrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1757 { "bngctrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1758 { "bnectr", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1759 { "bnectr-", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1760 { "bnectr+", XLOCB(19,BOFP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1761 { "bnectrl", XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1762 { "bnectrl-",XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1763 { "bnectrl+",XLOCB(19,BOFP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1764 { "bnsctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1765 { "bnsctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1766 { "bnsctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1767 { "bnsctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1768 { "bnsctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1769 { "bnsctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1770 { "bnuctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1771 { "bnuctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1772 { "bnuctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1773 { "bnuctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1774 { "bnuctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1775 { "bnuctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1776 { "btctr", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPC
, { BI
} },
1777 { "btctr-", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPC
, { BI
} },
1778 { "btctr+", XLO(19,BOTP
,528,0), XLBOBB_MASK
, PPC
, { BI
} },
1779 { "btctrl", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPC
, { BI
} },
1780 { "btctrl-", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPC
, { BI
} },
1781 { "btctrl+", XLO(19,BOTP
,528,1), XLBOBB_MASK
, PPC
, { BI
} },
1782 { "bfctr", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPC
, { BI
} },
1783 { "bfctr-", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPC
, { BI
} },
1784 { "bfctr+", XLO(19,BOFP
,528,0), XLBOBB_MASK
, PPC
, { BI
} },
1785 { "bfctrl", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPC
, { BI
} },
1786 { "bfctrl-", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPC
, { BI
} },
1787 { "bfctrl+", XLO(19,BOFP
,528,1), XLBOBB_MASK
, PPC
, { BI
} },
1788 { "bcctr", XLLK(19,528,0), XLYBB_MASK
, PPC
, { BO
, BI
} },
1789 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK
, PPC
, { BOE
, BI
} },
1790 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK
, PPC
, { BOE
, BI
} },
1791 { "bcctrl", XLLK(19,528,1), XLYBB_MASK
, PPC
, { BO
, BI
} },
1792 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK
, PPC
, { BOE
, BI
} },
1793 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK
, PPC
, { BOE
, BI
} },
1794 { "bcc", XLLK(19,528,0), XLBB_MASK
, POWER
, { BO
, BI
} },
1795 { "bccl", XLLK(19,528,1), XLBB_MASK
, POWER
, { BO
, BI
} },
1797 { "rlwimi", M(20,0), M_MASK
, PPC
, { RA
,RS
,SH
,MBE
,ME
} },
1798 { "rlimi", M(20,0), M_MASK
, POWER
, { RA
,RS
,SH
,MBE
,ME
} },
1800 { "rlwimi.", M(20,1), M_MASK
, PPC
, { RA
,RS
,SH
,MBE
,ME
} },
1801 { "rlimi.", M(20,1), M_MASK
, POWER
, { RA
,RS
,SH
,MBE
,ME
} },
1803 { "rotlwi", MME(21,31,0), MMBME_MASK
, PPC
, { RA
, RS
, SH
} },
1804 { "clrlwi", MME(21,31,0), MSHME_MASK
, PPC
, { RA
, RS
, MB
} },
1805 { "rlwinm", M(21,0), M_MASK
, PPC
, { RA
,RS
,SH
,MBE
,ME
} },
1806 { "rlinm", M(21,0), M_MASK
, POWER
, { RA
,RS
,SH
,MBE
,ME
} },
1807 { "rotlwi.", MME(21,31,1), MMBME_MASK
, PPC
, { RA
,RS
,SH
} },
1808 { "clrlwi.", MME(21,31,1), MSHME_MASK
, PPC
, { RA
, RS
, MB
} },
1809 { "rlwinm.", M(21,1), M_MASK
, PPC
, { RA
,RS
,SH
,MBE
,ME
} },
1810 { "rlinm.", M(21,1), M_MASK
, POWER
, { RA
,RS
,SH
,MBE
,ME
} },
1812 { "rlmi", M(22,0), M_MASK
, POWER
|M601
, { RA
,RS
,RB
,MBE
,ME
} },
1813 { "rlmi.", M(22,1), M_MASK
, POWER
|M601
, { RA
,RS
,RB
,MBE
,ME
} },
1815 { "rotlw", MME(23,31,0), MMBME_MASK
, PPC
, { RA
, RS
, RB
} },
1816 { "rlwnm", M(23,0), M_MASK
, PPC
, { RA
,RS
,RB
,MBE
,ME
} },
1817 { "rlnm", M(23,0), M_MASK
, POWER
, { RA
,RS
,RB
,MBE
,ME
} },
1818 { "rotlw.", MME(23,31,1), MMBME_MASK
, PPC
, { RA
, RS
, RB
} },
1819 { "rlwnm.", M(23,1), M_MASK
, PPC
, { RA
,RS
,RB
,MBE
,ME
} },
1820 { "rlnm.", M(23,1), M_MASK
, POWER
, { RA
,RS
,RB
,MBE
,ME
} },
1822 { "nop", OP(24), 0xffffffff, PPC
, { 0 } },
1823 { "ori", OP(24), OP_MASK
, PPC
, { RA
, RS
, UI
} },
1824 { "oril", OP(24), OP_MASK
, POWER
, { RA
, RS
, UI
} },
1826 { "oris", OP(25), OP_MASK
, PPC
, { RA
, RS
, UI
} },
1827 { "oriu", OP(25), OP_MASK
, POWER
, { RA
, RS
, UI
} },
1829 { "xori", OP(26), OP_MASK
, PPC
, { RA
, RS
, UI
} },
1830 { "xoril", OP(26), OP_MASK
, POWER
, { RA
, RS
, UI
} },
1832 { "xoris", OP(27), OP_MASK
, PPC
, { RA
, RS
, UI
} },
1833 { "xoriu", OP(27), OP_MASK
, POWER
, { RA
, RS
, UI
} },
1835 { "andi.", OP(28), OP_MASK
, PPC
, { RA
, RS
, UI
} },
1836 { "andil.", OP(28), OP_MASK
, POWER
, { RA
, RS
, UI
} },
1838 { "andis.", OP(29), OP_MASK
, PPC
, { RA
, RS
, UI
} },
1839 { "andiu.", OP(29), OP_MASK
, POWER
, { RA
, RS
, UI
} },
1841 { "rotldi", MD(30,0,0), MDMB_MASK
, PPC
|B64
, { RA
, RS
, SH6
} },
1842 { "clrldi", MD(30,0,0), MDSH_MASK
, PPC
|B64
, { RA
, RS
, MB6
} },
1843 { "rldicl", MD(30,0,0), MD_MASK
, PPC
|B64
, { RA
, RS
, SH6
, MB6
} },
1844 { "rotldi.", MD(30,0,1), MDMB_MASK
, PPC
|B64
, { RA
, RS
, SH6
} },
1845 { "clrldi.", MD(30,0,1), MDSH_MASK
, PPC
|B64
, { RA
, RS
, MB6
} },
1846 { "rldicl.", MD(30,0,1), MD_MASK
, PPC
|B64
, { RA
, RS
, SH6
, MB6
} },
1848 { "rldicr", MD(30,1,0), MD_MASK
, PPC
|B64
, { RA
, RS
, SH6
, ME6
} },
1849 { "rldicr.", MD(30,1,1), MD_MASK
, PPC
|B64
, { RA
, RS
, SH6
, ME6
} },
1851 { "rldic", MD(30,2,0), MD_MASK
, PPC
|B64
, { RA
, RS
, SH6
, MB6
} },
1852 { "rldic.", MD(30,2,1), MD_MASK
, PPC
|B64
, { RA
, RS
, SH6
, MB6
} },
1854 { "rldimi", MD(30,3,0), MD_MASK
, PPC
|B64
, { RA
, RS
, SH6
, MB6
} },
1855 { "rldimi.", MD(30,3,1), MD_MASK
, PPC
|B64
, { RA
, RS
, SH6
, MB6
} },
1857 { "rotld", MDS(30,8,0), MDSMB_MASK
, PPC
|B64
, { RA
, RS
, RB
} },
1858 { "rldcl", MDS(30,8,0), MDS_MASK
, PPC
|B64
, { RA
, RS
, RB
, MB6
} },
1859 { "rotld.", MDS(30,8,1), MDSMB_MASK
, PPC
|B64
, { RA
, RS
, RB
} },
1860 { "rldcl.", MDS(30,8,1), MDS_MASK
, PPC
|B64
, { RA
, RS
, RB
, MB6
} },
1862 { "rldcr", MDS(30,9,0), MDS_MASK
, PPC
|B64
, { RA
, RS
, RB
, ME6
} },
1863 { "rldcr.", MDS(30,9,1), MDS_MASK
, PPC
|B64
, { RA
, RS
, RB
, ME6
} },
1865 { "cmpw", XCMPL(31,0,0), XCMPL_MASK
, PPC
, { OBF
, RA
, RB
} },
1866 { "cmpd", XCMPL(31,0,1), XCMPL_MASK
, PPC
|B64
, { OBF
, RA
, RB
} },
1867 { "cmp", X(31,0), XCMP_MASK
, PPC
, { BF
, L
, RA
, RB
} },
1868 { "cmp", X(31,0), XCMPL_MASK
, POWER
, { BF
, RA
, RB
} },
1870 { "twlgt", XTO(31,4,TOLGT
), XTO_MASK
, PPC
, { RA
, RB
} },
1871 { "tlgt", XTO(31,4,TOLGT
), XTO_MASK
, POWER
, { RA
, RB
} },
1872 { "twllt", XTO(31,4,TOLLT
), XTO_MASK
, PPC
, { RA
, RB
} },
1873 { "tllt", XTO(31,4,TOLLT
), XTO_MASK
, POWER
, { RA
, RB
} },
1874 { "tweq", XTO(31,4,TOEQ
), XTO_MASK
, PPC
, { RA
, RB
} },
1875 { "teq", XTO(31,4,TOEQ
), XTO_MASK
, POWER
, { RA
, RB
} },
1876 { "twlge", XTO(31,4,TOLGE
), XTO_MASK
, PPC
, { RA
, RB
} },
1877 { "tlge", XTO(31,4,TOLGE
), XTO_MASK
, POWER
, { RA
, RB
} },
1878 { "twlnl", XTO(31,4,TOLNL
), XTO_MASK
, PPC
, { RA
, RB
} },
1879 { "tlnl", XTO(31,4,TOLNL
), XTO_MASK
, POWER
, { RA
, RB
} },
1880 { "twlle", XTO(31,4,TOLLE
), XTO_MASK
, PPC
, { RA
, RB
} },
1881 { "tlle", XTO(31,4,TOLLE
), XTO_MASK
, POWER
, { RA
, RB
} },
1882 { "twlng", XTO(31,4,TOLNG
), XTO_MASK
, PPC
, { RA
, RB
} },
1883 { "tlng", XTO(31,4,TOLNG
), XTO_MASK
, POWER
, { RA
, RB
} },
1884 { "twgt", XTO(31,4,TOGT
), XTO_MASK
, PPC
, { RA
, RB
} },
1885 { "tgt", XTO(31,4,TOGT
), XTO_MASK
, POWER
, { RA
, RB
} },
1886 { "twge", XTO(31,4,TOGE
), XTO_MASK
, PPC
, { RA
, RB
} },
1887 { "tge", XTO(31,4,TOGE
), XTO_MASK
, POWER
, { RA
, RB
} },
1888 { "twnl", XTO(31,4,TONL
), XTO_MASK
, PPC
, { RA
, RB
} },
1889 { "tnl", XTO(31,4,TONL
), XTO_MASK
, POWER
, { RA
, RB
} },
1890 { "twlt", XTO(31,4,TOLT
), XTO_MASK
, PPC
, { RA
, RB
} },
1891 { "tlt", XTO(31,4,TOLT
), XTO_MASK
, POWER
, { RA
, RB
} },
1892 { "twle", XTO(31,4,TOLE
), XTO_MASK
, PPC
, { RA
, RB
} },
1893 { "tle", XTO(31,4,TOLE
), XTO_MASK
, POWER
, { RA
, RB
} },
1894 { "twng", XTO(31,4,TONG
), XTO_MASK
, PPC
, { RA
, RB
} },
1895 { "tng", XTO(31,4,TONG
), XTO_MASK
, POWER
, { RA
, RB
} },
1896 { "twne", XTO(31,4,TONE
), XTO_MASK
, PPC
, { RA
, RB
} },
1897 { "tne", XTO(31,4,TONE
), XTO_MASK
, POWER
, { RA
, RB
} },
1898 { "trap", XTO(31,4,TOU
), 0xffffffff, PPC
, { 0 } },
1899 { "tw", X(31,4), X_MASK
, PPC
, { TO
, RA
, RB
} },
1900 { "t", X(31,4), X_MASK
, POWER
, { TO
, RA
, RB
} },
1902 { "subfc", XO(31,8,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1903 { "sf", XO(31,8,0,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
1904 { "subc", XO(31,8,0,0), XO_MASK
, PPC
, { RT
, RB
, RA
} },
1905 { "subfc.", XO(31,8,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1906 { "sf.", XO(31,8,0,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
1907 { "subc.", XO(31,8,0,1), XO_MASK
, PPC
, { RT
, RB
, RA
} },
1908 { "subfco", XO(31,8,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1909 { "sfo", XO(31,8,1,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
1910 { "subco", XO(31,8,1,0), XO_MASK
, PPC
, { RT
, RB
, RA
} },
1911 { "subfco.", XO(31,8,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1912 { "sfo.", XO(31,8,1,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
1913 { "subco.", XO(31,8,1,1), XO_MASK
, PPC
, { RT
, RB
, RA
} },
1915 { "mulhdu", XO(31,9,0,0), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
1916 { "mulhdu.", XO(31,9,0,1), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
1918 { "addc", XO(31,10,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1919 { "a", XO(31,10,0,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
1920 { "addc.", XO(31,10,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1921 { "a.", XO(31,10,0,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
1922 { "addco", XO(31,10,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1923 { "ao", XO(31,10,1,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
1924 { "addco.", XO(31,10,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1925 { "ao.", XO(31,10,1,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
1927 { "mulhwu", XO(31,11,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1928 { "mulhwu.", XO(31,11,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1930 { "mfcr", X(31,19), XRARB_MASK
, POWER
|PPC
, { RT
} },
1932 { "lwarx", X(31,20), X_MASK
, PPC
, { RT
, RA
, RB
} },
1934 { "ldx", X(31,21), X_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
1936 { "lwzx", X(31,23), X_MASK
, PPC
, { RT
, RA
, RB
} },
1937 { "lx", X(31,23), X_MASK
, POWER
, { RT
, RA
, RB
} },
1939 { "slw", XRC(31,24,0), X_MASK
, PPC
, { RA
, RS
, RB
} },
1940 { "sl", XRC(31,24,0), X_MASK
, POWER
, { RA
, RS
, RB
} },
1941 { "slw.", XRC(31,24,1), X_MASK
, PPC
, { RA
, RS
, RB
} },
1942 { "sl.", XRC(31,24,1), X_MASK
, POWER
, { RA
, RS
, RB
} },
1944 { "cntlzw", XRC(31,26,0), XRB_MASK
, PPC
, { RA
, RS
} },
1945 { "cntlz", XRC(31,26,0), XRB_MASK
, POWER
, { RA
, RS
} },
1946 { "cntlzw.", XRC(31,26,1), XRB_MASK
, PPC
, { RA
, RS
} },
1947 { "cntlz.", XRC(31,26,1), XRB_MASK
, POWER
, { RA
, RS
} },
1949 { "sld", XRC(31,27,0), X_MASK
, PPC
|B64
, { RA
, RS
, RB
} },
1950 { "sld.", XRC(31,27,1), X_MASK
, PPC
|B64
, { RA
, RS
, RB
} },
1952 { "and", XRC(31,28,0), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
1953 { "and.", XRC(31,28,1), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
1955 { "maskg", XRC(31,29,0), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
1956 { "maskg.", XRC(31,29,1), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
1958 { "cmplw", XCMPL(31,32,0), XCMPL_MASK
, PPC
, { OBF
, RA
, RB
} },
1959 { "cmpld", XCMPL(31,32,1), XCMPL_MASK
, PPC
|B64
, { OBF
, RA
, RB
} },
1960 { "cmpl", X(31,32), XCMP_MASK
, PPC
, { BF
, L
, RA
, RB
} },
1961 { "cmpl", X(31,32), XCMPL_MASK
, POWER
, { BF
, RA
, RB
} },
1963 { "subf", XO(31,40,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1964 { "sub", XO(31,40,0,0), XO_MASK
, PPC
, { RT
, RB
, RA
} },
1965 { "subf.", XO(31,40,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1966 { "sub.", XO(31,40,0,1), XO_MASK
, PPC
, { RT
, RB
, RA
} },
1967 { "subfo", XO(31,40,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1968 { "subo", XO(31,40,1,0), XO_MASK
, PPC
, { RT
, RB
, RA
} },
1969 { "subfo.", XO(31,40,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1970 { "subo.", XO(31,40,1,1), XO_MASK
, PPC
, { RT
, RB
, RA
} },
1972 { "ldux", X(31,53), X_MASK
, PPC
|B64
, { RT
, RAL
, RB
} },
1974 { "dcbst", X(31,54), XRT_MASK
, PPC
, { RA
, RB
} },
1976 { "lwzux", X(31,55), X_MASK
, PPC
, { RT
, RAL
, RB
} },
1977 { "lux", X(31,55), X_MASK
, POWER
, { RT
, RA
, RB
} },
1979 { "cntlzd", XRC(31,58,0), XRB_MASK
, PPC
|B64
, { RA
, RS
} },
1980 { "cntlzd.", XRC(31,58,1), XRB_MASK
, PPC
|B64
, { RA
, RS
} },
1982 { "andc", XRC(31,60,0), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
1983 { "andc.", XRC(31,60,1), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
1985 { "tdlgt", XTO(31,68,TOLGT
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1986 { "tdllt", XTO(31,68,TOLLT
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1987 { "tdeq", XTO(31,68,TOEQ
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1988 { "tdlge", XTO(31,68,TOLGE
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1989 { "tdlnl", XTO(31,68,TOLNL
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1990 { "tdlle", XTO(31,68,TOLLE
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1991 { "tdlng", XTO(31,68,TOLNG
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1992 { "tdgt", XTO(31,68,TOGT
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1993 { "tdge", XTO(31,68,TOGE
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1994 { "tdnl", XTO(31,68,TONL
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1995 { "tdlt", XTO(31,68,TOLT
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1996 { "tdle", XTO(31,68,TOLE
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1997 { "tdng", XTO(31,68,TONG
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1998 { "tdne", XTO(31,68,TONE
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1999 { "td", X(31,68), X_MASK
, PPC
|B64
, { TO
, RA
, RB
} },
2001 { "mulhd", XO(31,73,0,0), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2002 { "mulhd.", XO(31,73,0,1), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2004 { "mulhw", XO(31,75,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2005 { "mulhw.", XO(31,75,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2007 { "mfmsr", X(31,83), XRARB_MASK
, PPC
|POWER
, { RT
} },
2009 { "ldarx", X(31,84), X_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2011 { "dcbf", X(31,86), XRT_MASK
, PPC
, { RA
, RB
} },
2013 { "lbzx", X(31,87), X_MASK
, PPC
|POWER
, { RT
, RA
, RB
} },
2015 { "neg", XO(31,104,0,0), XORB_MASK
, PPC
|POWER
, { RT
, RA
} },
2016 { "neg.", XO(31,104,0,1), XORB_MASK
, PPC
|POWER
, { RT
, RA
} },
2017 { "nego", XO(31,104,1,0), XORB_MASK
, PPC
|POWER
, { RT
, RA
} },
2018 { "nego.", XO(31,104,1,1), XORB_MASK
, PPC
|POWER
, { RT
, RA
} },
2020 { "mul", XO(31,107,0,0), XO_MASK
, POWER
|M601
, { RT
, RA
, RB
} },
2021 { "mul.", XO(31,107,0,1), XO_MASK
, POWER
|M601
, { RT
, RA
, RB
} },
2022 { "mulo", XO(31,107,1,0), XO_MASK
, POWER
|M601
, { RT
, RA
, RB
} },
2023 { "mulo.", XO(31,107,1,1), XO_MASK
, POWER
|M601
, { RT
, RA
, RB
} },
2025 { "clf", X(31,118), XRB_MASK
, POWER
, { RT
, RA
} },
2027 { "lbzux", X(31,119), X_MASK
, PPC
|POWER
, { RT
, RAL
, RB
} },
2029 { "not", XRC(31,124,0), X_MASK
, PPC
|POWER
, { RA
, RS
, RBS
} },
2030 { "nor", XRC(31,124,0), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2031 { "not.", XRC(31,124,1), X_MASK
, PPC
|POWER
, { RA
, RS
, RBS
} },
2032 { "nor.", XRC(31,124,1), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2034 { "subfe", XO(31,136,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2035 { "sfe", XO(31,136,0,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2036 { "subfe.", XO(31,136,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2037 { "sfe.", XO(31,136,0,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2038 { "subfeo", XO(31,136,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2039 { "sfeo", XO(31,136,1,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2040 { "subfeo.", XO(31,136,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2041 { "sfeo.", XO(31,136,1,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2043 { "adde", XO(31,138,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2044 { "ae", XO(31,138,0,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2045 { "adde.", XO(31,138,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2046 { "ae.", XO(31,138,0,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2047 { "addeo", XO(31,138,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2048 { "aeo", XO(31,138,1,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2049 { "addeo.", XO(31,138,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2050 { "aeo.", XO(31,138,1,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2052 { "mtcr", XFXM(31,144,0xff), XFXFXM_MASK
|FXM_MASK
, PPC
|POWER
, { RS
}},
2053 { "mtcrf", X(31,144), XFXFXM_MASK
, PPC
|POWER
, { FXM
, RS
} },
2055 { "mtmsr", X(31,146), XRARB_MASK
, PPC
|POWER
, { RS
} },
2056 { "mtmsrd", X(31,178), XRARB_MASK
, PPC
|POWER
, { RS
} },
2058 { "stdx", X(31,149), X_MASK
, PPC
|B64
, { RS
, RA
, RB
} },
2060 { "stwcx.", XRC(31,150,1), X_MASK
, PPC
, { RS
, RA
, RB
} },
2062 { "stwx", X(31,151), X_MASK
, PPC
, { RS
, RA
, RB
} },
2063 { "stx", X(31,151), X_MASK
, POWER
, { RS
, RA
, RB
} },
2065 { "slq", XRC(31,152,0), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2066 { "slq.", XRC(31,152,1), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2068 { "sle", XRC(31,153,0), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2069 { "sle.", XRC(31,153,1), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2071 { "stdux", X(31,181), X_MASK
, PPC
|B64
, { RS
, RAS
, RB
} },
2073 { "stwux", X(31,183), X_MASK
, PPC
, { RS
, RAS
, RB
} },
2074 { "stux", X(31,183), X_MASK
, POWER
, { RS
, RA
, RB
} },
2076 { "sliq", XRC(31,184,0), X_MASK
, POWER
|M601
, { RA
, RS
, SH
} },
2077 { "sliq.", XRC(31,184,1), X_MASK
, POWER
|M601
, { RA
, RS
, SH
} },
2079 { "subfze", XO(31,200,0,0), XORB_MASK
, PPC
, { RT
, RA
} },
2080 { "sfze", XO(31,200,0,0), XORB_MASK
, POWER
, { RT
, RA
} },
2081 { "subfze.", XO(31,200,0,1), XORB_MASK
, PPC
, { RT
, RA
} },
2082 { "sfze.", XO(31,200,0,1), XORB_MASK
, POWER
, { RT
, RA
} },
2083 { "subfzeo", XO(31,200,1,0), XORB_MASK
, PPC
, { RT
, RA
} },
2084 { "sfzeo", XO(31,200,1,0), XORB_MASK
, POWER
, { RT
, RA
} },
2085 { "subfzeo.",XO(31,200,1,1), XORB_MASK
, PPC
, { RT
, RA
} },
2086 { "sfzeo.", XO(31,200,1,1), XORB_MASK
, POWER
, { RT
, RA
} },
2088 { "addze", XO(31,202,0,0), XORB_MASK
, PPC
, { RT
, RA
} },
2089 { "aze", XO(31,202,0,0), XORB_MASK
, POWER
, { RT
, RA
} },
2090 { "addze.", XO(31,202,0,1), XORB_MASK
, PPC
, { RT
, RA
} },
2091 { "aze.", XO(31,202,0,1), XORB_MASK
, POWER
, { RT
, RA
} },
2092 { "addzeo", XO(31,202,1,0), XORB_MASK
, PPC
, { RT
, RA
} },
2093 { "azeo", XO(31,202,1,0), XORB_MASK
, POWER
, { RT
, RA
} },
2094 { "addzeo.", XO(31,202,1,1), XORB_MASK
, PPC
, { RT
, RA
} },
2095 { "azeo.", XO(31,202,1,1), XORB_MASK
, POWER
, { RT
, RA
} },
2097 { "mtsr", X(31,210), XRB_MASK
|(1<<20), PPC
|POWER
|B32
, { SR
, RS
} },
2099 { "stdcx.", XRC(31,214,1), X_MASK
, PPC
|B64
, { RS
, RA
, RB
} },
2101 { "stbx", X(31,215), X_MASK
, PPC
|POWER
, { RS
, RA
, RB
} },
2103 { "sllq", XRC(31,216,0), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2104 { "sllq.", XRC(31,216,1), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2106 { "sleq", XRC(31,217,0), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2107 { "sleq.", XRC(31,217,1), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2109 { "subfme", XO(31,232,0,0), XORB_MASK
, PPC
, { RT
, RA
} },
2110 { "sfme", XO(31,232,0,0), XORB_MASK
, POWER
, { RT
, RA
} },
2111 { "subfme.", XO(31,232,0,1), XORB_MASK
, PPC
, { RT
, RA
} },
2112 { "sfme.", XO(31,232,0,1), XORB_MASK
, POWER
, { RT
, RA
} },
2113 { "subfmeo", XO(31,232,1,0), XORB_MASK
, PPC
, { RT
, RA
} },
2114 { "sfmeo", XO(31,232,1,0), XORB_MASK
, POWER
, { RT
, RA
} },
2115 { "subfmeo.",XO(31,232,1,1), XORB_MASK
, PPC
, { RT
, RA
} },
2116 { "sfmeo.", XO(31,232,1,1), XORB_MASK
, POWER
, { RT
, RA
} },
2118 { "mulld", XO(31,233,0,0), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2119 { "mulld.", XO(31,233,0,1), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2120 { "mulldo", XO(31,233,1,0), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2121 { "mulldo.", XO(31,233,1,1), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2123 { "addme", XO(31,234,0,0), XORB_MASK
, PPC
, { RT
, RA
} },
2124 { "ame", XO(31,234,0,0), XORB_MASK
, POWER
, { RT
, RA
} },
2125 { "addme.", XO(31,234,0,1), XORB_MASK
, PPC
, { RT
, RA
} },
2126 { "ame.", XO(31,234,0,1), XORB_MASK
, POWER
, { RT
, RA
} },
2127 { "addmeo", XO(31,234,1,0), XORB_MASK
, PPC
, { RT
, RA
} },
2128 { "ameo", XO(31,234,1,0), XORB_MASK
, POWER
, { RT
, RA
} },
2129 { "addmeo.", XO(31,234,1,1), XORB_MASK
, PPC
, { RT
, RA
} },
2130 { "ameo.", XO(31,234,1,1), XORB_MASK
, POWER
, { RT
, RA
} },
2132 { "mullw", XO(31,235,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2133 { "muls", XO(31,235,0,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2134 { "mullw.", XO(31,235,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2135 { "muls.", XO(31,235,0,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2136 { "mullwo", XO(31,235,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2137 { "mulso", XO(31,235,1,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2138 { "mullwo.", XO(31,235,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2139 { "mulso.", XO(31,235,1,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2141 { "mtsrin", X(31,242), XRA_MASK
, PPC
|B32
, { RS
, RB
} },
2142 { "mtsri", X(31,242), XRA_MASK
, POWER
|B32
, { RS
, RB
} },
2144 { "dcbtst", X(31,246), XRT_MASK
, PPC
, { RA
, RB
} },
2146 { "stbux", X(31,247), X_MASK
, PPC
|POWER
, { RS
, RAS
, RB
} },
2148 { "slliq", XRC(31,248,0), X_MASK
, POWER
|M601
, { RA
, RS
, SH
} },
2149 { "slliq.", XRC(31,248,1), X_MASK
, POWER
|M601
, { RA
, RS
, SH
} },
2151 { "doz", XO(31,264,0,0), XO_MASK
, POWER
|M601
, { RT
, RA
, RB
} },
2152 { "doz.", XO(31,264,0,1), XO_MASK
, POWER
|M601
, { RT
, RA
, RB
} },
2153 { "dozo", XO(31,264,1,0), XO_MASK
, POWER
|M601
, { RT
, RA
, RB
} },
2154 { "dozo.", XO(31,264,1,1), XO_MASK
, POWER
|M601
, { RT
, RA
, RB
} },
2156 { "add", XO(31,266,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2157 { "cax", XO(31,266,0,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2158 { "add.", XO(31,266,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2159 { "cax.", XO(31,266,0,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2160 { "addo", XO(31,266,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2161 { "caxo", XO(31,266,1,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2162 { "addo.", XO(31,266,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2163 { "caxo.", XO(31,266,1,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2165 { "lscbx", XRC(31,277,0), X_MASK
, POWER
|M601
, { RT
, RA
, RB
} },
2166 { "lscbx.", XRC(31,277,1), X_MASK
, POWER
|M601
, { RT
, RA
, RB
} },
2168 { "dcbt", X(31,278), XRT_MASK
, PPC
, { RA
, RB
} },
2170 { "lhzx", X(31,279), X_MASK
, PPC
|POWER
, { RT
, RA
, RB
} },
2172 { "icbt", X(31,262), XRT_MASK
, PPC
, { RA
, RB
} },
2174 { "eqv", XRC(31,284,0), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2175 { "eqv.", XRC(31,284,1), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2177 { "tlbie", X(31,306), XRTRA_MASK
, PPC
, { RB
} },
2178 { "tlbi", X(31,306), XRTRA_MASK
, POWER
, { RB
} },
2180 { "eciwx", X(31,310), X_MASK
, PPC
, { RT
, RA
, RB
} },
2182 { "lhzux", X(31,311), X_MASK
, PPC
|POWER
, { RT
, RAL
, RB
} },
2184 { "xor", XRC(31,316,0), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2185 { "xor.", XRC(31,316,1), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2187 { "mfdcr", X(31,323), X_MASK
, PPC
, { RT
, SPR
} },
2189 { "div", XO(31,331,0,0), XO_MASK
, POWER
|M601
, { RT
, RA
, RB
} },
2190 { "div.", XO(31,331,0,1), XO_MASK
, POWER
|M601
, { RT
, RA
, RB
} },
2191 { "divo", XO(31,331,1,0), XO_MASK
, POWER
|M601
, { RT
, RA
, RB
} },
2192 { "divo.", XO(31,331,1,1), XO_MASK
, POWER
|M601
, { RT
, RA
, RB
} },
2194 { "mfmq", XSPR(31,339,0), XSPR_MASK
, POWER
|M601
, { RT
} },
2195 { "mfxer", XSPR(31,339,1), XSPR_MASK
, PPC
|POWER
, { RT
} },
2196 { "mfrtcu", XSPR(31,339,4), XSPR_MASK
, PPC
|POWER
, { RT
} },
2197 { "mfrtcl", XSPR(31,339,5), XSPR_MASK
, PPC
|POWER
, { RT
} },
2198 { "mfdec", XSPR(31,339,6), XSPR_MASK
, POWER
|M601
, { RT
} },
2199 { "mflr", XSPR(31,339,8), XSPR_MASK
, PPC
|POWER
, { RT
} },
2200 { "mfctr", XSPR(31,339,9), XSPR_MASK
, PPC
|POWER
, { RT
} },
2201 { "mftid", XSPR(31,339,17), XSPR_MASK
, POWER
, { RT
} },
2202 { "mfdsisr", XSPR(31,339,18), XSPR_MASK
, PPC
|POWER
, { RT
} },
2203 { "mfdar", XSPR(31,339,19), XSPR_MASK
, PPC
|POWER
, { RT
} },
2204 { "mfdec", XSPR(31,339,22), XSPR_MASK
, PPC
, { RT
} },
2205 { "mfsdr0", XSPR(31,339,24), XSPR_MASK
, POWER
, { RT
} },
2206 { "mfsdr1", XSPR(31,339,25), XSPR_MASK
, PPC
|POWER
, { RT
} },
2207 { "mfsrr0", XSPR(31,339,26), XSPR_MASK
, PPC
|POWER
, { RT
} },
2208 { "mfsrr1", XSPR(31,339,27), XSPR_MASK
, PPC
|POWER
, { RT
} },
2209 { "mfsprg", XSPR(31,339,272), XSPRG_MASK
, PPC
, { RT
, SPRG
} },
2210 { "mfasr", XSPR(31,339,280), XSPR_MASK
, PPC
|B64
, { RT
} },
2211 { "mfear", XSPR(31,339,282), XSPR_MASK
, PPC
, { RT
} },
2212 { "mfpvr", XSPR(31,339,287), XSPR_MASK
, PPC
, { RT
} },
2213 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK
, PPC
, { RT
, SPRBAT
} },
2214 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK
, PPC
, { RT
, SPRBAT
} },
2215 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK
, PPC
, { RT
, SPRBAT
} },
2216 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK
, PPC
, { RT
, SPRBAT
} },
2217 { "mfspr", X(31,339), X_MASK
, PPC
|POWER
, { RT
, SPR
} },
2219 { "lwax", X(31,341), X_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2221 { "lhax", X(31,343), X_MASK
, PPC
|POWER
, { RT
, RA
, RB
} },
2223 { "dccci", X(31,454), XRT_MASK
, PPC
, { RA
, RB
} },
2225 { "abs", XO(31,360,0,0), XORB_MASK
, POWER
|M601
, { RT
, RA
} },
2226 { "abs.", XO(31,360,0,1), XORB_MASK
, POWER
|M601
, { RT
, RA
} },
2227 { "abso", XO(31,360,1,0), XORB_MASK
, POWER
|M601
, { RT
, RA
} },
2228 { "abso.", XO(31,360,1,1), XORB_MASK
, POWER
|M601
, { RT
, RA
} },
2230 { "divs", XO(31,363,0,0), XO_MASK
, POWER
|M601
, { RT
, RA
, RB
} },
2231 { "divs.", XO(31,363,0,1), XO_MASK
, POWER
|M601
, { RT
, RA
, RB
} },
2232 { "divso", XO(31,363,1,0), XO_MASK
, POWER
|M601
, { RT
, RA
, RB
} },
2233 { "divso.", XO(31,363,1,1), XO_MASK
, POWER
|M601
, { RT
, RA
, RB
} },
2235 { "tlbia", X(31,370), 0xffffffff, PPC
, { 0 } },
2237 { "mftbu", XSPR(31,371,269), XSPR_MASK
, PPC
, { RT
} },
2238 { "mftb", X(31,371), X_MASK
, PPC
, { RT
, TBR
} },
2240 { "lwaux", X(31,373), X_MASK
, PPC
|B64
, { RT
, RAL
, RB
} },
2242 { "lhaux", X(31,375), X_MASK
, PPC
|POWER
, { RT
, RAL
, RB
} },
2244 { "sthx", X(31,407), X_MASK
, PPC
|POWER
, { RS
, RA
, RB
} },
2246 { "lfqx", X(31,791), X_MASK
, POWER2
, { FRT
, RA
, RB
} },
2248 { "lfqux", X(31,823), X_MASK
, POWER2
, { FRT
, RA
, RB
} },
2250 { "stfqx", X(31,919), X_MASK
, POWER2
, { FRS
, RA
, RB
} },
2252 { "stfqux", X(31,951), X_MASK
, POWER2
, { FRS
, RA
, RB
} },
2254 { "orc", XRC(31,412,0), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2255 { "orc.", XRC(31,412,1), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2257 { "sradi", XS(31,413,0), XS_MASK
, PPC
|B64
, { RA
, RS
, SH6
} },
2258 { "sradi.", XS(31,413,1), XS_MASK
, PPC
|B64
, { RA
, RS
, SH6
} },
2260 { "slbie", X(31,434), XRTRA_MASK
, PPC
|B64
, { RB
} },
2262 { "ecowx", X(31,438), X_MASK
, PPC
, { RT
, RA
, RB
} },
2264 { "sthux", X(31,439), X_MASK
, PPC
|POWER
, { RS
, RAS
, RB
} },
2266 { "mr", XRC(31,444,0), X_MASK
, PPC
|POWER
, { RA
, RS
, RBS
} },
2267 { "or", XRC(31,444,0), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2268 { "mr.", XRC(31,444,1), X_MASK
, PPC
|POWER
, { RA
, RS
, RBS
} },
2269 { "or.", XRC(31,444,1), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2271 { "mtdcr", X(31,451), X_MASK
, PPC
, { SPR
, RS
} },
2273 { "divdu", XO(31,457,0,0), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2274 { "divdu.", XO(31,457,0,1), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2275 { "divduo", XO(31,457,1,0), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2276 { "divduo.", XO(31,457,1,1), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2278 { "divwu", XO(31,459,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2279 { "divwu.", XO(31,459,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2280 { "divwuo", XO(31,459,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2281 { "divwuo.", XO(31,459,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2283 { "mtmq", XSPR(31,467,0), XSPR_MASK
, POWER
|M601
, { RS
} },
2284 { "mtxer", XSPR(31,467,1), XSPR_MASK
, PPC
|POWER
, { RS
} },
2285 { "mtlr", XSPR(31,467,8), XSPR_MASK
, PPC
|POWER
, { RS
} },
2286 { "mtctr", XSPR(31,467,9), XSPR_MASK
, PPC
|POWER
, { RS
} },
2287 { "mttid", XSPR(31,467,17), XSPR_MASK
, POWER
, { RS
} },
2288 { "mtdsisr", XSPR(31,467,18), XSPR_MASK
, PPC
|POWER
, { RS
} },
2289 { "mtdar", XSPR(31,467,19), XSPR_MASK
, PPC
|POWER
, { RS
} },
2290 { "mtrtcu", XSPR(31,467,20), XSPR_MASK
, PPC
|POWER
, { RS
} },
2291 { "mtrtcl", XSPR(31,467,21), XSPR_MASK
, PPC
|POWER
, { RS
} },
2292 { "mtdec", XSPR(31,467,22), XSPR_MASK
, PPC
|POWER
, { RS
} },
2293 { "mtsdr0", XSPR(31,467,24), XSPR_MASK
, POWER
, { RS
} },
2294 { "mtsdr1", XSPR(31,467,25), XSPR_MASK
, PPC
|POWER
, { RS
} },
2295 { "mtsrr0", XSPR(31,467,26), XSPR_MASK
, PPC
|POWER
, { RS
} },
2296 { "mtsrr1", XSPR(31,467,27), XSPR_MASK
, PPC
|POWER
, { RS
} },
2297 { "mtsprg", XSPR(31,467,272), XSPRG_MASK
, PPC
, { SPRG
, RS
} },
2298 { "mtasr", XSPR(31,467,280), XSPR_MASK
, PPC
|B64
, { RS
} },
2299 { "mtear", XSPR(31,467,282), XSPR_MASK
, PPC
, { RS
} },
2300 { "mttbl", XSPR(31,467,284), XSPR_MASK
, PPC
, { RS
} },
2301 { "mttbu", XSPR(31,467,285), XSPR_MASK
, PPC
, { RS
} },
2302 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK
, PPC
, { SPRBAT
, RS
} },
2303 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK
, PPC
, { SPRBAT
, RS
} },
2304 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK
, PPC
, { SPRBAT
, RS
} },
2305 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK
, PPC
, { SPRBAT
, RS
} },
2306 { "mtspr", X(31,467), X_MASK
, PPC
|POWER
, { SPR
, RS
} },
2308 { "dcbi", X(31,470), XRT_MASK
, PPC
, { RA
, RB
} },
2310 { "nand", XRC(31,476,0), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2311 { "nand.", XRC(31,476,1), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2313 { "nabs", XO(31,488,0,0), XORB_MASK
, POWER
|M601
, { RT
, RA
} },
2314 { "nabs.", XO(31,488,0,1), XORB_MASK
, POWER
|M601
, { RT
, RA
} },
2315 { "nabso", XO(31,488,1,0), XORB_MASK
, POWER
|M601
, { RT
, RA
} },
2316 { "nabso.", XO(31,488,1,1), XORB_MASK
, POWER
|M601
, { RT
, RA
} },
2318 { "divd", XO(31,489,0,0), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2319 { "divd.", XO(31,489,0,1), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2320 { "divdo", XO(31,489,1,0), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2321 { "divdo.", XO(31,489,1,1), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2323 { "divw", XO(31,491,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2324 { "divw.", XO(31,491,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2325 { "divwo", XO(31,491,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2326 { "divwo.", XO(31,491,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2328 { "slbia", X(31,498), 0xffffffff, PPC
|B64
, { 0 } },
2330 { "cli", X(31,502), XRB_MASK
, POWER
, { RT
, RA
} },
2332 { "mcrxr", X(31,512), XRARB_MASK
|(3<<21), PPC
|POWER
, { BF
} },
2334 { "clcs", X(31,531), XRB_MASK
, POWER
|M601
, { RT
, RA
} },
2336 { "lswx", X(31,533), X_MASK
, PPC
, { RT
, RA
, RB
} },
2337 { "lsx", X(31,533), X_MASK
, POWER
, { RT
, RA
, RB
} },
2339 { "lwbrx", X(31,534), X_MASK
, PPC
, { RT
, RA
, RB
} },
2340 { "lbrx", X(31,534), X_MASK
, POWER
, { RT
, RA
, RB
} },
2342 { "lfsx", X(31,535), X_MASK
, PPC
|POWER
, { FRT
, RA
, RB
} },
2344 { "srw", XRC(31,536,0), X_MASK
, PPC
, { RA
, RS
, RB
} },
2345 { "sr", XRC(31,536,0), X_MASK
, POWER
, { RA
, RS
, RB
} },
2346 { "srw.", XRC(31,536,1), X_MASK
, PPC
, { RA
, RS
, RB
} },
2347 { "sr.", XRC(31,536,1), X_MASK
, POWER
, { RA
, RS
, RB
} },
2349 { "rrib", XRC(31,537,0), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2350 { "rrib.", XRC(31,537,1), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2352 { "srd", XRC(31,539,0), X_MASK
, PPC
|B64
, { RA
, RS
, RB
} },
2353 { "srd.", XRC(31,539,1), X_MASK
, PPC
|B64
, { RA
, RS
, RB
} },
2355 { "maskir", XRC(31,541,0), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2356 { "maskir.", XRC(31,541,1), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2358 { "tlbsync", X(31,566), 0xffffffff, PPC
, { 0 } },
2360 { "lfsux", X(31,567), X_MASK
, PPC
|POWER
, { FRT
, RAS
, RB
} },
2362 { "mfsr", X(31,595), XRB_MASK
|(1<<20), PPC
|POWER
|B32
, { RT
, SR
} },
2364 { "lswi", X(31,597), X_MASK
, PPC
, { RT
, RA
, NB
} },
2365 { "lsi", X(31,597), X_MASK
, POWER
, { RT
, RA
, NB
} },
2367 { "sync", X(31,598), 0xffffffff, PPC
, { 0 } },
2368 { "dcs", X(31,598), 0xffffffff, POWER
, { 0 } },
2370 { "lfdx", X(31,599), X_MASK
, PPC
|POWER
, { FRT
, RA
, RB
} },
2372 { "mfsri", X(31,627), X_MASK
, POWER
, { RT
, RA
, RB
} },
2374 { "dclst", X(31,630), XRB_MASK
, POWER
, { RS
, RA
} },
2376 { "lfdux", X(31,631), X_MASK
, PPC
|POWER
, { FRT
, RAS
, RB
} },
2378 { "mfsrin", X(31,659), XRA_MASK
, PPC
|B32
, { RT
, RB
} },
2380 { "stswx", X(31,661), X_MASK
, PPC
, { RS
, RA
, RB
} },
2381 { "stsx", X(31,661), X_MASK
, POWER
, { RS
, RA
, RB
} },
2383 { "stwbrx", X(31,662), X_MASK
, PPC
, { RS
, RA
, RB
} },
2384 { "stbrx", X(31,662), X_MASK
, POWER
, { RS
, RA
, RB
} },
2386 { "stfsx", X(31,663), X_MASK
, PPC
|POWER
, { FRS
, RA
, RB
} },
2388 { "srq", XRC(31,664,0), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2389 { "srq.", XRC(31,664,1), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2391 { "sre", XRC(31,665,0), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2392 { "sre.", XRC(31,665,1), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2394 { "stfsux", X(31,695), X_MASK
, PPC
|POWER
, { FRS
, RAS
, RB
} },
2396 { "sriq", XRC(31,696,0), X_MASK
, POWER
|M601
, { RA
, RS
, SH
} },
2397 { "sriq.", XRC(31,696,1), X_MASK
, POWER
|M601
, { RA
, RS
, SH
} },
2399 { "stswi", X(31,725), X_MASK
, PPC
, { RS
, RA
, NB
} },
2400 { "stsi", X(31,725), X_MASK
, POWER
, { RS
, RA
, NB
} },
2402 { "stfdx", X(31,727), X_MASK
, PPC
|POWER
, { FRS
, RA
, RB
} },
2404 { "srlq", XRC(31,728,0), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2405 { "srlq.", XRC(31,728,1), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2407 { "sreq", XRC(31,729,0), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2408 { "sreq.", XRC(31,729,1), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2410 { "stfdux", X(31,759), X_MASK
, PPC
|POWER
, { FRS
, RAS
, RB
} },
2412 { "srliq", XRC(31,760,0), X_MASK
, POWER
|M601
, { RA
, RS
, SH
} },
2413 { "srliq.", XRC(31,760,1), X_MASK
, POWER
|M601
, { RA
, RS
, SH
} },
2415 { "lhbrx", X(31,790), X_MASK
, PPC
|POWER
, { RT
, RA
, RB
} },
2417 { "sraw", XRC(31,792,0), X_MASK
, PPC
, { RA
, RS
, RB
} },
2418 { "sra", XRC(31,792,0), X_MASK
, POWER
, { RA
, RS
, RB
} },
2419 { "sraw.", XRC(31,792,1), X_MASK
, PPC
, { RA
, RS
, RB
} },
2420 { "sra.", XRC(31,792,1), X_MASK
, POWER
, { RA
, RS
, RB
} },
2422 { "srad", XRC(31,794,0), X_MASK
, PPC
|B64
, { RA
, RS
, RB
} },
2423 { "srad.", XRC(31,794,1), X_MASK
, PPC
|B64
, { RA
, RS
, RB
} },
2425 { "rac", X(31,818), X_MASK
, POWER
, { RT
, RA
, RB
} },
2427 { "srawi", XRC(31,824,0), X_MASK
, PPC
, { RA
, RS
, SH
} },
2428 { "srai", XRC(31,824,0), X_MASK
, POWER
, { RA
, RS
, SH
} },
2429 { "srawi.", XRC(31,824,1), X_MASK
, PPC
, { RA
, RS
, SH
} },
2430 { "srai.", XRC(31,824,1), X_MASK
, POWER
, { RA
, RS
, SH
} },
2432 { "eieio", X(31,854), 0xffffffff, PPC
, { 0 } },
2434 { "sthbrx", X(31,918), X_MASK
, PPC
|POWER
, { RS
, RA
, RB
} },
2436 { "sraq", XRC(31,920,0), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2437 { "sraq.", XRC(31,920,1), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2439 { "srea", XRC(31,921,0), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2440 { "srea.", XRC(31,921,1), X_MASK
, POWER
|M601
, { RA
, RS
, RB
} },
2442 { "extsh", XRC(31,922,0), XRB_MASK
, PPC
, { RA
, RS
} },
2443 { "exts", XRC(31,922,0), XRB_MASK
, POWER
, { RA
, RS
} },
2444 { "extsh.", XRC(31,922,1), XRB_MASK
, PPC
, { RA
, RS
} },
2445 { "exts.", XRC(31,922,1), XRB_MASK
, POWER
, { RA
, RS
} },
2447 { "sraiq", XRC(31,952,0), X_MASK
, POWER
|M601
, { RA
, RS
, SH
} },
2448 { "sraiq.", XRC(31,952,1), X_MASK
, POWER
|M601
, { RA
, RS
, SH
} },
2450 { "extsb", XRC(31,954,0), XRB_MASK
, PPC
, { RA
, RS
} },
2451 { "extsb.", XRC(31,954,1), XRB_MASK
, PPC
, { RA
, RS
} },
2453 { "iccci", X(31,966), XRT_MASK
, PPC
, { RA
, RB
} },
2455 { "icbi", X(31,982), XRT_MASK
, PPC
, { RA
, RB
} },
2457 { "stfiwx", X(31,983), X_MASK
, PPC
, { FRS
, RA
, RB
} },
2459 { "extsw", XRC(31,986,0), XRB_MASK
, PPC
, { RA
, RS
} },
2460 { "extsw.", XRC(31,986,1), XRB_MASK
, PPC
, { RA
, RS
} },
2462 { "dcbz", X(31,1014), XRT_MASK
, PPC
, { RA
, RB
} },
2463 { "dclz", X(31,1014), XRT_MASK
, PPC
, { RA
, RB
} },
2465 { "lwz", OP(32), OP_MASK
, PPC
, { RT
, D
, RA
} },
2466 { "l", OP(32), OP_MASK
, POWER
, { RT
, D
, RA
} },
2468 { "lwzu", OP(33), OP_MASK
, PPC
, { RT
, D
, RAL
} },
2469 { "lu", OP(33), OP_MASK
, POWER
, { RT
, D
, RA
} },
2471 { "lbz", OP(34), OP_MASK
, PPC
|POWER
, { RT
, D
, RA
} },
2473 { "lbzu", OP(35), OP_MASK
, PPC
|POWER
, { RT
, D
, RAL
} },
2475 { "stw", OP(36), OP_MASK
, PPC
, { RS
, D
, RA
} },
2476 { "st", OP(36), OP_MASK
, POWER
, { RS
, D
, RA
} },
2478 { "stwu", OP(37), OP_MASK
, PPC
, { RS
, D
, RAS
} },
2479 { "stu", OP(37), OP_MASK
, POWER
, { RS
, D
, RA
} },
2481 { "stb", OP(38), OP_MASK
, PPC
|POWER
, { RS
, D
, RA
} },
2483 { "stbu", OP(39), OP_MASK
, PPC
|POWER
, { RS
, D
, RAS
} },
2485 { "lhz", OP(40), OP_MASK
, PPC
|POWER
, { RT
, D
, RA
} },
2487 { "lhzu", OP(41), OP_MASK
, PPC
|POWER
, { RT
, D
, RAL
} },
2489 { "lha", OP(42), OP_MASK
, PPC
|POWER
, { RT
, D
, RA
} },
2491 { "lhau", OP(43), OP_MASK
, PPC
|POWER
, { RT
, D
, RAL
} },
2493 { "sth", OP(44), OP_MASK
, PPC
|POWER
, { RS
, D
, RA
} },
2495 { "sthu", OP(45), OP_MASK
, PPC
|POWER
, { RS
, D
, RAS
} },
2497 { "lmw", OP(46), OP_MASK
, PPC
, { RT
, D
, RAM
} },
2498 { "lm", OP(46), OP_MASK
, POWER
, { RT
, D
, RA
} },
2500 { "stmw", OP(47), OP_MASK
, PPC
, { RS
, D
, RA
} },
2501 { "stm", OP(47), OP_MASK
, POWER
, { RS
, D
, RA
} },
2503 { "lfs", OP(48), OP_MASK
, PPC
|POWER
, { FRT
, D
, RA
} },
2505 { "lfsu", OP(49), OP_MASK
, PPC
|POWER
, { FRT
, D
, RAS
} },
2507 { "lfd", OP(50), OP_MASK
, PPC
|POWER
, { FRT
, D
, RA
} },
2509 { "lfdu", OP(51), OP_MASK
, PPC
|POWER
, { FRT
, D
, RAS
} },
2511 { "stfs", OP(52), OP_MASK
, PPC
|POWER
, { FRS
, D
, RA
} },
2513 { "stfsu", OP(53), OP_MASK
, PPC
|POWER
, { FRS
, D
, RAS
} },
2515 { "stfd", OP(54), OP_MASK
, PPC
|POWER
, { FRS
, D
, RA
} },
2517 { "stfdu", OP(55), OP_MASK
, PPC
|POWER
, { FRS
, D
, RAS
} },
2519 { "lfq", OP(56), OP_MASK
, POWER2
, { FRT
, D
, RA
} },
2521 { "lfqu", OP(57), OP_MASK
, POWER2
, { FRT
, D
, RA
} },
2523 { "ld", DSO(58,0), DS_MASK
, PPC
|B64
, { RT
, DS
, RA
} },
2525 { "ldu", DSO(58,1), DS_MASK
, PPC
|B64
, { RT
, DS
, RAL
} },
2527 { "lwa", DSO(58,2), DS_MASK
, PPC
|B64
, { RT
, DS
, RA
} },
2529 { "fdivs", A(59,18,0), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2530 { "fdivs.", A(59,18,1), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2532 { "fsubs", A(59,20,0), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2533 { "fsubs.", A(59,20,1), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2535 { "fadds", A(59,21,0), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2536 { "fadds.", A(59,21,1), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2538 { "fsqrts", A(59,22,0), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
2539 { "fsqrts.", A(59,22,1), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
2541 { "fres", A(59,24,0), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
2542 { "fres.", A(59,24,1), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
2544 { "fmuls", A(59,25,0), AFRB_MASK
, PPC
, { FRT
, FRA
, FRC
} },
2545 { "fmuls.", A(59,25,1), AFRB_MASK
, PPC
, { FRT
, FRA
, FRC
} },
2547 { "fmsubs", A(59,28,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2548 { "fmsubs.", A(59,28,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2550 { "fmadds", A(59,29,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2551 { "fmadds.", A(59,29,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2553 { "fnmsubs", A(59,30,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2554 { "fnmsubs.",A(59,30,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2556 { "fnmadds", A(59,31,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2557 { "fnmadds.",A(59,31,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2559 { "stfq", OP(60), OP_MASK
, POWER2
, { FRS
, D
, RA
} },
2561 { "stfqu", OP(61), OP_MASK
, POWER2
, { FRS
, D
, RA
} },
2563 { "std", DSO(62,0), DS_MASK
, PPC
|B64
, { RS
, DS
, RA
} },
2565 { "stdu", DSO(62,1), DS_MASK
, PPC
|B64
, { RS
, DS
, RAS
} },
2567 { "fcmpu", X(63,0), X_MASK
|(3<<21), PPC
|POWER
, { BF
, FRA
, FRB
} },
2569 { "frsp", XRC(63,12,0), XRA_MASK
, PPC
|POWER
, { FRT
, FRB
} },
2570 { "frsp.", XRC(63,12,1), XRA_MASK
, PPC
|POWER
, { FRT
, FRB
} },
2572 { "fctiw", XRC(63,14,0), XRA_MASK
, PPC
, { FRT
, FRB
} },
2573 { "fcir", XRC(63,14,0), XRA_MASK
, POWER2
, { FRT
, FRB
} },
2574 { "fctiw.", XRC(63,14,1), XRA_MASK
, PPC
, { FRT
, FRB
} },
2575 { "fcir.", XRC(63,14,1), XRA_MASK
, POWER2
, { FRT
, FRB
} },
2577 { "fctiwz", XRC(63,15,0), XRA_MASK
, PPC
, { FRT
, FRB
} },
2578 { "fcirz", XRC(63,15,0), XRA_MASK
, POWER2
, { FRT
, FRB
} },
2579 { "fctiwz.", XRC(63,15,1), XRA_MASK
, PPC
, { FRT
, FRB
} },
2580 { "fcirz.", XRC(63,15,1), XRA_MASK
, POWER2
, { FRT
, FRB
} },
2582 { "fdiv", A(63,18,0), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2583 { "fd", A(63,18,0), AFRC_MASK
, POWER
, { FRT
, FRA
, FRB
} },
2584 { "fdiv.", A(63,18,1), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2585 { "fd.", A(63,18,1), AFRC_MASK
, POWER
, { FRT
, FRA
, FRB
} },
2587 { "fsub", A(63,20,0), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2588 { "fs", A(63,20,0), AFRC_MASK
, POWER
, { FRT
, FRA
, FRB
} },
2589 { "fsub.", A(63,20,1), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2590 { "fs.", A(63,20,1), AFRC_MASK
, POWER
, { FRT
, FRA
, FRB
} },
2592 { "fadd", A(63,21,0), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2593 { "fa", A(63,21,0), AFRC_MASK
, POWER
, { FRT
, FRA
, FRB
} },
2594 { "fadd.", A(63,21,1), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2595 { "fa.", A(63,21,1), AFRC_MASK
, POWER
, { FRT
, FRA
, FRB
} },
2597 { "fsqrt", A(63,22,0), AFRAFRC_MASK
, PPC
|POWER2
, { FRT
, FRB
} },
2598 { "fsqrt.", A(63,22,1), AFRAFRC_MASK
, PPC
|POWER2
, { FRT
, FRB
} },
2600 { "fsel", A(63,23,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2601 { "fsel.", A(63,23,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2603 { "fmul", A(63,25,0), AFRB_MASK
, PPC
, { FRT
, FRA
, FRC
} },
2604 { "fm", A(63,25,0), AFRB_MASK
, POWER
, { FRT
, FRA
, FRC
} },
2605 { "fmul.", A(63,25,1), AFRB_MASK
, PPC
, { FRT
, FRA
, FRC
} },
2606 { "fm.", A(63,25,1), AFRB_MASK
, POWER
, { FRT
, FRA
, FRC
} },
2608 { "frsqrte", A(63,26,0), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
2609 { "frsqrte.",A(63,26,1), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
2611 { "fmsub", A(63,28,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2612 { "fms", A(63,28,0), A_MASK
, POWER
, { FRT
,FRA
,FRC
,FRB
} },
2613 { "fmsub.", A(63,28,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2614 { "fms.", A(63,28,1), A_MASK
, POWER
, { FRT
,FRA
,FRC
,FRB
} },
2616 { "fmadd", A(63,29,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2617 { "fma", A(63,29,0), A_MASK
, POWER
, { FRT
,FRA
,FRC
,FRB
} },
2618 { "fmadd.", A(63,29,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2619 { "fma.", A(63,29,1), A_MASK
, POWER
, { FRT
,FRA
,FRC
,FRB
} },
2621 { "fnmsub", A(63,30,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2622 { "fnms", A(63,30,0), A_MASK
, POWER
, { FRT
,FRA
,FRC
,FRB
} },
2623 { "fnmsub.", A(63,30,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2624 { "fnms.", A(63,30,1), A_MASK
, POWER
, { FRT
,FRA
,FRC
,FRB
} },
2626 { "fnmadd", A(63,31,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2627 { "fnma", A(63,31,0), A_MASK
, POWER
, { FRT
,FRA
,FRC
,FRB
} },
2628 { "fnmadd.", A(63,31,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2629 { "fnma.", A(63,31,1), A_MASK
, POWER
, { FRT
,FRA
,FRC
,FRB
} },
2631 { "fcmpo", X(63,30), X_MASK
|(3<<21), PPC
|POWER
, { BF
, FRA
, FRB
} },
2633 { "mtfsb1", XRC(63,38,0), XRARB_MASK
, PPC
|POWER
, { BT
} },
2634 { "mtfsb1.", XRC(63,38,1), XRARB_MASK
, PPC
|POWER
, { BT
} },
2636 { "fneg", XRC(63,40,0), XRA_MASK
, PPC
|POWER
, { FRT
, FRB
} },
2637 { "fneg.", XRC(63,40,1), XRA_MASK
, PPC
|POWER
, { FRT
, FRB
} },
2639 { "mcrfs", X(63,64), XRB_MASK
|(3<<21)|(3<<16), PPC
|POWER
, { BF
, BFA
} },
2641 { "mtfsb0", XRC(63,70,0), XRARB_MASK
, PPC
|POWER
, { BT
} },
2642 { "mtfsb0.", XRC(63,70,1), XRARB_MASK
, PPC
|POWER
, { BT
} },
2644 { "fmr", XRC(63,72,0), XRA_MASK
, PPC
|POWER
, { FRT
, FRB
} },
2645 { "fmr.", XRC(63,72,1), XRA_MASK
, PPC
|POWER
, { FRT
, FRB
} },
2647 { "mtfsfi", XRC(63,134,0), XRA_MASK
|(3<<21)|(1<<11), PPC
|POWER
, { BF
, U
} },
2648 { "mtfsfi.", XRC(63,134,1), XRA_MASK
|(3<<21)|(1<<11), PPC
|POWER
, { BF
, U
} },
2650 { "fnabs", XRC(63,136,0), XRA_MASK
, PPC
|POWER
, { FRT
, FRB
} },
2651 { "fnabs.", XRC(63,136,1), XRA_MASK
, PPC
|POWER
, { FRT
, FRB
} },
2653 { "fabs", XRC(63,264,0), XRA_MASK
, PPC
|POWER
, { FRT
, FRB
} },
2654 { "fabs.", XRC(63,264,1), XRA_MASK
, PPC
|POWER
, { FRT
, FRB
} },
2656 { "mffs", XRC(63,583,0), XRARB_MASK
, PPC
|POWER
, { FRT
} },
2657 { "mffs.", XRC(63,583,1), XRARB_MASK
, PPC
|POWER
, { FRT
} },
2659 { "mtfsf", XFL(63,711,0), XFL_MASK
, PPC
|POWER
, { FLM
, FRB
} },
2660 { "mtfsf.", XFL(63,711,1), XFL_MASK
, PPC
|POWER
, { FLM
, FRB
} },
2662 { "fctid", XRC(63,814,0), XRA_MASK
, PPC
|B64
, { FRT
, FRB
} },
2663 { "fctid.", XRC(63,814,1), XRA_MASK
, PPC
|B64
, { FRT
, FRB
} },
2665 { "fctidz", XRC(63,815,0), XRA_MASK
, PPC
|B64
, { FRT
, FRB
} },
2666 { "fctidz.", XRC(63,815,1), XRA_MASK
, PPC
|B64
, { FRT
, FRB
} },
2668 { "fcfid", XRC(63,846,0), XRA_MASK
, PPC
|B64
, { FRT
, FRB
} },
2669 { "fcfid.", XRC(63,846,1), XRA_MASK
, PPC
|B64
, { FRT
, FRB
} },
2673 const int powerpc_num_opcodes
=
2674 sizeof (powerpc_opcodes
) / sizeof (powerpc_opcodes
[0]);
2676 /* The macro table. This is only used by the assembler. */
2678 const struct powerpc_macro powerpc_macros
[] = {
2679 { "extldi", 4, PPC
|B64
, "rldicr %0,%1,%3,(%2)-1" },
2680 { "extldi.", 4, PPC
|B64
, "rldicr. %0,%1,%3,(%2)-1" },
2681 { "extrdi", 4, PPC
|B64
, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
2682 { "extrdi.", 4, PPC
|B64
, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
2683 { "insrdi", 4, PPC
|B64
, "rldimi %0,%1,64-((%2)+(%3)),%3" },
2684 { "insrdi.", 4, PPC
|B64
, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
2685 { "rotrdi", 3, PPC
|B64
, "rldicl %0,%1,64-(%2),0" },
2686 { "rotrdi.", 3, PPC
|B64
, "rldicl. %0,%1,64-(%2),0" },
2687 { "sldi", 3, PPC
|B64
, "rldicr %0,%1,%2,63-(%2)" },
2688 { "sldi.", 3, PPC
|B64
, "rldicr. %0,%1,%2,63-(%2)" },
2689 { "srdi", 3, PPC
|B64
, "rldicl %0,%1,64-(%2),%2" },
2690 { "srdi.", 3, PPC
|B64
, "rldicl. %0,%1,64-(%2),%2" },
2691 { "clrrdi", 3, PPC
|B64
, "rldicr %0,%1,0,63-(%2)" },
2692 { "clrrdi.", 3, PPC
|B64
, "rldicr. %0,%1,0,63-(%2)" },
2693 { "clrlsldi",4, PPC
|B64
, "rldic %0,%1,%3,(%2)-(%3)" },
2694 { "clrlsldi.",4, PPC
|B64
, "rldic. %0,%1,%3,(%2)-(%3)" },
2696 { "extlwi", 4, PPC
, "rlwinm %0,%1,%3,0,(%2)-1" },
2697 { "extlwi.", 4, PPC
, "rlwinm. %0,%1,%3,0,(%2)-1" },
2698 { "extrwi", 4, PPC
, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
2699 { "extrwi.", 4, PPC
, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
2700 { "inslwi", 4, PPC
, "rlwimi %0,%1,32-(%3),%3,(%2)+(%3)-1" },
2701 { "inslwi.", 4, PPC
, "rlwimi. %0,%1,32-(%3),%3,(%2)+(%3)-1" },
2702 { "insrwi", 4, PPC
, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
2703 { "insrwi.", 4, PPC
, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
2704 { "rotrwi", 3, PPC
, "rlwinm %0,%1,32-(%2),0,31" },
2705 { "rotrwi.", 3, PPC
, "rlwinm. %0,%1,32-(%2),0,31" },
2706 { "slwi", 3, PPC
, "rlwinm %0,%1,%2,0,31-(%2)" },
2707 { "sli", 3, POWER
, "rlinm %0,%1,%2,0,31-(%2)" },
2708 { "slwi.", 3, PPC
, "rlwinm. %0,%1,%2,0,31-(%2)" },
2709 { "sli.", 3, POWER
, "rlinm. %0,%1,%2,0,31-(%2)" },
2710 { "srwi", 3, PPC
, "rlwinm %0,%1,32-(%2),%2,31" },
2711 { "sri", 3, POWER
, "rlinm %0,%1,32-(%2),%2,31" },
2712 { "srwi.", 3, PPC
, "rlwinm. %0,%1,32-(%2),%2,31" },
2713 { "sri.", 3, POWER
, "rlinm. %0,%1,32-(%2),%2,31" },
2714 { "clrrwi", 3, PPC
, "rlwinm %0,%1,0,0,31-(%2)" },
2715 { "clrrwi.", 3, PPC
, "rlwinm. %0,%1,0,0,31-(%2)" },
2716 { "clrlslwi",4, PPC
, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
2717 { "clrlslwi.",4, PPC
, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
2721 const int powerpc_num_macros
=
2722 sizeof (powerpc_macros
) / sizeof (powerpc_macros
[0]);