arch/ia64/sn/io/machvec/pci.c

   1 /*
   2  *
   3  * SNI64 specific PCI support for SNI IO.
   4  *
   5  * This file is subject to the terms and conditions of the GNU General Public
   6  * License.  See the file "COPYING" in the main directory of this archive
   7  * for more details.
   8  *
   9  * Copyright (c) 1997, 1998, 2000-2003 Silicon Graphics, Inc.  All rights reserved.
  10  */
  11 #include <linux/init.h>
  12 #include <linux/types.h>
  13 #include <linux/config.h>
  14 #include <linux/pci.h>
  15 #include <asm/sn/types.h>
  16 #include <asm/sn/sgi.h>
  17 #include <asm/sn/io.h>
  18 #include <asm/sn/driver.h>
  19 #include <asm/sn/iograph.h>
  20 #include <asm/param.h>
  21 #include <asm/sn/pio.h>
  22 #include <asm/sn/xtalk/xwidget.h>
  23 #include <asm/sn/sn_private.h>
  24 #include <asm/sn/addrs.h>
  25 #include <asm/sn/invent.h>
  26 #include <asm/sn/hcl.h>
  27 #include <asm/sn/hcl_util.h>
  28 #include <asm/sn/pci/pciio.h>
  29 #include <asm/sn/pci/pcibr.h>
  30 #include <asm/sn/pci/pcibr_private.h>
  31 #include <asm/sn/pci/bridge.h>
  32
  33 #ifdef DEBUG_CONFIG
  34 #define DBG(x...) printk(x)
  35 #else
  36 #define DBG(x...)
  37 #endif
  38
  39
  40
  41 #ifdef CONFIG_PCI
  42
  43 extern vertex_hdl_t pci_bus_to_vertex(unsigned char);
  44 extern vertex_hdl_t devfn_to_vertex(unsigned char bus, unsigned char devfn);
  45
  46 int sn_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val)
  47 {
  48         unsigned long res = 0;
  49         vertex_hdl_t device_vertex;
  50
  51         device_vertex = devfn_to_vertex(bus->number, devfn);
  52         if (!device_vertex)
  53                 return PCIBIOS_DEVICE_NOT_FOUND;
  54         res = pciio_config_get(device_vertex, (unsigned) where, size);
  55         *val = (unsigned int) res;
  56         return PCIBIOS_SUCCESSFUL;
  57 }
  58
  59 int sn_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
  60 {
  61         vertex_hdl_t device_vertex;
  62
  63         device_vertex = devfn_to_vertex(bus->number, devfn);
  64         if (!device_vertex)
  65                 return PCIBIOS_DEVICE_NOT_FOUND;
  66         pciio_config_set( device_vertex, (unsigned)where, size, (uint64_t) val);
  67         return PCIBIOS_SUCCESSFUL;
  68 }
  69
  70 struct pci_ops sn_pci_ops = {
  71         .read = sn_read_config,
  72         .write = sn_write_config
  73 };
  74
  75 /*
  76  * sn_pci_find_bios - SNIA64 pci_find_bios() platform specific code.
  77  */
  78 void __init
  79 sn_pci_find_bios(void)
  80 {
  81         extern struct pci_ops *pci_root_ops;
  82         /*
  83          * Go initialize our IO Infrastructure ..
  84          */
  85         extern void sgi_master_io_infr_init(void);
  86
  87         sgi_master_io_infr_init();
  88
  89         /* sn_io_infrastructure_init(); */
  90         pci_root_ops = &sn_pci_ops;
  91 }
  92
  93 void
  94 pci_fixup_ioc3(struct pci_dev *d)
  95 {
  96         int             i;
  97         unsigned int    size;
  98
  99         /* IOC3 only decodes 0x20 bytes of the config space, reading
 100          * beyond that is relatively benign but writing beyond that
 101          * (especially the base address registers) will shut down the
 102          * pci bus...so avoid doing so.
 103          * NOTE: this means we can't program the intr_pin into the device,
 104          *       currently we hack this with special code in
 105          *       sgi_pci_intr_support()
 106          */
 107         DBG("pci_fixup_ioc3: Fixing base addresses for ioc3 device %s\n", d->slot_name);
 108
 109         /* I happen to know from the spec that the ioc3 needs only 0xfffff
 110          * The standard pci trick of writing ~0 to the baddr and seeing
 111          * what comes back doesn't work with the ioc3
 112          */
 113         size = 0xfffff;
 114         d->resource[0].end = (unsigned long) d->resource[0].start + (unsigned long) size;
 115
 116         /*
 117          * Zero out the resource structure .. because we did not go through
 118          * the normal PCI Infrastructure Init, garbbage are left in these
 119          * fileds.
 120          */
 121         for (i = 1; i <= PCI_ROM_RESOURCE; i++) {
 122                 d->resource[i].start = 0UL;
 123                 d->resource[i].end = 0UL;
 124                 d->resource[i].flags = 0UL;
 125         }
 126
 127         d->subsystem_vendor = 0;
 128         d->subsystem_device = 0;
 129
 130 }
 131
 132 #else
 133 void sn_pci_find_bios(void) {}
 134 void pci_fixup_ioc3(struct pci_dev *d) {}
 135 struct list_head pci_root_buses;
 136 struct list_head pci_root_buses;
 137 struct list_head pci_devices;
 138
 139 #endif /* CONFIG_PCI */