2 * pci.c - Low-Level PCI Access in IA-64
4 * Derived from bios32.c of i386 tree.
6 * Copyright (C) 2002 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * Bjorn Helgaas <bjorn_helgaas@hp.com>
10 * Note: Above list of copyright holders is incomplete...
12 #include <linux/config.h>
14 #include <linux/acpi.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/smp_lock.h>
22 #include <linux/spinlock.h>
24 #include <asm/machvec.h>
26 #include <asm/segment.h>
27 #include <asm/system.h>
43 #define DBG(x...) printk(x)
48 struct pci_fixup pcibios_fixups
[1];
51 * Low-level SAL-based PCI configuration access functions. Note that SAL
52 * calls are already serialized (via sal_lock), so we don't need another
53 * synchronization mechanism here.
56 #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \
57 ((u64)(seg << 24) | (u64)(bus << 16) | \
58 (u64)(devfn << 8) | (u64)(reg))
62 pci_sal_read (int seg
, int bus
, int devfn
, int reg
, int len
, u32
*value
)
67 if (!value
|| (seg
> 255) || (bus
> 255) || (devfn
> 255) || (reg
> 255))
70 result
= ia64_sal_pci_config_read(PCI_SAL_ADDRESS(seg
, bus
, devfn
, reg
), len
, &data
);
78 pci_sal_write (int seg
, int bus
, int devfn
, int reg
, int len
, u32 value
)
80 if ((seg
> 255) || (bus
> 255) || (devfn
> 255) || (reg
> 255))
83 return ia64_sal_pci_config_write(PCI_SAL_ADDRESS(seg
, bus
, devfn
, reg
), len
, value
);
86 struct pci_raw_ops pci_sal_ops
= {
88 .write
= pci_sal_write
91 struct pci_raw_ops
*raw_pci_ops
= &pci_sal_ops
; /* default to SAL */
95 pci_read (struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32
*value
)
97 return raw_pci_ops
->read(pci_domain_nr(bus
), bus
->number
,
98 devfn
, where
, size
, value
);
102 pci_write (struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32 value
)
104 return raw_pci_ops
->write(pci_domain_nr(bus
), bus
->number
,
105 devfn
, where
, size
, value
);
108 static struct pci_ops pci_root_ops
= {
116 if (!acpi_pci_irq_init())
117 printk(KERN_INFO
"PCI: Using ACPI for IRQ routing\n");
119 printk(KERN_WARNING
"PCI: Invalid ACPI-PCI IRQ routing table\n");
123 subsys_initcall(pci_acpi_init
);
125 /* Called by ACPI when it finds a new root bus. */
127 static struct pci_controller
*
128 alloc_pci_controller (int seg
)
130 struct pci_controller
*controller
;
132 controller
= kmalloc(sizeof(*controller
), GFP_KERNEL
);
136 memset(controller
, 0, sizeof(*controller
));
137 controller
->segment
= seg
;
141 static struct pci_bus
*
142 scan_root_bus (int bus
, struct pci_ops
*ops
, void *sysdata
)
147 * We know this is a new root bus we haven't seen before, so
148 * scan it, even if we've seen the same bus number in a different
151 b
= kmalloc(sizeof(*b
), GFP_KERNEL
);
155 memset(b
, 0, sizeof(*b
));
156 INIT_LIST_HEAD(&b
->children
);
157 INIT_LIST_HEAD(&b
->devices
);
159 list_add_tail(&b
->node
, &pci_root_buses
);
161 b
->number
= b
->secondary
= bus
;
162 b
->resource
[0] = &ioport_resource
;
163 b
->resource
[1] = &iomem_resource
;
165 b
->sysdata
= sysdata
;
167 b
->subordinate
= pci_do_scan_bus(b
);
173 alloc_resource (char *name
, struct resource
*root
, unsigned long start
, unsigned long end
, unsigned long flags
)
175 struct resource
*res
;
177 res
= kmalloc(sizeof(*res
), GFP_KERNEL
);
181 memset(res
, 0, sizeof(*res
));
187 if (request_resource(root
, res
))
194 add_io_space (struct acpi_resource_address64
*addr
)
200 if (addr
->address_translation_offset
== 0)
201 return IO_SPACE_BASE(0); /* part of legacy IO space */
203 if (addr
->attribute
.io
.translation_attribute
== ACPI_SPARSE_TRANSLATION
)
206 offset
= (u64
) ioremap(addr
->address_translation_offset
, 0);
207 for (i
= 0; i
< num_io_spaces
; i
++)
208 if (io_space
[i
].mmio_base
== offset
&&
209 io_space
[i
].sparse
== sparse
)
210 return IO_SPACE_BASE(i
);
212 if (num_io_spaces
== MAX_IO_SPACES
) {
213 printk("Too many IO port spaces\n");
218 io_space
[i
].mmio_base
= offset
;
219 io_space
[i
].sparse
= sparse
;
221 return IO_SPACE_BASE(i
);
225 count_window (struct acpi_resource
*resource
, void *data
)
227 unsigned int *windows
= (unsigned int *) data
;
228 struct acpi_resource_address64 addr
;
231 status
= acpi_resource_to_address64(resource
, &addr
);
232 if (ACPI_SUCCESS(status
))
233 if (addr
.resource_type
== ACPI_MEMORY_RANGE
||
234 addr
.resource_type
== ACPI_IO_RANGE
)
240 struct pci_root_info
{
241 struct pci_controller
*controller
;
246 add_window (struct acpi_resource
*res
, void *data
)
248 struct pci_root_info
*info
= (struct pci_root_info
*) data
;
249 struct pci_window
*window
;
250 struct acpi_resource_address64 addr
;
252 unsigned long flags
, offset
= 0;
253 struct resource
*root
;
255 status
= acpi_resource_to_address64(res
, &addr
);
256 if (ACPI_SUCCESS(status
)) {
257 if (addr
.resource_type
== ACPI_MEMORY_RANGE
) {
258 flags
= IORESOURCE_MEM
;
259 root
= &iomem_resource
;
260 offset
= addr
.address_translation_offset
;
261 } else if (addr
.resource_type
== ACPI_IO_RANGE
) {
262 flags
= IORESOURCE_IO
;
263 root
= &ioport_resource
;
264 offset
= add_io_space(&addr
);
270 window
= &info
->controller
->window
[info
->controller
->windows
++];
271 window
->resource
.flags
|= flags
;
272 window
->resource
.start
= addr
.min_address_range
;
273 window
->resource
.end
= addr
.max_address_range
;
274 window
->offset
= offset
;
276 if (alloc_resource(info
->name
, root
, addr
.min_address_range
+ offset
,
277 addr
.max_address_range
+ offset
, flags
))
278 printk(KERN_ERR
"alloc 0x%lx-0x%lx from %s for %s failed\n",
279 addr
.min_address_range
+ offset
, addr
.max_address_range
+ offset
,
280 root
->name
, info
->name
);
287 pci_acpi_scan_root (struct acpi_device
*device
, int domain
, int bus
)
289 struct pci_root_info info
;
290 struct pci_controller
*controller
;
291 unsigned int windows
= 0;
294 printk("PCI: Probing PCI hardware on bus (%04x:%02x)\n", domain
, bus
);
295 controller
= alloc_pci_controller(domain
);
299 controller
->acpi_handle
= device
->handle
;
301 acpi_walk_resources(device
->handle
, METHOD_NAME__CRS
, count_window
, &windows
);
302 controller
->window
= kmalloc(sizeof(*controller
->window
) * windows
, GFP_KERNEL
);
303 if (!controller
->window
)
306 name
= kmalloc(16, GFP_KERNEL
);
310 sprintf(name
, "PCI Bus %04x:%02x", domain
, bus
);
311 info
.controller
= controller
;
313 acpi_walk_resources(device
->handle
, METHOD_NAME__CRS
, add_window
, &info
);
315 return scan_root_bus(bus
, &pci_root_ops
, controller
);
318 kfree(controller
->window
);
326 pcibios_fixup_device_resources (struct pci_dev
*dev
, struct pci_bus
*bus
)
328 struct pci_controller
*controller
= PCI_CONTROLLER(dev
);
329 struct pci_window
*window
;
332 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
333 if (!dev
->resource
[i
].start
)
336 #define contains(win, res) ((res)->start >= (win)->start && \
337 (res)->end <= (win)->end)
339 for (j
= 0; j
< controller
->windows
; j
++) {
340 window
= &controller
->window
[j
];
341 if (((dev
->resource
[i
].flags
& IORESOURCE_MEM
&&
342 window
->resource
.flags
& IORESOURCE_MEM
) ||
343 (dev
->resource
[i
].flags
& IORESOURCE_IO
&&
344 window
->resource
.flags
& IORESOURCE_IO
)) &&
345 contains(&window
->resource
, &dev
->resource
[i
])) {
346 dev
->resource
[i
].start
+= window
->offset
;
347 dev
->resource
[i
].end
+= window
->offset
;
354 * Called after each bus is probed, but before its children are examined.
357 pcibios_fixup_bus (struct pci_bus
*b
)
359 struct list_head
*ln
;
361 for (ln
= b
->devices
.next
; ln
!= &b
->devices
; ln
= ln
->next
)
362 pcibios_fixup_device_resources(pci_dev_b(ln
), b
);
368 pcibios_update_irq (struct pci_dev
*dev
, int irq
)
370 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, irq
);
372 /* ??? FIXME -- record old value for shutdown. */
376 pcibios_enable_resources (struct pci_dev
*dev
, int mask
)
385 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
387 for (idx
=0; idx
<6; idx
++) {
388 /* Only set up the desired resources. */
389 if (!(mask
& (1 << idx
)))
392 r
= &dev
->resource
[idx
];
393 if (!r
->start
&& r
->end
) {
395 "PCI: Device %s not available because of resource collisions\n",
399 if (r
->flags
& IORESOURCE_IO
)
400 cmd
|= PCI_COMMAND_IO
;
401 if (r
->flags
& IORESOURCE_MEM
)
402 cmd
|= PCI_COMMAND_MEMORY
;
404 if (dev
->resource
[PCI_ROM_RESOURCE
].start
)
405 cmd
|= PCI_COMMAND_MEMORY
;
406 if (cmd
!= old_cmd
) {
407 printk("PCI: Enabling device %s (%04x -> %04x)\n", dev
->slot_name
, old_cmd
, cmd
);
408 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
414 pcibios_enable_device (struct pci_dev
*dev
, int mask
)
418 ret
= pcibios_enable_resources(dev
, mask
);
422 printk(KERN_INFO
"PCI: Found IRQ %d for device %s\n", dev
->irq
, dev
->slot_name
);
423 return acpi_pci_irq_enable(dev
);
427 pcibios_align_resource (void *data
, struct resource
*res
,
428 unsigned long size
, unsigned long align
)
433 * PCI BIOS setup, always defaults to SAL interface
436 pcibios_setup (char *str
)
442 pci_mmap_page_range (struct pci_dev
*dev
, struct vm_area_struct
*vma
,
443 enum pci_mmap_state mmap_state
, int write_combine
)
446 * I/O space cannot be accessed via normal processor loads and stores on this
449 if (mmap_state
== pci_mmap_io
)
451 * XXX we could relax this for I/O spaces for which ACPI indicates that
452 * the space is 1-to-1 mapped. But at the moment, we don't support
453 * multiple PCI address spaces and the legacy I/O space is not 1-to-1
454 * mapped, so this is moot.
459 * Leave vm_pgoff as-is, the PCI space address is the physical address on this
462 vma
->vm_flags
|= (VM_SHM
| VM_LOCKED
| VM_IO
);
465 vma
->vm_page_prot
= pgprot_writecombine(vma
->vm_page_prot
);
467 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
469 if (remap_page_range(vma
, vma
->vm_start
, vma
->vm_pgoff
<< PAGE_SHIFT
,
470 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
))
477 * pci_cacheline_size - determine cacheline size for PCI devices
480 * We want to use the line-size of the outer-most cache. We assume
481 * that this line-size is the same for all CPUs.
483 * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
485 * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
488 pci_cacheline_size (void)
490 u64 levels
, unique_caches
;
492 pal_cache_config_info_t cci
;
493 static u8 cacheline_size
;
496 return cacheline_size
;
498 status
= ia64_pal_cache_summary(&levels
, &unique_caches
);
500 printk(KERN_ERR
"%s: ia64_pal_cache_summary() failed (status=%ld)\n",
501 __FUNCTION__
, status
);
502 return SMP_CACHE_BYTES
;
505 status
= ia64_pal_cache_config_info(levels
- 1, /* cache_type (data_or_unified)= */ 2,
508 printk(KERN_ERR
"%s: ia64_pal_cache_config_info() failed (status=%ld)\n",
509 __FUNCTION__
, status
);
510 return SMP_CACHE_BYTES
;
512 cacheline_size
= 1 << cci
.pcci_line_size
;
513 return cacheline_size
;
517 * pcibios_prep_mwi - helper function for drivers/pci/pci.c:pci_set_mwi()
518 * @dev: the PCI device for which MWI is enabled
520 * For ia64, we can get the cacheline sizes from PAL.
522 * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
525 pcibios_prep_mwi (struct pci_dev
*dev
)
527 unsigned long desired_linesize
, current_linesize
;
531 desired_linesize
= pci_cacheline_size();
533 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &pci_linesize
);
534 current_linesize
= 4 * pci_linesize
;
535 if (desired_linesize
!= current_linesize
) {
536 printk(KERN_WARNING
"PCI: slot %s has incorrect PCI cache line size of %lu bytes,",
537 dev
->slot_name
, current_linesize
);
538 if (current_linesize
> desired_linesize
) {
539 printk(" expected %lu bytes instead\n", desired_linesize
);
542 printk(" correcting to %lu\n", desired_linesize
);
543 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, desired_linesize
/ 4);