arch/ia64/pci/pci.c

   1 /*
   2  * pci.c - Low-Level PCI Access in IA-64
   3  *
   4  * Derived from bios32.c of i386 tree.
   5  *
   6  * Copyright (C) 2002 Hewlett-Packard Co
   7  *      David Mosberger-Tang <davidm@hpl.hp.com>
   8  *      Bjorn Helgaas <bjorn_helgaas@hp.com>
   9  *
  10  * Note: Above list of copyright holders is incomplete...
  11  */
  12 #include <linux/config.h>
  13
  14 #include <linux/acpi.h>
  15 #include <linux/types.h>
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/init.h>
  19 #include <linux/ioport.h>
  20 #include <linux/slab.h>
  21 #include <linux/smp_lock.h>
  22 #include <linux/spinlock.h>
  23
  24 #include <asm/machvec.h>
  25 #include <asm/page.h>
  26 #include <asm/segment.h>
  27 #include <asm/system.h>
  28 #include <asm/io.h>
  29
  30 #include <asm/sal.h>
  31
  32
  33 #ifdef CONFIG_SMP
  34 # include <asm/smp.h>
  35 #endif
  36 #include <asm/irq.h>
  37
  38
  39 #undef DEBUG
  40 #define DEBUG
  41
  42 #ifdef DEBUG
  43 #define DBG(x...) printk(x)
  44 #else
  45 #define DBG(x...)
  46 #endif
  47
  48 struct pci_fixup pcibios_fixups[1];
  49
  50 /*
  51  * Low-level SAL-based PCI configuration access functions. Note that SAL
  52  * calls are already serialized (via sal_lock), so we don't need another
  53  * synchronization mechanism here.
  54  */
  55
  56 #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \
  57         ((u64)(seg << 24) | (u64)(bus << 16) | \
  58          (u64)(devfn << 8) | (u64)(reg))
  59
  60
  61 static int
  62 pci_sal_read (int seg, int bus, int devfn, int reg, int len, u32 *value)
  63 {
  64         int result = 0;
  65         u64 data = 0;
  66
  67         if (!value || (seg > 255) || (bus > 255) || (devfn > 255) || (reg > 255))
  68                 return -EINVAL;
  69
  70         result = ia64_sal_pci_config_read(PCI_SAL_ADDRESS(seg, bus, devfn, reg), len, &data);
  71
  72         *value = (u32) data;
  73
  74         return result;
  75 }
  76
  77 static int
  78 pci_sal_write (int seg, int bus, int devfn, int reg, int len, u32 value)
  79 {
  80         if ((seg > 255) || (bus > 255) || (devfn > 255) || (reg > 255))
  81                 return -EINVAL;
  82
  83         return ia64_sal_pci_config_write(PCI_SAL_ADDRESS(seg, bus, devfn, reg), len, value);
  84 }
  85
  86 struct pci_raw_ops pci_sal_ops = {
  87         .read =         pci_sal_read,
  88         .write =        pci_sal_write
  89 };
  90
  91 struct pci_raw_ops *raw_pci_ops = &pci_sal_ops; /* default to SAL */
  92
  93
  94 static int
  95 pci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
  96 {
  97         return raw_pci_ops->read(pci_domain_nr(bus), bus->number,
  98                         devfn, where, size, value);
  99 }
 100
 101 static int
 102 pci_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
 103 {
 104         return raw_pci_ops->write(pci_domain_nr(bus), bus->number,
 105                         devfn, where, size, value);
 106 }
 107
 108 static struct pci_ops pci_root_ops = {
 109         .read = pci_read,
 110         .write = pci_write,
 111 };
 112
 113 static int __init
 114 pci_acpi_init (void)
 115 {
 116         if (!acpi_pci_irq_init())
 117                 printk(KERN_INFO "PCI: Using ACPI for IRQ routing\n");
 118         else
 119                 printk(KERN_WARNING "PCI: Invalid ACPI-PCI IRQ routing table\n");
 120         return 0;
 121 }
 122
 123 subsys_initcall(pci_acpi_init);
 124
 125 /* Called by ACPI when it finds a new root bus.  */
 126
 127 static struct pci_controller *
 128 alloc_pci_controller (int seg)
 129 {
 130         struct pci_controller *controller;
 131
 132         controller = kmalloc(sizeof(*controller), GFP_KERNEL);
 133         if (!controller)
 134                 return NULL;
 135
 136         memset(controller, 0, sizeof(*controller));
 137         controller->segment = seg;
 138         return controller;
 139 }
 140
 141 static struct pci_bus *
 142 scan_root_bus (int bus, struct pci_ops *ops, void *sysdata)
 143 {
 144         struct pci_bus *b;
 145
 146         /*
 147          * We know this is a new root bus we haven't seen before, so
 148          * scan it, even if we've seen the same bus number in a different
 149          * segment.
 150          */
 151         b = kmalloc(sizeof(*b), GFP_KERNEL);
 152         if (!b)
 153                 return NULL;
 154
 155         memset(b, 0, sizeof(*b));
 156         INIT_LIST_HEAD(&b->children);
 157         INIT_LIST_HEAD(&b->devices);
 158
 159         list_add_tail(&b->node, &pci_root_buses);
 160
 161         b->number = b->secondary = bus;
 162         b->resource[0] = &ioport_resource;
 163         b->resource[1] = &iomem_resource;
 164
 165         b->sysdata = sysdata;
 166         b->ops = ops;
 167         b->subordinate = pci_do_scan_bus(b);
 168
 169         return b;
 170 }
 171
 172 static int
 173 alloc_resource (char *name, struct resource *root, unsigned long start, unsigned long end, unsigned long flags)
 174 {
 175         struct resource *res;
 176
 177         res = kmalloc(sizeof(*res), GFP_KERNEL);
 178         if (!res)
 179                 return -ENOMEM;
 180
 181         memset(res, 0, sizeof(*res));
 182         res->name = name;
 183         res->start = start;
 184         res->end = end;
 185         res->flags = flags;
 186
 187         if (request_resource(root, res))
 188                 return -EBUSY;
 189
 190         return 0;
 191 }
 192
 193 static u64
 194 add_io_space (struct acpi_resource_address64 *addr)
 195 {
 196         u64 offset;
 197         int sparse = 0;
 198         int i;
 199
 200         if (addr->address_translation_offset == 0)
 201                 return IO_SPACE_BASE(0);        /* part of legacy IO space */
 202
 203         if (addr->attribute.io.translation_attribute == ACPI_SPARSE_TRANSLATION)
 204                 sparse = 1;
 205
 206         offset = (u64) ioremap(addr->address_translation_offset, 0);
 207         for (i = 0; i < num_io_spaces; i++)
 208                 if (io_space[i].mmio_base == offset &&
 209                     io_space[i].sparse == sparse)
 210                         return IO_SPACE_BASE(i);
 211
 212         if (num_io_spaces == MAX_IO_SPACES) {
 213                 printk("Too many IO port spaces\n");
 214                 return ~0;
 215         }
 216
 217         i = num_io_spaces++;
 218         io_space[i].mmio_base = offset;
 219         io_space[i].sparse = sparse;
 220
 221         return IO_SPACE_BASE(i);
 222 }
 223
 224 static acpi_status
 225 count_window (struct acpi_resource *resource, void *data)
 226 {
 227         unsigned int *windows = (unsigned int *) data;
 228         struct acpi_resource_address64 addr;
 229         acpi_status status;
 230
 231         status = acpi_resource_to_address64(resource, &addr);
 232         if (ACPI_SUCCESS(status))
 233                 if (addr.resource_type == ACPI_MEMORY_RANGE ||
 234                     addr.resource_type == ACPI_IO_RANGE)
 235                         (*windows)++;
 236
 237         return AE_OK;
 238 }
 239
 240 struct pci_root_info {
 241         struct pci_controller *controller;
 242         char *name;
 243 };
 244
 245 static acpi_status
 246 add_window (struct acpi_resource *res, void *data)
 247 {
 248         struct pci_root_info *info = (struct pci_root_info *) data;
 249         struct pci_window *window;
 250         struct acpi_resource_address64 addr;
 251         acpi_status status;
 252         unsigned long flags, offset = 0;
 253         struct resource *root;
 254
 255         status = acpi_resource_to_address64(res, &addr);
 256         if (ACPI_SUCCESS(status)) {
 257                 if (addr.resource_type == ACPI_MEMORY_RANGE) {
 258                         flags = IORESOURCE_MEM;
 259                         root = &iomem_resource;
 260                         offset = addr.address_translation_offset;
 261                 } else if (addr.resource_type == ACPI_IO_RANGE) {
 262                         flags = IORESOURCE_IO;
 263                         root = &ioport_resource;
 264                         offset = add_io_space(&addr);
 265                         if (offset == ~0)
 266                                 return AE_OK;
 267                 } else
 268                         return AE_OK;
 269
 270                 window = &info->controller->window[info->controller->windows++];
 271                 window->resource.flags |= flags;
 272                 window->resource.start  = addr.min_address_range;
 273                 window->resource.end    = addr.max_address_range;
 274                 window->offset          = offset;
 275
 276                 if (alloc_resource(info->name, root, addr.min_address_range + offset,
 277                         addr.max_address_range + offset, flags))
 278                         printk(KERN_ERR "alloc 0x%lx-0x%lx from %s for %s failed\n",
 279                                 addr.min_address_range + offset, addr.max_address_range + offset,
 280                                 root->name, info->name);
 281         }
 282
 283         return AE_OK;
 284 }
 285
 286 struct pci_bus *
 287 pci_acpi_scan_root (struct acpi_device *device, int domain, int bus)
 288 {
 289         struct pci_root_info info;
 290         struct pci_controller *controller;
 291         unsigned int windows = 0;
 292         char *name;
 293
 294         printk("PCI: Probing PCI hardware on bus (%04x:%02x)\n", domain, bus);
 295         controller = alloc_pci_controller(domain);
 296         if (!controller)
 297                 goto out1;
 298
 299         controller->acpi_handle = device->handle;
 300
 301         acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window, &windows);
 302         controller->window = kmalloc(sizeof(*controller->window) * windows, GFP_KERNEL);
 303         if (!controller->window)
 304                 goto out2;
 305
 306         name = kmalloc(16, GFP_KERNEL);
 307         if (!name)
 308                 goto out3;
 309
 310         sprintf(name, "PCI Bus %04x:%02x", domain, bus);
 311         info.controller = controller;
 312         info.name = name;
 313         acpi_walk_resources(device->handle, METHOD_NAME__CRS, add_window, &info);
 314
 315         return scan_root_bus(bus, &pci_root_ops, controller);
 316
 317 out3:
 318         kfree(controller->window);
 319 out2:
 320         kfree(controller);
 321 out1:
 322         return NULL;
 323 }
 324
 325 void __init
 326 pcibios_fixup_device_resources (struct pci_dev *dev, struct pci_bus *bus)
 327 {
 328         struct pci_controller *controller = PCI_CONTROLLER(dev);
 329         struct pci_window *window;
 330         int i, j;
 331
 332         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 333                 if (!dev->resource[i].start)
 334                         continue;
 335
 336 #define contains(win, res)      ((res)->start >= (win)->start && \
 337                                  (res)->end   <= (win)->end)
 338
 339                 for (j = 0; j < controller->windows; j++) {
 340                         window = &controller->window[j];
 341                         if (((dev->resource[i].flags & IORESOURCE_MEM &&
 342                               window->resource.flags & IORESOURCE_MEM) ||
 343                              (dev->resource[i].flags & IORESOURCE_IO &&
 344                               window->resource.flags & IORESOURCE_IO)) &&
 345                             contains(&window->resource, &dev->resource[i])) {
 346                                 dev->resource[i].start += window->offset;
 347                                 dev->resource[i].end   += window->offset;
 348                         }
 349                 }
 350         }
 351 }
 352
 353 /*
 354  *  Called after each bus is probed, but before its children are examined.
 355  */
 356 void __devinit
 357 pcibios_fixup_bus (struct pci_bus *b)
 358 {
 359         struct list_head *ln;
 360
 361         for (ln = b->devices.next; ln != &b->devices; ln = ln->next)
 362                 pcibios_fixup_device_resources(pci_dev_b(ln), b);
 363
 364         return;
 365 }
 366
 367 void __devinit
 368 pcibios_update_irq (struct pci_dev *dev, int irq)
 369 {
 370         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 371
 372         /* ??? FIXME -- record old value for shutdown.  */
 373 }
 374
 375 static inline int
 376 pcibios_enable_resources (struct pci_dev *dev, int mask)
 377 {
 378         u16 cmd, old_cmd;
 379         int idx;
 380         struct resource *r;
 381
 382         if (!dev)
 383                 return -EINVAL;
 384
 385         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 386         old_cmd = cmd;
 387         for (idx=0; idx<6; idx++) {
 388                 /* Only set up the desired resources.  */
 389                 if (!(mask & (1 << idx)))
 390                         continue;
 391
 392                 r = &dev->resource[idx];
 393                 if (!r->start && r->end) {
 394                         printk(KERN_ERR
 395                                "PCI: Device %s not available because of resource collisions\n",
 396                                dev->slot_name);
 397                         return -EINVAL;
 398                 }
 399                 if (r->flags & IORESOURCE_IO)
 400                         cmd |= PCI_COMMAND_IO;
 401                 if (r->flags & IORESOURCE_MEM)
 402                         cmd |= PCI_COMMAND_MEMORY;
 403         }
 404         if (dev->resource[PCI_ROM_RESOURCE].start)
 405                 cmd |= PCI_COMMAND_MEMORY;
 406         if (cmd != old_cmd) {
 407                 printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
 408                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 409         }
 410         return 0;
 411 }
 412
 413 int
 414 pcibios_enable_device (struct pci_dev *dev, int mask)
 415 {
 416         int ret;
 417
 418         ret = pcibios_enable_resources(dev, mask);
 419         if (ret < 0)
 420                 return ret;
 421
 422         printk(KERN_INFO "PCI: Found IRQ %d for device %s\n", dev->irq, dev->slot_name);
 423         return acpi_pci_irq_enable(dev);
 424 }
 425
 426 void
 427 pcibios_align_resource (void *data, struct resource *res,
 428                         unsigned long size, unsigned long align)
 429 {
 430 }
 431
 432 /*
 433  * PCI BIOS setup, always defaults to SAL interface
 434  */
 435 char * __init
 436 pcibios_setup (char *str)
 437 {
 438         return NULL;
 439 }
 440
 441 int
 442 pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
 443                      enum pci_mmap_state mmap_state, int write_combine)
 444 {
 445         /*
 446          * I/O space cannot be accessed via normal processor loads and stores on this
 447          * platform.
 448          */
 449         if (mmap_state == pci_mmap_io)
 450                 /*
 451                  * XXX we could relax this for I/O spaces for which ACPI indicates that
 452                  * the space is 1-to-1 mapped.  But at the moment, we don't support
 453                  * multiple PCI address spaces and the legacy I/O space is not 1-to-1
 454                  * mapped, so this is moot.
 455                  */
 456                 return -EINVAL;
 457
 458         /*
 459          * Leave vm_pgoff as-is, the PCI space address is the physical address on this
 460          * platform.
 461          */
 462         vma->vm_flags |= (VM_SHM | VM_LOCKED | VM_IO);
 463
 464         if (write_combine)
 465                 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
 466         else
 467                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 468
 469         if (remap_page_range(vma, vma->vm_start, vma->vm_pgoff << PAGE_SHIFT,
 470                              vma->vm_end - vma->vm_start, vma->vm_page_prot))
 471                 return -EAGAIN;
 472
 473         return 0;
 474 }
 475
 476 /**
 477  * pci_cacheline_size - determine cacheline size for PCI devices
 478  * @dev: void
 479  *
 480  * We want to use the line-size of the outer-most cache.  We assume
 481  * that this line-size is the same for all CPUs.
 482  *
 483  * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
 484  *
 485  * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
 486  */
 487 static unsigned long
 488 pci_cacheline_size (void)
 489 {
 490         u64 levels, unique_caches;
 491         s64 status;
 492         pal_cache_config_info_t cci;
 493         static u8 cacheline_size;
 494
 495         if (cacheline_size)
 496                 return cacheline_size;
 497
 498         status = ia64_pal_cache_summary(&levels, &unique_caches);
 499         if (status != 0) {
 500                 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
 501                        __FUNCTION__, status);
 502                 return SMP_CACHE_BYTES;
 503         }
 504
 505         status = ia64_pal_cache_config_info(levels - 1, /* cache_type (data_or_unified)= */ 2,
 506                                             &cci);
 507         if (status != 0) {
 508                 printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed (status=%ld)\n",
 509                        __FUNCTION__, status);
 510                 return SMP_CACHE_BYTES;
 511         }
 512         cacheline_size = 1 << cci.pcci_line_size;
 513         return cacheline_size;
 514 }
 515
 516 /**
 517  * pcibios_prep_mwi - helper function for drivers/pci/pci.c:pci_set_mwi()
 518  * @dev: the PCI device for which MWI is enabled
 519  *
 520  * For ia64, we can get the cacheline sizes from PAL.
 521  *
 522  * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
 523  */
 524 int
 525 pcibios_prep_mwi (struct pci_dev *dev)
 526 {
 527         unsigned long desired_linesize, current_linesize;
 528         int rc = 0;
 529         u8 pci_linesize;
 530
 531         desired_linesize = pci_cacheline_size();
 532
 533         pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &pci_linesize);
 534         current_linesize = 4 * pci_linesize;
 535         if (desired_linesize != current_linesize) {
 536                 printk(KERN_WARNING "PCI: slot %s has incorrect PCI cache line size of %lu bytes,",
 537                        dev->slot_name, current_linesize);
 538                 if (current_linesize > desired_linesize) {
 539                         printk(" expected %lu bytes instead\n", desired_linesize);
 540                         rc = -EINVAL;
 541                 } else {
 542                         printk(" correcting to %lu\n", desired_linesize);
 543                         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, desired_linesize / 4);
 544                 }
 545         }
 546         return rc;
 547 }