2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/config.h>
18 #include <linux/init.h>
21 #include <linux/irq.h>
22 #include <linux/delay.h>
23 #include <linux/bootmem.h>
24 #include <linux/smp_lock.h>
25 #include <linux/interrupt.h>
26 #include <linux/mc146818rtc.h>
27 #include <linux/kernel_stat.h>
28 #include <linux/sysdev.h>
30 #include <asm/atomic.h>
33 #include <asm/mpspec.h>
34 #include <asm/pgalloc.h>
36 #include <asm/arch_hooks.h>
38 #include <mach_apic.h>
42 static void apic_pm_activate(void);
44 void __init
apic_intr_init(void)
49 /* self generated IPI for local APIC timer */
50 set_intr_gate(LOCAL_TIMER_VECTOR
, apic_timer_interrupt
);
52 /* IPI vectors for APIC spurious and error interrupts */
53 set_intr_gate(SPURIOUS_APIC_VECTOR
, spurious_interrupt
);
54 set_intr_gate(ERROR_APIC_VECTOR
, error_interrupt
);
57 /* Using APIC to generate smp_local_timer_interrupt? */
58 int using_apic_timer
= 0;
60 static DEFINE_PER_CPU(int, prof_multiplier
) = 1;
61 static DEFINE_PER_CPU(int, prof_old_multiplier
) = 1;
62 static DEFINE_PER_CPU(int, prof_counter
) = 1;
64 void enable_NMI_through_LVT0 (void * dummy
)
68 ver
= apic_read(APIC_LVR
);
69 ver
= GET_APIC_VERSION(ver
);
70 v
= APIC_DM_NMI
; /* unmask and set to NMI */
71 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
72 v
|= APIC_LVT_LEVEL_TRIGGER
;
73 apic_write_around(APIC_LVT0
, v
);
78 unsigned int v
, ver
, maxlvt
;
80 v
= apic_read(APIC_LVR
);
81 ver
= GET_APIC_VERSION(v
);
82 /* 82489DXs do not report # of LVT entries. */
83 maxlvt
= APIC_INTEGRATED(ver
) ? GET_APIC_MAXLVT(v
) : 2;
87 void clear_local_APIC(void)
92 maxlvt
= get_maxlvt();
95 * Masking an LVT entry on a P6 can trigger a local APIC error
96 * if the vector is zero. Mask LVTERR first to prevent this.
99 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
100 apic_write_around(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
103 * Careful: we have to set masks only first to deassert
104 * any level-triggered sources.
106 v
= apic_read(APIC_LVTT
);
107 apic_write_around(APIC_LVTT
, v
| APIC_LVT_MASKED
);
108 v
= apic_read(APIC_LVT0
);
109 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
110 v
= apic_read(APIC_LVT1
);
111 apic_write_around(APIC_LVT1
, v
| APIC_LVT_MASKED
);
113 v
= apic_read(APIC_LVTPC
);
114 apic_write_around(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
117 /* lets not touch this if we didn't frob it */
118 #ifdef CONFIG_X86_MCE_P4THERMAL
120 v
= apic_read(APIC_LVTTHMR
);
121 apic_write_around(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
125 * Clean APIC state for other OSs:
127 apic_write_around(APIC_LVTT
, APIC_LVT_MASKED
);
128 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
129 apic_write_around(APIC_LVT1
, APIC_LVT_MASKED
);
131 apic_write_around(APIC_LVTERR
, APIC_LVT_MASKED
);
133 apic_write_around(APIC_LVTPC
, APIC_LVT_MASKED
);
135 #ifdef CONFIG_X86_MCE_P4THERMAL
137 apic_write_around(APIC_LVTTHMR
, APIC_LVT_MASKED
);
139 v
= GET_APIC_VERSION(apic_read(APIC_LVR
));
140 if (APIC_INTEGRATED(v
)) { /* !82489DX */
141 if (maxlvt
> 3) /* Due to Pentium errata 3AP and 11AP. */
142 apic_write(APIC_ESR
, 0);
147 void __init
connect_bsp_APIC(void)
151 * Do not trust the local APIC being empty at bootup.
155 * PIC mode, enable APIC mode in the IMCR, i.e.
156 * connect BSP's local APIC to INT and NMI lines.
158 printk("leaving PIC mode, enabling APIC mode.\n");
165 void disconnect_bsp_APIC(void)
169 * Put the board back into PIC mode (has an effect
170 * only on certain older boards). Note that APIC
171 * interrupts, including IPIs, won't work beyond
172 * this point! The only exception are INIT IPIs.
174 printk("disabling APIC mode, entering PIC mode.\n");
180 void disable_local_APIC(void)
187 * Disable APIC (implies clearing of registers
190 value
= apic_read(APIC_SPIV
);
191 value
&= ~APIC_SPIV_APIC_ENABLED
;
192 apic_write_around(APIC_SPIV
, value
);
196 * This is to verify that we're looking at a real local APIC.
197 * Check these against your board if the CPUs aren't getting
198 * started for no apparent reason.
200 int __init
verify_local_APIC(void)
202 unsigned int reg0
, reg1
;
205 * The version register is read-only in a real APIC.
207 reg0
= apic_read(APIC_LVR
);
208 Dprintk("Getting VERSION: %x\n", reg0
);
209 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
210 reg1
= apic_read(APIC_LVR
);
211 Dprintk("Getting VERSION: %x\n", reg1
);
214 * The two version reads above should print the same
215 * numbers. If the second one is different, then we
216 * poke at a non-APIC.
222 * Check if the version looks reasonably.
224 reg1
= GET_APIC_VERSION(reg0
);
225 if (reg1
== 0x00 || reg1
== 0xff)
228 if (reg1
< 0x02 || reg1
== 0xff)
232 * The ID register is read/write in a real APIC.
234 reg0
= apic_read(APIC_ID
);
235 Dprintk("Getting ID: %x\n", reg0
);
236 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
237 reg1
= apic_read(APIC_ID
);
238 Dprintk("Getting ID: %x\n", reg1
);
239 apic_write(APIC_ID
, reg0
);
240 if (reg1
!= (reg0
^ APIC_ID_MASK
))
244 * The next two are just to see if we have sane values.
245 * They're only really relevant if we're in Virtual Wire
246 * compatibility mode, but most boxes are anymore.
248 reg0
= apic_read(APIC_LVT0
);
249 Dprintk("Getting LVT0: %x\n", reg0
);
250 reg1
= apic_read(APIC_LVT1
);
251 Dprintk("Getting LVT1: %x\n", reg1
);
256 void __init
sync_Arb_IDs(void)
261 apic_wait_icr_idle();
263 Dprintk("Synchronizing Arb IDs.\n");
264 apic_write_around(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
268 extern void __error_in_apic_c (void);
271 * An initial setup of the virtual wire mode.
273 void __init
init_bsp_APIC(void)
275 unsigned long value
, ver
;
278 * Don't do the setup now if we have a SMP BIOS as the
279 * through-I/O-APIC virtual wire mode might be active.
281 if (smp_found_config
|| !cpu_has_apic
)
284 value
= apic_read(APIC_LVR
);
285 ver
= GET_APIC_VERSION(value
);
288 * Do not trust the local APIC being empty at bootup.
295 value
= apic_read(APIC_SPIV
);
296 value
&= ~APIC_VECTOR_MASK
;
297 value
|= APIC_SPIV_APIC_ENABLED
;
299 /* This bit is reserved on P4/Xeon and should be cleared */
300 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) && (boot_cpu_data
.x86
== 15))
301 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
303 value
|= APIC_SPIV_FOCUS_DISABLED
;
304 value
|= SPURIOUS_APIC_VECTOR
;
305 apic_write_around(APIC_SPIV
, value
);
308 * Set up the virtual wire mode.
310 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
312 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
313 value
|= APIC_LVT_LEVEL_TRIGGER
;
314 apic_write_around(APIC_LVT1
, value
);
317 void __init
setup_local_APIC (void)
319 unsigned long value
, ver
, maxlvt
;
321 /* Pound the ESR really hard over the head with a big hammer - mbligh */
323 apic_write(APIC_ESR
, 0);
324 apic_write(APIC_ESR
, 0);
325 apic_write(APIC_ESR
, 0);
326 apic_write(APIC_ESR
, 0);
329 value
= apic_read(APIC_LVR
);
330 ver
= GET_APIC_VERSION(value
);
332 if ((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f)
336 * Double-check whether this APIC is really registered.
338 if (!apic_id_registered())
342 * Intel recommends to set DFR, LDR and TPR before enabling
343 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
344 * document number 292116). So here it goes...
349 * Set Task Priority to 'accept all'. We never change this
352 value
= apic_read(APIC_TASKPRI
);
353 value
&= ~APIC_TPRI_MASK
;
354 apic_write_around(APIC_TASKPRI
, value
);
357 * Now that we are all set up, enable the APIC
359 value
= apic_read(APIC_SPIV
);
360 value
&= ~APIC_VECTOR_MASK
;
364 value
|= APIC_SPIV_APIC_ENABLED
;
367 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
368 * certain networking cards. If high frequency interrupts are
369 * happening on a particular IOAPIC pin, plus the IOAPIC routing
370 * entry is masked/unmasked at a high rate as well then sooner or
371 * later IOAPIC line gets 'stuck', no more interrupts are received
372 * from the device. If focus CPU is disabled then the hang goes
375 * [ This bug can be reproduced easily with a level-triggered
376 * PCI Ne2000 networking cards and PII/PIII processors, dual
380 * Actually disabling the focus CPU check just makes the hang less
381 * frequent as it makes the interrupt distributon model be more
382 * like LRU than MRU (the short-term load is more even across CPUs).
383 * See also the comment in end_level_ioapic_irq(). --macro
386 /* Enable focus processor (bit==0) */
387 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
389 /* Disable focus processor (bit==1) */
390 value
|= APIC_SPIV_FOCUS_DISABLED
;
393 * Set spurious IRQ vector
395 value
|= SPURIOUS_APIC_VECTOR
;
396 apic_write_around(APIC_SPIV
, value
);
401 * set up through-local-APIC on the BP's LINT0. This is not
402 * strictly necessery in pure symmetric-IO mode, but sometimes
403 * we delegate interrupts to the 8259A.
406 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
408 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
409 if (!smp_processor_id() && (pic_mode
|| !value
)) {
410 value
= APIC_DM_EXTINT
;
411 printk("enabled ExtINT on CPU#%d\n", smp_processor_id());
413 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
414 printk("masked ExtINT on CPU#%d\n", smp_processor_id());
416 apic_write_around(APIC_LVT0
, value
);
419 * only the BP should see the LINT1 NMI signal, obviously.
421 if (!smp_processor_id())
424 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
425 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
426 value
|= APIC_LVT_LEVEL_TRIGGER
;
427 apic_write_around(APIC_LVT1
, value
);
429 if (APIC_INTEGRATED(ver
) && !esr_disable
) { /* !82489DX */
430 maxlvt
= get_maxlvt();
431 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
432 apic_write(APIC_ESR
, 0);
433 value
= apic_read(APIC_ESR
);
434 printk("ESR value before enabling vector: %08lx\n", value
);
436 value
= ERROR_APIC_VECTOR
; // enables sending errors
437 apic_write_around(APIC_LVTERR
, value
);
439 * spec says clear errors after enabling vector.
442 apic_write(APIC_ESR
, 0);
443 value
= apic_read(APIC_ESR
);
444 printk("ESR value after enabling vector: %08lx\n", value
);
448 * Something untraceble is creating bad interrupts on
449 * secondary quads ... for the moment, just leave the
450 * ESR disabled - we can't do anything useful with the
451 * errors anyway - mbligh
453 printk("Leaving ESR disabled.\n");
455 printk("No ESR for 82489DX.\n");
458 if (nmi_watchdog
== NMI_LOCAL_APIC
)
459 setup_apic_nmi_watchdog();
466 /* 'active' is true if the local APIC was enabled by us and
467 not the BIOS; this signifies that we are also responsible
468 for disabling it before entering apm/acpi suspend */
470 /* r/w apic fields */
471 unsigned int apic_id
;
472 unsigned int apic_taskpri
;
473 unsigned int apic_ldr
;
474 unsigned int apic_dfr
;
475 unsigned int apic_spiv
;
476 unsigned int apic_lvtt
;
477 unsigned int apic_lvtpc
;
478 unsigned int apic_lvt0
;
479 unsigned int apic_lvt1
;
480 unsigned int apic_lvterr
;
481 unsigned int apic_tmict
;
482 unsigned int apic_tdcr
;
483 unsigned int apic_thmr
;
486 static int lapic_suspend(struct sys_device
*dev
, u32 state
)
491 if (!apic_pm_state
.active
)
494 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
495 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
496 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
497 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
498 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
499 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
500 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
501 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
502 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
503 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
504 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
505 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
506 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
508 local_irq_save(flags
);
509 disable_local_APIC();
510 rdmsr(MSR_IA32_APICBASE
, l
, h
);
511 l
&= ~MSR_IA32_APICBASE_ENABLE
;
512 wrmsr(MSR_IA32_APICBASE
, l
, h
);
513 local_irq_restore(flags
);
517 static int lapic_resume(struct sys_device
*dev
)
522 if (!apic_pm_state
.active
)
525 /* XXX: Pavel needs this for S3 resume, but can't explain why */
526 set_fixmap_nocache(FIX_APIC_BASE
, APIC_DEFAULT_PHYS_BASE
);
528 local_irq_save(flags
);
529 rdmsr(MSR_IA32_APICBASE
, l
, h
);
530 l
&= ~MSR_IA32_APICBASE_BASE
;
531 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
532 wrmsr(MSR_IA32_APICBASE
, l
, h
);
533 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
534 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
535 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
536 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
537 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
538 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
539 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
540 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
541 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
542 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
543 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
544 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
545 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
546 apic_write(APIC_ESR
, 0);
548 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
549 apic_write(APIC_ESR
, 0);
551 local_irq_restore(flags
);
556 static struct sysdev_class lapic_sysclass
= {
557 set_kset_name("lapic"),
558 .resume
= lapic_resume
,
559 .suspend
= lapic_suspend
,
562 static struct sys_device device_lapic
= {
564 .cls
= &lapic_sysclass
,
567 static void __init
apic_pm_activate(void)
569 apic_pm_state
.active
= 1;
572 static int __init
init_lapic_sysfs(void)
578 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
580 error
= sysdev_class_register(&lapic_sysclass
);
582 error
= sys_device_register(&device_lapic
);
585 device_initcall(init_lapic_sysfs
);
587 #else /* CONFIG_PM */
589 static void apic_pm_activate(void) { }
591 #endif /* CONFIG_PM */
594 * Detect and enable local APICs on non-SMP boards.
595 * Original code written by Keir Fraser.
597 int dont_enable_local_apic __initdata
= 0;
599 static int __init
detect_init_APIC (void)
602 extern void get_cpu_vendor(struct cpuinfo_x86
*);
604 /* Disabled by DMI scan or kernel option? */
605 if (dont_enable_local_apic
)
608 /* Workaround for us being called before identify_cpu(). */
609 get_cpu_vendor(&boot_cpu_data
);
611 switch (boot_cpu_data
.x86_vendor
) {
613 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
614 (boot_cpu_data
.x86
== 15))
617 case X86_VENDOR_INTEL
:
618 if (boot_cpu_data
.x86
== 6 ||
619 boot_cpu_data
.x86
== 15 ||
620 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
629 * Some BIOSes disable the local APIC in the
630 * APIC_BASE MSR. This can only be done in
631 * software for Intel P6 and AMD K7 (Model > 1).
633 rdmsr(MSR_IA32_APICBASE
, l
, h
);
634 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
635 printk("Local APIC disabled by BIOS -- reenabling.\n");
636 l
&= ~MSR_IA32_APICBASE_BASE
;
637 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
638 wrmsr(MSR_IA32_APICBASE
, l
, h
);
642 * The APIC feature bit should now be enabled
645 features
= cpuid_edx(1);
646 if (!(features
& (1 << X86_FEATURE_APIC
))) {
647 printk("Could not enable APIC!\n");
650 set_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
651 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
652 if (nmi_watchdog
!= NMI_NONE
)
653 nmi_watchdog
= NMI_LOCAL_APIC
;
655 printk("Found and enabled local APIC!\n");
662 printk("No local APIC present or hardware disabled\n");
666 void __init
init_apic_mappings(void)
668 unsigned long apic_phys
;
671 * If no local APIC can be found then set up a fake all
672 * zeroes page to simulate the local APIC and another
673 * one for the IO-APIC.
675 if (!smp_found_config
&& detect_init_APIC()) {
676 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
677 apic_phys
= __pa(apic_phys
);
679 apic_phys
= mp_lapic_addr
;
681 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
682 Dprintk("mapped APIC to %08lx (%08lx)\n", APIC_BASE
, apic_phys
);
685 * Fetch the APIC ID of the BSP in case we have a
686 * default configuration (or the MP table is broken).
688 if (boot_cpu_physical_apicid
== -1U)
689 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
691 #ifdef CONFIG_X86_IO_APIC
693 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
696 for (i
= 0; i
< nr_ioapics
; i
++) {
697 if (smp_found_config
) {
698 ioapic_phys
= mp_ioapics
[i
].mpc_apicaddr
;
700 printk(KERN_ERR
"WARNING: bogus zero IO-APIC address found in MPTABLE, disabling IO/APIC support!\n");
702 smp_found_config
= 0;
703 skip_ioapic_setup
= 1;
704 goto fake_ioapic_page
;
708 ioapic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
709 ioapic_phys
= __pa(ioapic_phys
);
711 set_fixmap_nocache(idx
, ioapic_phys
);
712 Dprintk("mapped IOAPIC to %08lx (%08lx)\n",
713 __fix_to_virt(idx
), ioapic_phys
);
721 * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts
722 * per second. We assume that the caller has already set up the local
725 * The APIC timer is not exactly sync with the external timer chip, it
726 * closely follows bus clocks.
730 * The timer chip is already set up at HZ interrupts per second here,
731 * but we do not accept timer interrupts yet. We only allow the BP
734 static unsigned int __init
get_8254_timer_count(void)
736 extern spinlock_t i8253_lock
;
741 spin_lock_irqsave(&i8253_lock
, flags
);
743 outb_p(0x00, PIT_MODE
);
744 count
= inb_p(PIT_CH0
);
745 count
|= inb_p(PIT_CH0
) << 8;
747 spin_unlock_irqrestore(&i8253_lock
, flags
);
752 void __init
wait_8254_wraparound(void)
754 unsigned int curr_count
, prev_count
=~0;
757 curr_count
= get_8254_timer_count();
760 prev_count
= curr_count
;
761 curr_count
= get_8254_timer_count();
762 delta
= curr_count
-prev_count
;
765 * This limit for delta seems arbitrary, but it isn't, it's
766 * slightly above the level of error a buggy Mercury/Neptune
767 * chipset timer can cause.
770 } while (delta
< 300);
774 * This function sets up the local APIC timer, with a timeout of
775 * 'clocks' APIC bus clock. During calibration we actually call
776 * this function twice on the boot CPU, once with a bogus timeout
777 * value, second time for real. The other (noncalibrating) CPUs
778 * call this function only once, with the real, calibrated value.
780 * We do reads before writes even if unnecessary, to get around the
781 * P5 APIC double write bug.
784 #define APIC_DIVISOR 16
786 void __setup_APIC_LVTT(unsigned int clocks
)
788 unsigned int lvtt1_value
, tmp_value
;
790 lvtt1_value
= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
) |
791 APIC_LVT_TIMER_PERIODIC
| LOCAL_TIMER_VECTOR
;
792 apic_write_around(APIC_LVTT
, lvtt1_value
);
797 tmp_value
= apic_read(APIC_TDCR
);
798 apic_write_around(APIC_TDCR
, (tmp_value
799 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
802 apic_write_around(APIC_TMICT
, clocks
/APIC_DIVISOR
);
805 static void setup_APIC_timer(unsigned int clocks
)
809 local_irq_save(flags
);
812 * Wait for IRQ0's slice:
814 wait_8254_wraparound();
816 __setup_APIC_LVTT(clocks
);
818 local_irq_restore(flags
);
822 * In this function we calibrate APIC bus clocks to the external
823 * timer. Unfortunately we cannot use jiffies and the timer irq
824 * to calibrate, since some later bootup code depends on getting
825 * the first irq? Ugh.
827 * We want to do the calibration only once since we
828 * want to have local timer irqs syncron. CPUs connected
829 * by the same APIC bus have the very same bus frequency.
830 * And we want to have irqs off anyways, no accidental
834 int __init
calibrate_APIC_clock(void)
836 unsigned long long t1
= 0, t2
= 0;
840 const int LOOPS
= HZ
/10;
842 printk("calibrating APIC timer ...\n");
845 * Put whatever arbitrary (but long enough) timeout
846 * value into the APIC clock, we just want to get the
847 * counter running for calibration.
849 __setup_APIC_LVTT(1000000000);
852 * The timer chip counts down to zero. Let's wait
853 * for a wraparound to start exact measurement:
854 * (the current tick might have been already half done)
857 wait_8254_wraparound();
860 * We wrapped around just now. Let's start:
864 tt1
= apic_read(APIC_TMCCT
);
867 * Let's wait LOOPS wraprounds:
869 for (i
= 0; i
< LOOPS
; i
++)
870 wait_8254_wraparound();
872 tt2
= apic_read(APIC_TMCCT
);
877 * The APIC bus clock counter is 32 bits only, it
878 * might have overflown, but note that we use signed
879 * longs, thus no extra care needed.
881 * underflown to be exact, as the timer counts down ;)
884 result
= (tt1
-tt2
)*APIC_DIVISOR
/LOOPS
;
887 printk("..... CPU clock speed is %ld.%04ld MHz.\n",
888 ((long)(t2
-t1
)/LOOPS
)/(1000000/HZ
),
889 ((long)(t2
-t1
)/LOOPS
)%(1000000/HZ
));
891 printk("..... host bus clock speed is %ld.%04ld MHz.\n",
893 result
%(1000000/HZ
));
898 static unsigned int calibration_result
;
900 int dont_use_local_apic_timer __initdata
= 0;
902 void __init
setup_boot_APIC_clock(void)
904 /* Disabled by DMI scan or kernel option? */
905 if (dont_use_local_apic_timer
)
908 printk("Using local APIC timer interrupts.\n");
909 using_apic_timer
= 1;
913 calibration_result
= calibrate_APIC_clock();
915 * Now set up the timer for real.
917 setup_APIC_timer(calibration_result
);
922 void __init
setup_secondary_APIC_clock(void)
924 local_irq_disable(); /* FIXME: Do we need this? --RR */
925 setup_APIC_timer(calibration_result
);
929 void __init
disable_APIC_timer(void)
931 if (using_apic_timer
) {
934 v
= apic_read(APIC_LVTT
);
935 apic_write_around(APIC_LVTT
, v
| APIC_LVT_MASKED
);
939 void enable_APIC_timer(void)
941 if (using_apic_timer
) {
944 v
= apic_read(APIC_LVTT
);
945 apic_write_around(APIC_LVTT
, v
& ~APIC_LVT_MASKED
);
950 * the frequency of the profiling timer can be changed
951 * by writing a multiplier value into /proc/profile.
953 int setup_profiling_timer(unsigned int multiplier
)
958 * Sanity check. [at least 500 APIC cycles should be
959 * between APIC interrupts as a rule of thumb, to avoid
962 if ( (!multiplier
) || (calibration_result
/multiplier
< 500))
966 * Set the new multiplier for each CPU. CPUs don't start using the
967 * new values until the next timer interrupt in which they do process
968 * accounting. At that time they also adjust their APIC timers
971 for (i
= 0; i
< NR_CPUS
; ++i
)
972 per_cpu(prof_multiplier
, i
) = multiplier
;
980 * Local timer interrupt handler. It does both profiling and
981 * process statistics/rescheduling.
983 * We do profiling in every local tick, statistics/rescheduling
984 * happen only every 'profiling multiplier' ticks. The default
985 * multiplier is 1 and it can be changed by writing the new multiplier
986 * value into /proc/profile.
989 inline void smp_local_timer_interrupt(struct pt_regs
* regs
)
991 int cpu
= smp_processor_id();
993 x86_do_profile(regs
);
995 if (--per_cpu(prof_counter
, cpu
) <= 0) {
997 * The multiplier may have changed since the last time we got
998 * to this point as a result of the user writing to
999 * /proc/profile. In this case we need to adjust the APIC
1000 * timer accordingly.
1002 * Interrupts are already masked off at this point.
1004 per_cpu(prof_counter
, cpu
) = per_cpu(prof_multiplier
, cpu
);
1005 if (per_cpu(prof_counter
, cpu
) !=
1006 per_cpu(prof_old_multiplier
, cpu
)) {
1009 per_cpu(prof_counter
, cpu
));
1010 per_cpu(prof_old_multiplier
, cpu
) =
1011 per_cpu(prof_counter
, cpu
);
1015 update_process_times(user_mode(regs
));
1020 * We take the 'long' return path, and there every subsystem
1021 * grabs the apropriate locks (kernel lock/ irq lock).
1023 * we might want to decouple profiling from the 'long path',
1024 * and do the profiling totally in assembly.
1026 * Currently this isn't too much of an issue (performance wise),
1027 * we can take more than 100K local irqs per second on a 100 MHz P5.
1032 * Local APIC timer interrupt. This is the most natural way for doing
1033 * local interrupts, but local timer interrupts can be emulated by
1034 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1036 * [ if a single-CPU system runs an SMP kernel then we call the local
1037 * interrupt as well. Thus we cannot inline the local irq ... ]
1040 void smp_apic_timer_interrupt(struct pt_regs regs
)
1042 int cpu
= smp_processor_id();
1045 * the NMI deadlock-detector uses this.
1047 irq_stat
[cpu
].apic_timer_irqs
++;
1050 * NOTE! We'd better ACK the irq immediately,
1051 * because timer handling can be slow.
1055 * update_process_times() expects us to have done irq_enter().
1056 * Besides, if we don't timer interrupts ignore the global
1057 * interrupt lock, which is the WrongThing (tm) to do.
1060 smp_local_timer_interrupt(®s
);
1065 * This interrupt should _never_ happen with our APIC/SMP architecture
1067 asmlinkage
void smp_spurious_interrupt(void)
1073 * Check if this really is a spurious interrupt and ACK it
1074 * if it is a vectored one. Just in case...
1075 * Spurious interrupts should not be ACKed.
1077 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1078 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1081 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1082 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, should never happen.\n",
1083 smp_processor_id());
1088 * This interrupt should never happen with our APIC/SMP architecture
1091 asmlinkage
void smp_error_interrupt(void)
1093 unsigned long v
, v1
;
1096 /* First tickle the hardware, only then report what went on. -- REW */
1097 v
= apic_read(APIC_ESR
);
1098 apic_write(APIC_ESR
, 0);
1099 v1
= apic_read(APIC_ESR
);
1101 atomic_inc(&irq_err_count
);
1103 /* Here is what the APIC error bits mean:
1106 2: Send accept error
1107 3: Receive accept error
1109 5: Send illegal vector
1110 6: Received illegal vector
1111 7: Illegal register address
1113 printk (KERN_INFO
"APIC error on CPU%d: %02lx(%02lx)\n",
1114 smp_processor_id(), v
, v1
);
1119 * This initializes the IO-APIC and APIC hardware if this is
1122 int __init
APIC_init_uniprocessor (void)
1124 if (!smp_found_config
&& !cpu_has_apic
)
1128 * Complain if the BIOS pretends there is one.
1130 if (!cpu_has_apic
&& APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1131 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1132 boot_cpu_physical_apicid
);
1136 verify_local_APIC();
1140 phys_cpu_present_map
= 1 << boot_cpu_physical_apicid
;
1144 if (nmi_watchdog
== NMI_LOCAL_APIC
)
1145 check_nmi_watchdog();
1146 #ifdef CONFIG_X86_IO_APIC
1147 if (smp_found_config
)
1148 if (!skip_ioapic_setup
&& nr_ioapics
)
1151 setup_boot_APIC_clock();