include/asm-mips64/sn/sn0/addrs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Derived from IRIX <sys/SN/SN0/addrs.h>, revision 1.126.
   7  *
   8  * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
   9  * Copyright (C) 1999 by Ralf Baechle
  10  */
  11 #ifndef _ASM_SN_SN0_ADDRS_H
  12 #define _ASM_SN_SN0_ADDRS_H
  13
  14 #include <linux/config.h>
  15
  16 /*
  17  * SN0 (on a T5) Address map
  18  *
  19  * This file contains a set of definitions and macros which are used
  20  * to reference into the major address spaces (CAC, HSPEC, IO, MSPEC,
  21  * and UNCAC) used by the SN0 architecture.  It also contains addresses
  22  * for "major" statically locatable PROM/Kernel data structures, such as
  23  * the partition table, the configuration data structure, etc.
  24  * We make an implicit assumption that the processor using this file
  25  * follows the R10K's provisions for specifying uncached attributes;
  26  * should this change, the base registers may very well become processor-
  27  * dependent.
  28  *
  29  * For more information on the address spaces, see the "Local Resources"
  30  * chapter of the Hub specification.
  31  *
  32  * NOTE: This header file is included both by C and by assembler source
  33  *       files.  Please bracket any language-dependent definitions
  34  *       appropriately.
  35  */
  36
  37 /*
  38  * Some of the macros here need to be casted to appropriate types when used
  39  * from C.  They definitely must not be casted from assembly language so we
  40  * use some new ANSI preprocessor stuff to paste these on where needed.
  41  */
  42
  43 #define CAC_BASE                0xa800000000000000
  44
  45 #define HSPEC_BASE              0x9000000000000000
  46 #define IO_BASE                 0x9200000000000000
  47 #define MSPEC_BASE              0x9400000000000000
  48 #define UNCAC_BASE              0x9600000000000000
  49
  50 #define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
  51 #define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
  52 #define TO_UNCAC(x)             (UNCAC_BASE | ((x) & TO_PHYS_MASK))
  53 #define TO_MSPEC(x)             (MSPEC_BASE | ((x) & TO_PHYS_MASK))
  54 #define TO_HSPEC(x)             (HSPEC_BASE | ((x) & TO_PHYS_MASK))
  55
  56
  57 /*
  58  * The following couple of definitions will eventually need to be variables,
  59  * since the amount of address space assigned to each node depends on
  60  * whether the system is running in N-mode (more nodes with less memory)
  61  * or M-mode (fewer nodes with more memory).  We expect that it will
  62  * be a while before we need to make this decision dynamically, though,
  63  * so for now we just use defines bracketed by an ifdef.
  64  */
  65
  66 #ifdef CONFIG_SGI_SN0_N_MODE
  67
  68 #define NODE_SIZE_BITS          31
  69 #define BWIN_SIZE_BITS          28
  70
  71 #define NASID_BITS              9
  72 #define NASID_BITMASK           (0x1ffLL)
  73 #define NASID_SHFT              31
  74 #define NASID_META_BITS         5
  75 #define NASID_LOCAL_BITS        4
  76
  77 #define BDDIR_UPPER_MASK        (UINT64_CAST 0x7ffff << 10)
  78 #define BDECC_UPPER_MASK        (UINT64_CAST 0x3ffffff << 3)
  79
  80 #else /* !defined(CONFIG_SGI_SN0_N_MODE), assume that M-mode is desired */
  81
  82 #define NODE_SIZE_BITS          32
  83 #define BWIN_SIZE_BITS          29
  84
  85 #define NASID_BITMASK           (0xffLL)
  86 #define NASID_BITS              8
  87 #define NASID_SHFT              32
  88 #define NASID_META_BITS         4
  89 #define NASID_LOCAL_BITS        4
  90
  91 #define BDDIR_UPPER_MASK        (UINT64_CAST 0xfffff << 10)
  92 #define BDECC_UPPER_MASK        (UINT64_CAST 0x7ffffff << 3)
  93
  94 #endif /* !defined(CONFIG_SGI_SN0_N_MODE) */
  95
  96 #define NODE_ADDRSPACE_SIZE     (UINT64_CAST 1 << NODE_SIZE_BITS)
  97
  98 #define NASID_MASK              (UINT64_CAST NASID_BITMASK << NASID_SHFT)
  99 #define NASID_GET(_pa)          (int) ((UINT64_CAST (_pa) >>            \
 100                                         NASID_SHFT) & NASID_BITMASK)
 101
 102 #if !defined(__ASSEMBLY__) && !defined(_STANDALONE)
 103
 104 #define NODE_SWIN_BASE(nasid, widget)                                   \
 105         ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN)          \
 106         : RAW_NODE_SWIN_BASE(nasid, widget))
 107 #else /* __ASSEMBLY__ || _STANDALONE */
 108 #define NODE_SWIN_BASE(nasid, widget) \
 109      (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS))
 110 #endif /* __ASSEMBLY__ || _STANDALONE */
 111
 112 /*
 113  * The following definitions pertain to the IO special address
 114  * space.  They define the location of the big and little windows
 115  * of any given node.
 116  */
 117
 118 #define BWIN_INDEX_BITS         3
 119 #define BWIN_SIZE               (UINT64_CAST 1 << BWIN_SIZE_BITS)
 120 #define BWIN_SIZEMASK           (BWIN_SIZE - 1)
 121 #define BWIN_WIDGET_MASK        0x7
 122 #define NODE_BWIN_BASE0(nasid)  (NODE_IO_BASE(nasid) + BWIN_SIZE)
 123 #define NODE_BWIN_BASE(nasid, bigwin)   (NODE_BWIN_BASE0(nasid) +       \
 124                         (UINT64_CAST (bigwin) << BWIN_SIZE_BITS))
 125
 126 #define BWIN_WIDGETADDR(addr)   ((addr) & BWIN_SIZEMASK)
 127 #define BWIN_WINDOWNUM(addr)    (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
 128 /*
 129  * Verify if addr belongs to large window address of node with "nasid"
 130  *
 131  *
 132  * NOTE: "addr" is expected to be XKPHYS address, and NOT physical
 133  * address
 134  *
 135  *
 136  */
 137
 138 #define NODE_BWIN_ADDR(nasid, addr)     \
 139                 (((addr) >= NODE_BWIN_BASE0(nasid)) && \
 140                  ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \
 141                                 BWIN_SIZE)))
 142
 143 /*
 144  * The following define the major position-independent aliases used
 145  * in SN0.
 146  *      CALIAS -- Varies in size, points to the first n bytes of memory
 147  *                      on the reader's node.
 148  */
 149
 150 #define CALIAS_BASE             CAC_BASE
 151
 152
 153
 154 #define BRIDGE_REG_PTR(_base, _off)     ((volatile bridgereg_t *) \
 155         ((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
 156
 157 #define SN0_WIDGET_BASE(_nasid, _wid)   (NODE_SWIN_BASE((_nasid), (_wid)))
 158
 159 /* Turn on sable logging for the processors whose bits are set. */
 160 #ifdef SABLE
 161 #define SABLE_LOG_TRIGGER(_map) \
 162                 *((volatile hubreg_t *)(IO_BASE + 0x17ffff0)) = (_map)
 163 #else
 164 #define SABLE_LOG_TRIGGER(_map)
 165 #endif /* SABLE */
 166
 167 #ifndef __ASSEMBLY__
 168 #define KERN_NMI_ADDR(nasid, slice)                                     \
 169                     TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET +      \
 170                                   (IP27_NMI_KREGS_CPU_SIZE * (slice)))
 171 #endif /* !__ASSEMBLY__ */
 172
 173 #ifdef PROM
 174
 175 #define MISC_PROM_BASE          PHYS_TO_K0(0x01300000)
 176 #define MISC_PROM_SIZE          0x200000
 177
 178 #define DIAG_BASE               PHYS_TO_K0(0x01500000)
 179 #define DIAG_SIZE               0x300000
 180
 181 #define ROUTE_BASE              PHYS_TO_K0(0x01800000)
 182 #define ROUTE_SIZE              0x200000
 183
 184 #define IP27PROM_FLASH_HDR      PHYS_TO_K0(0x01300000)
 185 #define IP27PROM_FLASH_DATA     PHYS_TO_K0(0x01301000)
 186 #define IP27PROM_CORP_MAX       32
 187 #define IP27PROM_CORP           PHYS_TO_K0(0x01800000)
 188 #define IP27PROM_CORP_SIZE      0x10000
 189 #define IP27PROM_CORP_STK       PHYS_TO_K0(0x01810000)
 190 #define IP27PROM_CORP_STKSIZE   0x2000
 191 #define IP27PROM_DECOMP_BUF     PHYS_TO_K0(0x01900000)
 192 #define IP27PROM_DECOMP_SIZE    0xfff00
 193
 194 #define IP27PROM_BASE           PHYS_TO_K0(0x01a00000)
 195 #define IP27PROM_BASE_MAPPED    (K2BASE | 0x1fc00000)
 196 #define IP27PROM_SIZE_MAX       0x100000
 197
 198 #define IP27PROM_PCFG           PHYS_TO_K0(0x01b00000)
 199 #define IP27PROM_PCFG_SIZE      0xd0000
 200 #define IP27PROM_ERRDMP         PHYS_TO_K1(0x01bd0000)
 201 #define IP27PROM_ERRDMP_SIZE    0xf000
 202
 203 #define IP27PROM_INIT_START     PHYS_TO_K1(0x01bd0000)
 204 #define IP27PROM_CONSOLE        PHYS_TO_K1(0x01bdf000)
 205 #define IP27PROM_CONSOLE_SIZE   0x200
 206 #define IP27PROM_NETUART        PHYS_TO_K1(0x01bdf200)
 207 #define IP27PROM_NETUART_SIZE   0x100
 208 #define IP27PROM_UNUSED1        PHYS_TO_K1(0x01bdf300)
 209 #define IP27PROM_UNUSED1_SIZE   0x500
 210 #define IP27PROM_ELSC_BASE_A    PHYS_TO_K0(0x01bdf800)
 211 #define IP27PROM_ELSC_BASE_B    PHYS_TO_K0(0x01bdfc00)
 212 #define IP27PROM_STACK_A        PHYS_TO_K0(0x01be0000)
 213 #define IP27PROM_STACK_B        PHYS_TO_K0(0x01bf0000)
 214 #define IP27PROM_STACK_SHFT     16
 215 #define IP27PROM_STACK_SIZE     (1 << IP27PROM_STACK_SHFT)
 216 #define IP27PROM_INIT_END       PHYS_TO_K0(0x01c00000)
 217
 218 #define SLAVESTACK_BASE         PHYS_TO_K0(0x01580000)
 219 #define SLAVESTACK_SIZE         0x40000
 220
 221 #define ENETBUFS_BASE           PHYS_TO_K0(0x01f80000)
 222 #define ENETBUFS_SIZE           0x20000
 223
 224 #define IO6PROM_BASE            PHYS_TO_K0(0x01c00000)
 225 #define IO6PROM_SIZE            0x400000
 226 #define IO6PROM_BASE_MAPPED     (K2BASE | 0x11c00000)
 227 #define IO6DPROM_BASE           PHYS_TO_K0(0x01c00000)
 228 #define IO6DPROM_SIZE           0x200000
 229
 230 #define NODEBUGUNIX_ADDR        PHYS_TO_K0(0x00019000)
 231 #define DEBUGUNIX_ADDR          PHYS_TO_K0(0x00100000)
 232
 233 #define IP27PROM_INT_LAUNCH     10      /* and 11 */
 234 #define IP27PROM_INT_NETUART    12      /* through 17 */
 235
 236 #endif /* PROM */
 237
 238 /*
 239  * needed by symmon so it needs to be outside #if PROM
 240  */
 241 #define IP27PROM_ELSC_SHFT      10
 242 #define IP27PROM_ELSC_SIZE      (1 << IP27PROM_ELSC_SHFT)
 243
 244 /*
 245  * This address is used by IO6PROM to build MemoryDescriptors of
 246  * free memory. This address is important since unix gets loaded
 247  * at this address, and this memory has to be FREE if unix is to
 248  * be loaded.
 249  */
 250
 251 #define FREEMEM_BASE            PHYS_TO_K0(0x2000000)
 252
 253 #define IO6PROM_STACK_SHFT      14      /* stack per cpu */
 254 #define IO6PROM_STACK_SIZE      (1 << IO6PROM_STACK_SHFT)
 255
 256 /*
 257  * IP27 PROM vectors
 258  */
 259
 260 #define IP27PROM_ENTRY          PHYS_TO_COMPATK1(0x1fc00000)
 261 #define IP27PROM_RESTART        PHYS_TO_COMPATK1(0x1fc00008)
 262 #define IP27PROM_SLAVELOOP      PHYS_TO_COMPATK1(0x1fc00010)
 263 #define IP27PROM_PODMODE        PHYS_TO_COMPATK1(0x1fc00018)
 264 #define IP27PROM_IOC3UARTPOD    PHYS_TO_COMPATK1(0x1fc00020)
 265 #define IP27PROM_FLASHLEDS      PHYS_TO_COMPATK1(0x1fc00028)
 266 #define IP27PROM_REPOD          PHYS_TO_COMPATK1(0x1fc00030)
 267 #define IP27PROM_LAUNCHSLAVE    PHYS_TO_COMPATK1(0x1fc00038)
 268 #define IP27PROM_WAITSLAVE      PHYS_TO_COMPATK1(0x1fc00040)
 269 #define IP27PROM_POLLSLAVE      PHYS_TO_COMPATK1(0x1fc00048)
 270
 271 #define KL_UART_BASE    LOCAL_HUB_ADDR(MD_UREG0_0)      /* base of UART regs */
 272 #define KL_UART_CMD     LOCAL_HUB_ADDR(MD_UREG0_0)      /* UART command reg */
 273 #define KL_UART_DATA    LOCAL_HUB_ADDR(MD_UREG0_1)      /* UART data reg */
 274 #define KL_I2C_REG      MD_UREG0_0                      /* I2C reg */
 275
 276 #ifndef __ASSEMBLY__
 277
 278 /* Address 0x400 to 0x1000 ualias points to cache error eframe + misc
 279  * CACHE_ERR_SP_PTR could either contain an address to the stack, or
 280  * the stack could start at CACHE_ERR_SP_PTR
 281  */
 282 #if defined (HUB_ERR_STS_WAR)
 283 #define CACHE_ERR_EFRAME        0x480
 284 #else /* HUB_ERR_STS_WAR */
 285 #define CACHE_ERR_EFRAME        0x400
 286 #endif /* HUB_ERR_STS_WAR */
 287
 288 #define CACHE_ERR_ECCFRAME      (CACHE_ERR_EFRAME + EF_SIZE)
 289 #define CACHE_ERR_SP_PTR        (0x1000 - 32)   /* why -32? TBD */
 290 #define CACHE_ERR_IBASE_PTR     (0x1000 - 40)
 291 #define CACHE_ERR_SP            (CACHE_ERR_SP_PTR - 16)
 292 #define CACHE_ERR_AREA_SIZE     (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME)
 293
 294 #endif  /* !__ASSEMBLY__ */
 295
 296 #define _ARCSPROM
 297
 298 #ifdef _STANDALONE
 299
 300 /*
 301  * The PROM needs to pass the device base address and the
 302  * device pci cfg space address to the device drivers during
 303  * install. The COMPONENT->Key field is used for this purpose.
 304  * Macros needed by SN0 device drivers to convert the
 305  * COMPONENT->Key field to the respective base address.
 306  * Key field looks as follows:
 307  *
 308  *  +----------------------------------------------------+
 309  *  |devnasid | widget  |pciid |hubwidid|hstnasid | adap |
 310  *  |   2     |   1     |  1   |   1    |    2    |   1  |
 311  *  +----------------------------------------------------+
 312  *  |         |         |      |        |         |      |
 313  *  64        48        40     32       24        8      0
 314  *
 315  * These are used by standalone drivers till the io infrastructure
 316  * is in place.
 317  */
 318
 319 #ifndef __ASSEMBLY__
 320
 321 #define uchar unsigned char
 322
 323 #define KEY_DEVNASID_SHFT  48
 324 #define KEY_WIDID_SHFT     40
 325 #define KEY_PCIID_SHFT     32
 326 #define KEY_HUBWID_SHFT    24
 327 #define KEY_HSTNASID_SHFT  8
 328
 329 #define MK_SN0_KEY(nasid, widid, pciid) \
 330                         ((((__psunsigned_t)nasid)<< KEY_DEVNASID_SHFT |\
 331                                 ((__psunsigned_t)widid) << KEY_WIDID_SHFT) |\
 332                                 ((__psunsigned_t)pciid) << KEY_PCIID_SHFT)
 333
 334 #define ADD_HUBWID_KEY(key,hubwid)\
 335                         (key|=((__psunsigned_t)hubwid << KEY_HUBWID_SHFT))
 336
 337 #define ADD_HSTNASID_KEY(key,hstnasid)\
 338                         (key|=((__psunsigned_t)hstnasid << KEY_HSTNASID_SHFT))
 339
 340 #define GET_DEVNASID_FROM_KEY(key)      ((short)(key >> KEY_DEVNASID_SHFT))
 341 #define GET_WIDID_FROM_KEY(key)         ((uchar)(key >> KEY_WIDID_SHFT))
 342 #define GET_PCIID_FROM_KEY(key)         ((uchar)(key >> KEY_PCIID_SHFT))
 343 #define GET_HUBWID_FROM_KEY(key)        ((uchar)(key >> KEY_HUBWID_SHFT))
 344 #define GET_HSTNASID_FROM_KEY(key)      ((short)(key >> KEY_HSTNASID_SHFT))
 345
 346 #define PCI_64_TARGID_SHFT              60
 347
 348 #define GET_PCIBASE_FROM_KEY(key)  (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
 349                                         GET_WIDID_FROM_KEY(key))\
 350                                         | BRIDGE_DEVIO(GET_PCIID_FROM_KEY(key)))
 351
 352 #define GET_PCICFGBASE_FROM_KEY(key) \
 353                         (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
 354                               GET_WIDID_FROM_KEY(key))\
 355                         | BRIDGE_TYPE0_CFG_DEV(GET_PCIID_FROM_KEY(key)))
 356
 357 #define GET_WIDBASE_FROM_KEY(key) \
 358                         (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
 359                               GET_WIDID_FROM_KEY(key)))
 360
 361 #define PUT_INSTALL_STATUS(c,s)         c->Revision = s
 362 #define GET_INSTALL_STATUS(c)           c->Revision
 363
 364 #endif /* !__ASSEMBLY__ */
 365
 366 #endif /* _STANDALONE */
 367
 368 #if defined (HUB_ERR_STS_WAR)
 369
 370 #define ERR_STS_WAR_REGISTER    IIO_IIBUSERR
 371 #define ERR_STS_WAR_ADDR        LOCAL_HUB_ADDR(IIO_IIBUSERR)
 372 #define ERR_STS_WAR_PHYSADDR    TO_PHYS((__psunsigned_t)ERR_STS_WAR_ADDR)
 373                                 /* Used to match addr in error reg. */
 374 #define OLD_ERR_STS_WAR_OFFSET  ((MD_MEM_BANKS * MD_BANK_SIZE) - 0x100)
 375
 376 #endif /* HUB_ERR_STS_WAR */
 377
 378 #endif /* _ASM_SN_SN0_ADDRS_H */