include/asm-mips64/ip32/crime.h

   1 /*
   2  * Definitions for the SGI O2 Crime chip.
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 2000 Harald Koerfgen
   9  */
  10
  11 #ifndef __ASM_CRIME_H__
  12 #define __ASM_CRIME_H__
  13
  14 #include <asm/types.h>
  15 #include <asm/addrspace.h>
  16
  17 /*
  18  * Address map
  19  */
  20 #ifndef __ASSEMBLY__
  21 #define CRIME_BASE      KSEG1ADDR(0x14000000)
  22 #else
  23 #define CRIME_BASE      0xffffffffb4000000
  24 #endif
  25
  26 #ifndef __ASSEMBLY__
  27 static inline u64 crime_read_64 (unsigned long __offset) {
  28         return *((volatile u64 *) (CRIME_BASE + __offset));
  29 }
  30 static inline void crime_write_64 (unsigned long __offset, u64 __val) {
  31         *((volatile u64 *) (CRIME_BASE + __offset)) = __val;
  32 }
  33 #endif
  34
  35 #undef BIT
  36 #define BIT(x) (1UL << (x))
  37
  38 /* All CRIME registers are 64 bits */
  39 #define CRIME_ID                0
  40
  41 #define CRIME_ID_MASK           0xff
  42 #define CRIME_ID_IDBITS         0xf0
  43 #define CRIME_ID_IDVALUE        0xa0
  44 #define CRIME_ID_REV            0x0f
  45
  46 #define CRIME_REV_PETTY         0x00
  47 #define CRIME_REV_11            0x11
  48 #define CRIME_REV_13            0x13
  49 #define CRIME_REV_14            0x14
  50
  51 #define CRIME_CONTROL           (0x00000008)
  52 #define CRIME_CONTROL_MASK      0x3fff          /* 14-bit registers */
  53
  54 /* CRIME_CONTROL register bits */
  55 #define CRIME_CONTROL_TRITON_SYSADC     0x2000
  56 #define CRIME_CONTROL_CRIME_SYSADC      0x1000
  57 #define CRIME_CONTROL_HARD_RESET        0x0800
  58 #define CRIME_CONTROL_SOFT_RESET        0x0400
  59 #define CRIME_CONTROL_DOG_ENA           0x0200
  60 #define CRIME_CONTROL_ENDIANESS         0x0100
  61
  62 #define CRIME_CONTROL_ENDIAN_BIG        0x0100
  63 #define CRIME_CONTROL_ENDIAN_LITTLE     0x0000
  64
  65 #define CRIME_CONTROL_CQUEUE_HWM        0x000f
  66 #define CRIME_CONTROL_CQUEUE_SHFT       0
  67 #define CRIME_CONTROL_WBUF_HWM          0x00f0
  68 #define CRIME_CONTROL_WBUF_SHFT         8
  69
  70 #define CRIME_INT_STAT                  (0x00000010)
  71 #define CRIME_INT_MASK                  (0x00000018)
  72 #define CRIME_SOFT_INT                  (0x00000020)
  73 #define CRIME_HARD_INT                  (0x00000028)
  74
  75 /* Bits in CRIME_INT_XXX and CRIME_HARD_INT */
  76 #define MACE_VID_IN1_INT                BIT (0)
  77 #define MACE_VID_IN2_INT                BIT (1)
  78 #define MACE_VID_OUT_INT                BIT (2)
  79 #define MACE_ETHERNET_INT               BIT (3)
  80 #define MACE_SUPERIO_INT                BIT (4)
  81 #define MACE_MISC_INT                   BIT (5)
  82 #define MACE_AUDIO_INT                  BIT (6)
  83 #define MACE_PCI_BRIDGE_INT             BIT (7)
  84 #define MACEPCI_SCSI0_INT               BIT (8)
  85 #define MACEPCI_SCSI1_INT               BIT (9)
  86 #define MACEPCI_SLOT0_INT               BIT (10)
  87 #define MACEPCI_SLOT1_INT               BIT (11)
  88 #define MACEPCI_SLOT2_INT               BIT (12)
  89 #define MACEPCI_SHARED0_INT             BIT (13)
  90 #define MACEPCI_SHARED1_INT             BIT (14)
  91 #define MACEPCI_SHARED2_INT             BIT (15)
  92 #define CRIME_GBE0_INT                  BIT (16)
  93 #define CRIME_GBE1_INT                  BIT (17)
  94 #define CRIME_GBE2_INT                  BIT (18)
  95 #define CRIME_GBE3_INT                  BIT (19)
  96 #define CRIME_CPUERR_INT                BIT (20)
  97 #define CRIME_MEMERR_INT                BIT (21)
  98 #define CRIME_RE_EMPTY_E_INT            BIT (22)
  99 #define CRIME_RE_FULL_E_INT             BIT (23)
 100 #define CRIME_RE_IDLE_E_INT             BIT (24)
 101 #define CRIME_RE_EMPTY_L_INT            BIT (25)
 102 #define CRIME_RE_FULL_L_INT             BIT (26)
 103 #define CRIME_RE_IDLE_L_INT             BIT (27)
 104 #define CRIME_SOFT0_INT                 BIT (28)
 105 #define CRIME_SOFT1_INT                 BIT (29)
 106 #define CRIME_SOFT2_INT                 BIT (30)
 107 #define CRIME_SYSCORERR_INT             CRIME_SOFT2_INT
 108 #define CRIME_VICE_INT                  BIT (31)
 109
 110 /* Masks for deciding who handles the interrupt */
 111 #define CRIME_MACE_INT_MASK             0x8f
 112 #define CRIME_MACEISA_INT_MASK          0x70
 113 #define CRIME_MACEPCI_INT_MASK          0xff00
 114 #define CRIME_CRIME_INT_MASK            0xffff0000
 115
 116 /*
 117  * XXX Todo
 118  */
 119 #define CRIME_DOG                       (0x00000030)
 120 /* We are word-play compatible but not misspelling compatible */
 121 #define MC_GRUFF                        CRIME_DOG
 122 #define CRIME_DOG_MASK                  (0x001fffff)
 123
 124 /* CRIME_DOG register bits */
 125 #define CRIME_DOG_POWER_ON_RESET        (0x00010000)
 126 #define CRIME_DOG_WARM_RESET            (0x00080000)
 127 #define CRIME_DOG_TIMEOUT               (CRIME_DOG_POWER_ON_RESET|CRIME_DOG_WARM_RESET)
 128 #define CRIME_DOG_VALUE                 (0x00007fff)    /* ??? */
 129
 130 #define CRIME_TIME                      (0x00000038)
 131 #define CRIME_TIME_MASK                 (0x0000ffffffffffff)
 132
 133 #ifdef MASTER_FREQ
 134 #undef MASTER_FREQ
 135 #endif
 136 #define CRIME_MASTER_FREQ               66666500        /* Crime upcounter frequency */
 137 #define CRIME_NS_PER_TICK               15      /* for delay_calibrate */
 138
 139 #define CRIME_CPU_ERROR_ADDR            (0x00000040)
 140 #define CRIME_CPU_ERROR_ADDR_MASK       (0x3ffffffff)
 141
 142 #define CRIME_CPU_ERROR_STAT            (0x00000048)
 143 /* REV_PETTY only! */
 144 #define CRIME_CPU_ERROR_ENA             (0x00000050)
 145
 146 /*
 147  * bit definitions for CRIME/VICE error status and enable registers
 148  */
 149 #define CRIME_CPU_ERROR_MASK           0x7UL   /* cpu error stat is 3 bits */
 150 #define CRIME_CPU_ERROR_CPU_ILL_ADDR   0x4
 151 #define CRIME_CPU_ERROR_VICE_WRT_PRTY  0x2
 152 #define CRIME_CPU_ERROR_CPU_WRT_PRTY   0x1
 153
 154 /*
 155  * these are the definitions for the error status/enable  register in
 156  * petty crime.  Note that the enable register does not exist in crime
 157  * rev 1 and above.
 158  */
 159 #define CRIME_CPU_ERROR_MASK_REV0               0x3ff   /* cpu error stat is 9 bits */
 160 #define CRIME_CPU_ERROR_CPU_INV_ADDR_RD         0x200
 161 #define CRIME_CPU_ERROR_VICE_II                 0x100
 162 #define CRIME_CPU_ERROR_VICE_SYSAD              0x80
 163 #define CRIME_CPU_ERROR_VICE_SYSCMD             0x40
 164 #define CRIME_CPU_ERROR_VICE_INV_ADDR           0x20
 165 #define CRIME_CPU_ERROR_CPU_II                  0x10
 166 #define CRIME_CPU_ERROR_CPU_SYSAD               0x8
 167 #define CRIME_CPU_ERROR_CPU_SYSCMD              0x4
 168 #define CRIME_CPU_ERROR_CPU_INV_ADDR_WR         0x2
 169 #define CRIME_CPU_ERROR_CPU_INV_REG_ADDR        0x1
 170
 171 #define CRIME_VICE_ERROR_ADDR           (0x00000058)
 172 #define CRIME_VICE_ERROR_ADDR_MASK      (0x3fffffff)
 173
 174 #define CRIME_MEM_CONTROL               (0x00000200)
 175 #define CRIME_MEM_CONTROL_MASK          0x3     /* 25 cent register */
 176 #define CRIME_MEM_CONTROL_ECC_ENA       0x1
 177 #define CRIME_MEM_CONTROL_USE_ECC_REPL  0x2
 178
 179 /*
 180  * macros for CRIME memory bank control registers.
 181  */
 182 #define CRIME_MEM_BANK_CONTROL(__bank)          (0x00000208 + ((__bank) << 3))
 183 #define CRIME_MEM_BANK_CONTROL_MASK             0x11f /* 9 bits 7:5 reserved */
 184 #define CRIME_MEM_BANK_CONTROL_ADDR             0x01f
 185 #define CRIME_MEM_BANK_CONTROL_SDRAM_SIZE       0x100
 186
 187 #define CRIME_MEM_REFRESH_COUNTER       (0x00000248)
 188 #define CRIME_MEM_REFRESH_COUNTER_MASK  0x7ff   /* 11-bit register */
 189
 190 #define CRIME_MAXBANKS                 8
 191
 192 /*
 193  * CRIME Memory error status register bit definitions
 194  */
 195 #define CRIME_MEM_ERROR_STAT            (0x00000250)
 196 #define CRIME_MEM_ERROR_STAT_MASK       0x0ff7ffff    /* 28-bit register */
 197 #define CRIME_MEM_ERROR_MACE_ID         0x0000007f
 198 #define CRIME_MEM_ERROR_MACE_ACCESS     0x00000080
 199 #define CRIME_MEM_ERROR_RE_ID           0x00007f00
 200 #define CRIME_MEM_ERROR_RE_ACCESS       0x00008000
 201 #define CRIME_MEM_ERROR_GBE_ACCESS      0x00010000
 202 #define CRIME_MEM_ERROR_VICE_ACCESS     0x00020000
 203 #define CRIME_MEM_ERROR_CPU_ACCESS      0x00040000
 204 #define CRIME_MEM_ERROR_RESERVED        0x00080000
 205 #define CRIME_MEM_ERROR_SOFT_ERR        0x00100000
 206 #define CRIME_MEM_ERROR_HARD_ERR        0x00200000
 207 #define CRIME_MEM_ERROR_MULTIPLE        0x00400000
 208 #define CRIME_MEM_ERROR_ECC             0x01800000
 209 #define CRIME_MEM_ERROR_MEM_ECC_RD      0x00800000
 210 #define CRIME_MEM_ERROR_MEM_ECC_RMW     0x01000000
 211 #define CRIME_MEM_ERROR_INV             0x0e000000
 212 #define CRIME_MEM_ERROR_INV_MEM_ADDR_RD 0x02000000
 213 #define CRIME_MEM_ERROR_INV_MEM_ADDR_WR 0x04000000
 214 #define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW        0x08000000
 215
 216 #define CRIME_MEM_ERROR_ADDR            (0x00000258)
 217 #define CRIME_MEM_ERROR_ADDR_MASK       0x3fffffff
 218
 219 #define CRIME_MEM_ERROR_ECC_SYN         (0x00000260)
 220 #define CRIME_MEM_ERROR_ECC_SYN_MASK    0xffffffff
 221
 222 #define CRIME_MEM_ERROR_ECC_CHK         (0x00000268)
 223 #define CRIME_MEM_ERROR_ECC_CHK_MASK    0xffffffff
 224
 225 #define CRIME_MEM_ERROR_ECC_REPL        (0x00000270)
 226 #define CRIME_MEM_ERROR_ECC_REPL_MASK   0xffffffff
 227
 228 #endif /* __ASM_CRIME_H__ */