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Get rid of arch/mips64/kernel. 9116 lines of code gone.
[linux-2.6/linux-mips.git] / sound / sparc / cs4231.c
blobac54f283fe63c3aed43c22012d29b48d32fdbcb7
1 /*
2 * Driver for CS4231 sound chips found on Sparcs.
3 * Copyright (C) 2002 David S. Miller <davem@redhat.com>
4 *
5 * Based entirely upon drivers/sbus/audio/cs4231.c which is:
6 * Copyright (C) 1996, 1997, 1998, 1998 Derrick J Brashear (shadow@andrew.cmu.edu)
7 * and also sound/isa/cs423x/cs4231_lib.c which is:
8 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
9 */
10
11 #include <linux/config.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/delay.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18
19 #include <sound/driver.h>
20 #include <sound/core.h>
21 #include <sound/pcm.h>
22 #include <sound/info.h>
23 #include <sound/control.h>
24 #include <sound/timer.h>
25 #define SNDRV_GET_ID
26 #include <sound/initval.h>
27 #include <sound/pcm_params.h>
28
29 #include <asm/io.h>
30 #include <asm/irq.h>
31
32 #ifdef CONFIG_SBUS
33 #define SBUS_SUPPORT
34 #endif
35
36 #ifdef SBUS_SUPPORT
37 #include <asm/sbus.h>
38 #endif
39
40 #if defined(CONFIG_PCI) && defined(CONFIG_SPARC64)
41 #define EBUS_SUPPORT
42 #endif
43
44 #ifdef EBUS_SUPPORT
45 #include <linux/pci.h>
46 #include <asm/ebus.h>
47 #endif
48
49 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
50 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
51 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
52
53 MODULE_PARM(index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
54 MODULE_PARM_DESC(index, "Index value for Sun CS4231 soundcard.");
55 MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
56 MODULE_PARM(id, "1-" __MODULE_STRING(SNDRV_CARDS) "s");
57 MODULE_PARM_DESC(id, "ID string for Sun CS4231 soundcard.");
58 MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
59 MODULE_PARM(enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
60 MODULE_PARM_DESC(enable, "Enable Sun CS4231 soundcard.");
61 MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
62 MODULE_AUTHOR("Jaroslav Kysela, Derrick J. Brashear and David S. Miller");
63 MODULE_DESCRIPTION("Sun CS4231");
64 MODULE_LICENSE("GPL");
65 MODULE_CLASSES("{sound}");
66 MODULE_DEVICES("{{Sun,CS4231}}");
67
68 typedef struct snd_cs4231 {
69 spinlock_t lock;
70 unsigned long port;
71 #ifdef EBUS_SUPPORT
72 struct ebus_dma_info eb2c;
73 struct ebus_dma_info eb2p;
74 #endif
75
76 u32 flags;
77 #define CS4231_FLAG_EBUS 0x00000001
78 #define CS4231_FLAG_PLAYBACK 0x00000002
79 #define CS4231_FLAG_CAPTURE 0x00000004
80
81 snd_card_t *card;
82 snd_pcm_t *pcm;
83 snd_pcm_substream_t *playback_substream;
84 unsigned int p_periods_sent;
85 snd_pcm_substream_t *capture_substream;
86 unsigned int c_periods_sent;
87 snd_timer_t *timer;
88
89 unsigned short mode;
90 #define CS4231_MODE_NONE 0x0000
91 #define CS4231_MODE_PLAY 0x0001
92 #define CS4231_MODE_RECORD 0x0002
93 #define CS4231_MODE_TIMER 0x0004
94 #define CS4231_MODE_OPEN (CS4231_MODE_PLAY|CS4231_MODE_RECORD|CS4231_MODE_TIMER)
95
96 unsigned char image[32]; /* registers image */
97 int mce_bit;
98 int calibrate_mute;
99 struct semaphore mce_mutex;
100 struct semaphore open_mutex;
101
102 union {
103 #ifdef SBUS_SUPPORT
104 struct sbus_dev *sdev;
105 #endif
106 #ifdef EBUS_SUPPORT
107 struct pci_dev *pdev;
108 #endif
109 } dev_u;
110 unsigned int irq[2];
111 unsigned int regs_size;
112 struct snd_cs4231 *next;
113 } cs4231_t;
114 #define chip_t cs4231_t
115
116 static cs4231_t *cs4231_list;
117
118 /* Eventually we can use sound/isa/cs423x/cs4231_lib.c directly, but for
119 * now.... -DaveM
120 */
121
122 /* IO ports */
123
124 #define CS4231P(chip, x) ((chip)->port + c_d_c_CS4231##x)
125
126 /* XXX offsets are different than PC ISA chips... */
127 #define c_d_c_CS4231REGSEL 0x0
128 #define c_d_c_CS4231REG 0x4
129 #define c_d_c_CS4231STATUS 0x8
130 #define c_d_c_CS4231PIO 0xc
131
132 /* codec registers */
133
134 #define CS4231_LEFT_INPUT 0x00 /* left input control */
135 #define CS4231_RIGHT_INPUT 0x01 /* right input control */
136 #define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */
137 #define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */
138 #define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */
139 #define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */
140 #define CS4231_LEFT_OUTPUT 0x06 /* left output control register */
141 #define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */
142 #define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */
143 #define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */
144 #define CS4231_PIN_CTRL 0x0a /* pin control */
145 #define CS4231_TEST_INIT 0x0b /* test and initialization */
146 #define CS4231_MISC_INFO 0x0c /* miscellaneaous information */
147 #define CS4231_LOOPBACK 0x0d /* loopback control */
148 #define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */
149 #define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */
150 #define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */
151 #define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */
152 #define CS4231_LEFT_LINE_IN 0x12 /* left line input control */
153 #define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */
154 #define CS4231_TIMER_LOW 0x14 /* timer low byte */
155 #define CS4231_TIMER_HIGH 0x15 /* timer high byte */
156 #define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */
157 #define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */
158 #define CS4236_EXT_REG 0x17 /* extended register access */
159 #define CS4231_IRQ_STATUS 0x18 /* irq status register */
160 #define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */
161 #define CS4231_VERSION 0x19 /* CS4231(A) - version values */
162 #define CS4231_MONO_CTRL 0x1a /* mono input/output control */
163 #define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */
164 #define CS4235_LEFT_MASTER 0x1b /* left master output control */
165 #define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */
166 #define CS4231_PLY_VAR_FREQ 0x1d /* playback variable frequency */
167 #define CS4235_RIGHT_MASTER 0x1d /* right master output control */
168 #define CS4231_REC_UPR_CNT 0x1e /* record upper count */
169 #define CS4231_REC_LWR_CNT 0x1f /* record lower count */
170
171 /* definitions for codec register select port - CODECP( REGSEL ) */
172
173 #define CS4231_INIT 0x80 /* CODEC is initializing */
174 #define CS4231_MCE 0x40 /* mode change enable */
175 #define CS4231_TRD 0x20 /* transfer request disable */
176
177 /* definitions for codec status register - CODECP( STATUS ) */
178
179 #define CS4231_GLOBALIRQ 0x01 /* IRQ is active */
180
181 /* definitions for codec irq status */
182
183 #define CS4231_PLAYBACK_IRQ 0x10
184 #define CS4231_RECORD_IRQ 0x20
185 #define CS4231_TIMER_IRQ 0x40
186 #define CS4231_ALL_IRQS 0x70
187 #define CS4231_REC_UNDERRUN 0x08
188 #define CS4231_REC_OVERRUN 0x04
189 #define CS4231_PLY_OVERRUN 0x02
190 #define CS4231_PLY_UNDERRUN 0x01
191
192 /* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */
193
194 #define CS4231_ENABLE_MIC_GAIN 0x20
195
196 #define CS4231_MIXS_LINE 0x00
197 #define CS4231_MIXS_AUX1 0x40
198 #define CS4231_MIXS_MIC 0x80
199 #define CS4231_MIXS_ALL 0xc0
200
201 /* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */
202
203 #define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */
204 #define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */
205 #define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */
206 #define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */
207 #define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */
208 #define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */
209 #define CS4231_STEREO 0x10 /* stereo mode */
210 /* bits 3-1 define frequency divisor */
211 #define CS4231_XTAL1 0x00 /* 24.576 crystal */
212 #define CS4231_XTAL2 0x01 /* 16.9344 crystal */
213
214 /* definitions for interface control register - CS4231_IFACE_CTRL */
215
216 #define CS4231_RECORD_PIO 0x80 /* record PIO enable */
217 #define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */
218 #define CS4231_CALIB_MODE 0x18 /* calibration mode bits */
219 #define CS4231_AUTOCALIB 0x08 /* auto calibrate */
220 #define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */
221 #define CS4231_RECORD_ENABLE 0x02 /* record enable */
222 #define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */
223
224 /* definitions for pin control register - CS4231_PIN_CTRL */
225
226 #define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */
227 #define CS4231_XCTL1 0x40 /* external control #1 */
228 #define CS4231_XCTL0 0x80 /* external control #0 */
229
230 /* definitions for test and init register - CS4231_TEST_INIT */
231
232 #define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */
233 #define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */
234
235 /* definitions for misc control register - CS4231_MISC_INFO */
236
237 #define CS4231_MODE2 0x40 /* MODE 2 */
238 #define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */
239 #define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */
240
241 /* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */
242
243 #define CS4231_DACZ 0x01 /* zero DAC when underrun */
244 #define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */
245 #define CS4231_OLB 0x80 /* output level bit */
246
247 /* SBUS DMA register defines. */
248
249 #define APCCSR 0x10UL /* APC DMA CSR */
250 #define APCCVA 0x20UL /* APC Capture DMA Address */
251 #define APCCC 0x24UL /* APC Capture Count */
252 #define APCCNVA 0x28UL /* APC Capture DMA Next Address */
253 #define APCCNC 0x2cUL /* APC Capture Next Count */
254 #define APCPVA 0x30UL /* APC Play DMA Address */
255 #define APCPC 0x34UL /* APC Play Count */
256 #define APCPNVA 0x38UL /* APC Play DMA Next Address */
257 #define APCPNC 0x3cUL /* APC Play Next Count */
258
259 /* APCCSR bits */
260
261 #define APC_INT_PENDING 0x800000 /* Interrupt Pending */
262 #define APC_PLAY_INT 0x400000 /* Playback interrupt */
263 #define APC_CAPT_INT 0x200000 /* Capture interrupt */
264 #define APC_GENL_INT 0x100000 /* General interrupt */
265 #define APC_XINT_ENA 0x80000 /* General ext int. enable */
266 #define APC_XINT_PLAY 0x40000 /* Playback ext intr */
267 #define APC_XINT_CAPT 0x20000 /* Capture ext intr */
268 #define APC_XINT_GENL 0x10000 /* Error ext intr */
269 #define APC_XINT_EMPT 0x8000 /* Pipe empty interrupt (0 write to pva) */
270 #define APC_XINT_PEMP 0x4000 /* Play pipe empty (pva and pnva not set) */
271 #define APC_XINT_PNVA 0x2000 /* Playback NVA dirty */
272 #define APC_XINT_PENA 0x1000 /* play pipe empty Int enable */
273 #define APC_XINT_COVF 0x800 /* Cap data dropped on floor */
274 #define APC_XINT_CNVA 0x400 /* Capture NVA dirty */
275 #define APC_XINT_CEMP 0x200 /* Capture pipe empty (cva and cnva not set) */
276 #define APC_XINT_CENA 0x100 /* Cap. pipe empty int enable */
277 #define APC_PPAUSE 0x80 /* Pause the play DMA */
278 #define APC_CPAUSE 0x40 /* Pause the capture DMA */
279 #define APC_CDC_RESET 0x20 /* CODEC RESET */
280 #define APC_PDMA_READY 0x08 /* Play DMA Go */
281 #define APC_CDMA_READY 0x04 /* Capture DMA Go */
282 #define APC_CHIP_RESET 0x01 /* Reset the chip */
283
284 /* EBUS DMA register offsets */
285
286 #define EBDMA_CSR 0x00UL /* Control/Status */
287 #define EBDMA_ADDR 0x04UL /* DMA Address */
288 #define EBDMA_COUNT 0x08UL /* DMA Count */
289
290 /*
291 * Some variables
292 */
293
294 static unsigned char freq_bits[14] = {
295 /* 5510 */ 0x00 | CS4231_XTAL2,
296 /* 6620 */ 0x0E | CS4231_XTAL2,
297 /* 8000 */ 0x00 | CS4231_XTAL1,
298 /* 9600 */ 0x0E | CS4231_XTAL1,
299 /* 11025 */ 0x02 | CS4231_XTAL2,
300 /* 16000 */ 0x02 | CS4231_XTAL1,
301 /* 18900 */ 0x04 | CS4231_XTAL2,
302 /* 22050 */ 0x06 | CS4231_XTAL2,
303 /* 27042 */ 0x04 | CS4231_XTAL1,
304 /* 32000 */ 0x06 | CS4231_XTAL1,
305 /* 33075 */ 0x0C | CS4231_XTAL2,
306 /* 37800 */ 0x08 | CS4231_XTAL2,
307 /* 44100 */ 0x0A | CS4231_XTAL2,
308 /* 48000 */ 0x0C | CS4231_XTAL1
309 };
310
311 static unsigned int rates[14] = {
312 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
313 27042, 32000, 33075, 37800, 44100, 48000
314 };
315
316 static snd_pcm_hw_constraint_list_t hw_constraints_rates = {
317 .count = 14,
318 .list = rates,
319 };
320
321 static int snd_cs4231_xrate(snd_pcm_runtime_t *runtime)
322 {
323 return snd_pcm_hw_constraint_list(runtime, 0,
324 SNDRV_PCM_HW_PARAM_RATE,
325 &hw_constraints_rates);
326 }
327
328 static unsigned char snd_cs4231_original_image[32] =
329 {
330 0x00, /* 00/00 - lic */
331 0x00, /* 01/01 - ric */
332 0x9f, /* 02/02 - la1ic */
333 0x9f, /* 03/03 - ra1ic */
334 0x9f, /* 04/04 - la2ic */
335 0x9f, /* 05/05 - ra2ic */
336 0xbf, /* 06/06 - loc */
337 0xbf, /* 07/07 - roc */
338 0x20, /* 08/08 - pdfr */
339 CS4231_AUTOCALIB, /* 09/09 - ic */
340 0x00, /* 0a/10 - pc */
341 0x00, /* 0b/11 - ti */
342 CS4231_MODE2, /* 0c/12 - mi */
343 0x00, /* 0d/13 - lbc */
344 0x00, /* 0e/14 - pbru */
345 0x00, /* 0f/15 - pbrl */
346 0x80, /* 10/16 - afei */
347 0x01, /* 11/17 - afeii */
348 0x9f, /* 12/18 - llic */
349 0x9f, /* 13/19 - rlic */
350 0x00, /* 14/20 - tlb */
351 0x00, /* 15/21 - thb */
352 0x00, /* 16/22 - la3mic/reserved */
353 0x00, /* 17/23 - ra3mic/reserved */
354 0x00, /* 18/24 - afs */
355 0x00, /* 19/25 - lamoc/version */
356 0x00, /* 1a/26 - mioc */
357 0x00, /* 1b/27 - ramoc/reserved */
358 0x20, /* 1c/28 - cdfr */
359 0x00, /* 1d/29 - res4 */
360 0x00, /* 1e/30 - cbru */
361 0x00, /* 1f/31 - cbrl */
362 };
363
364 static u8 __cs4231_readb(cs4231_t *cp, unsigned long reg_addr)
365 {
366 #ifdef EBUS_SUPPORT
367 if (cp->flags & CS4231_FLAG_EBUS) {
368 return readb(reg_addr);
369 } else {
370 #endif
371 #ifdef SBUS_SUPPORT
372 return sbus_readb(reg_addr);
373 #endif
374 #ifdef EBUS_SUPPORT
375 }
376 #endif
377 }
378
379 static void __cs4231_writeb(cs4231_t *cp, u8 val, unsigned long reg_addr)
380 {
381 #ifdef EBUS_SUPPORT
382 if (cp->flags & CS4231_FLAG_EBUS) {
383 return writeb(val, reg_addr);
384 } else {
385 #endif
386 #ifdef SBUS_SUPPORT
387 return sbus_writeb(val, reg_addr);
388 #endif
389 #ifdef EBUS_SUPPORT
390 }
391 #endif
392 }
393
394 /*
395 * Basic I/O functions
396 */
397
398 void snd_cs4231_outm(cs4231_t *chip, unsigned char reg,
399 unsigned char mask, unsigned char value)
400 {
401 int timeout;
402 unsigned char tmp;
403
404 for (timeout = 250;
405 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
406 timeout--)
407 udelay(100);
408 #ifdef CONFIG_SND_DEBUG
409 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
410 snd_printk("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
411 #endif
412 if (chip->calibrate_mute) {
413 chip->image[reg] &= mask;
414 chip->image[reg] |= value;
415 } else {
416 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
417 mb();
418 tmp = (chip->image[reg] & mask) | value;
419 __cs4231_writeb(chip, tmp, CS4231P(chip, REG));
420 chip->image[reg] = tmp;
421 mb();
422 }
423 }
424
425 static void snd_cs4231_dout(cs4231_t *chip, unsigned char reg, unsigned char value)
426 {
427 int timeout;
428
429 for (timeout = 250;
430 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
431 timeout--)
432 udelay(100);
433 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
434 __cs4231_writeb(chip, value, CS4231P(chip, REG));
435 mb();
436 }
437
438 static void snd_cs4231_out(cs4231_t *chip, unsigned char reg, unsigned char value)
439 {
440 int timeout;
441
442 for (timeout = 250;
443 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
444 timeout--)
445 udelay(100);
446 #ifdef CONFIG_SND_DEBUG
447 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
448 snd_printk("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
449 #endif
450 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
451 __cs4231_writeb(chip, value, CS4231P(chip, REG));
452 chip->image[reg] = value;
453 mb();
454 #if 0
455 printk("codec out - reg 0x%x = 0x%x\n", chip->mce_bit | reg, value);
456 #endif
457 }
458
459 static unsigned char snd_cs4231_in(cs4231_t *chip, unsigned char reg)
460 {
461 int timeout;
462 unsigned char ret;
463
464 for (timeout = 250;
465 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
466 timeout--)
467 udelay(100);
468 #ifdef CONFIG_SND_DEBUG
469 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
470 snd_printk("in: auto calibration time out - reg = 0x%x\n", reg);
471 #endif
472 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
473 mb();
474 ret = __cs4231_readb(chip, CS4231P(chip, REG));
475 #if 0
476 printk("codec in - reg 0x%x = 0x%x\n", chip->mce_bit | reg, ret);
477 #endif
478 return ret;
479 }
480
481 #ifdef CONFIG_SND_DEBUG
482
483 void snd_cs4231_debug(cs4231_t *chip)
484 {
485 printk("CS4231 REGS: INDEX = 0x%02x ",
486 __cs4231_readb(chip, CS4231P(chip, REGSEL)));
487 printk(" STATUS = 0x%02x\n",
488 __cs4231_readb(chip, CS4231P(chip, STATUS)));
489 printk(" 0x00: left input = 0x%02x ", snd_cs4231_in(chip, 0x00));
490 printk(" 0x10: alt 1 (CFIG 2) = 0x%02x\n", snd_cs4231_in(chip, 0x10));
491 printk(" 0x01: right input = 0x%02x ", snd_cs4231_in(chip, 0x01));
492 printk(" 0x11: alt 2 (CFIG 3) = 0x%02x\n", snd_cs4231_in(chip, 0x11));
493 printk(" 0x02: GF1 left input = 0x%02x ", snd_cs4231_in(chip, 0x02));
494 printk(" 0x12: left line in = 0x%02x\n", snd_cs4231_in(chip, 0x12));
495 printk(" 0x03: GF1 right input = 0x%02x ", snd_cs4231_in(chip, 0x03));
496 printk(" 0x13: right line in = 0x%02x\n", snd_cs4231_in(chip, 0x13));
497 printk(" 0x04: CD left input = 0x%02x ", snd_cs4231_in(chip, 0x04));
498 printk(" 0x14: timer low = 0x%02x\n", snd_cs4231_in(chip, 0x14));
499 printk(" 0x05: CD right input = 0x%02x ", snd_cs4231_in(chip, 0x05));
500 printk(" 0x15: timer high = 0x%02x\n", snd_cs4231_in(chip, 0x15));
501 printk(" 0x06: left output = 0x%02x ", snd_cs4231_in(chip, 0x06));
502 printk(" 0x16: left MIC (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x16));
503 printk(" 0x07: right output = 0x%02x ", snd_cs4231_in(chip, 0x07));
504 printk(" 0x17: right MIC (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x17));
505 printk(" 0x08: playback format = 0x%02x ", snd_cs4231_in(chip, 0x08));
506 printk(" 0x18: IRQ status = 0x%02x\n", snd_cs4231_in(chip, 0x18));
507 printk(" 0x09: iface (CFIG 1) = 0x%02x ", snd_cs4231_in(chip, 0x09));
508 printk(" 0x19: left line out = 0x%02x\n", snd_cs4231_in(chip, 0x19));
509 printk(" 0x0a: pin control = 0x%02x ", snd_cs4231_in(chip, 0x0a));
510 printk(" 0x1a: mono control = 0x%02x\n", snd_cs4231_in(chip, 0x1a));
511 printk(" 0x0b: init & status = 0x%02x ", snd_cs4231_in(chip, 0x0b));
512 printk(" 0x1b: right line out = 0x%02x\n", snd_cs4231_in(chip, 0x1b));
513 printk(" 0x0c: revision & mode = 0x%02x ", snd_cs4231_in(chip, 0x0c));
514 printk(" 0x1c: record format = 0x%02x\n", snd_cs4231_in(chip, 0x1c));
515 printk(" 0x0d: loopback = 0x%02x ", snd_cs4231_in(chip, 0x0d));
516 printk(" 0x1d: var freq (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x1d));
517 printk(" 0x0e: ply upr count = 0x%02x ", snd_cs4231_in(chip, 0x0e));
518 printk(" 0x1e: rec upr count = 0x%02x\n", snd_cs4231_in(chip, 0x1e));
519 printk(" 0x0f: ply lwr count = 0x%02x ", snd_cs4231_in(chip, 0x0f));
520 printk(" 0x1f: rec lwr count = 0x%02x\n", snd_cs4231_in(chip, 0x1f));
521 }
522
523 #endif
524
525 /*
526 * CS4231 detection / MCE routines
527 */
528
529 static void snd_cs4231_busy_wait(cs4231_t *chip)
530 {
531 int timeout;
532
533 /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
534 for (timeout = 5; timeout > 0; timeout--)
535 __cs4231_readb(chip, CS4231P(chip, REGSEL));
536 /* end of cleanup sequence */
537 for (timeout = 250;
538 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
539 timeout--)
540 udelay(100);
541 }
542
543 static void snd_cs4231_mce_up(cs4231_t *chip)
544 {
545 unsigned long flags;
546 int timeout;
547
548 spin_lock_irqsave(&chip->lock, flags);
549 for (timeout = 250; timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT); timeout--)
550 udelay(100);
551 #ifdef CONFIG_SND_DEBUG
552 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
553 snd_printk("mce_up - auto calibration time out (0)\n");
554 #endif
555 chip->mce_bit |= CS4231_MCE;
556 timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL));
557 if (timeout == 0x80)
558 snd_printk("mce_up [0x%lx]: serious init problem - codec still busy\n", chip->port);
559 if (!(timeout & CS4231_MCE))
560 __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL));
561 spin_unlock_irqrestore(&chip->lock, flags);
562 }
563
564 static void snd_cs4231_mce_down(cs4231_t *chip)
565 {
566 unsigned long flags;
567 int timeout;
568 signed long time;
569
570 spin_lock_irqsave(&chip->lock, flags);
571 snd_cs4231_busy_wait(chip);
572 #if 0
573 printk("(1) timeout = %i\n", timeout);
574 #endif
575 #ifdef CONFIG_SND_DEBUG
576 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
577 snd_printk("mce_down [0x%lx] - auto calibration time out (0)\n", CS4231P(chip, REGSEL));
578 #endif
579 chip->mce_bit &= ~CS4231_MCE;
580 timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL));
581 __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL));
582 if (timeout == 0x80)
583 snd_printk("mce_down [0x%lx]: serious init problem - codec still busy\n", chip->port);
584 if ((timeout & CS4231_MCE) == 0) {
585 spin_unlock_irqrestore(&chip->lock, flags);
586 return;
587 }
588 snd_cs4231_busy_wait(chip);
589
590 /* calibration process */
591
592 for (timeout = 500; timeout > 0 && (snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) == 0; timeout--)
593 udelay(100);
594 if ((snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) == 0) {
595 snd_printd("cs4231_mce_down - auto calibration time out (1)\n");
596 spin_unlock_irqrestore(&chip->lock, flags);
597 return;
598 }
599 #if 0
600 printk("(2) timeout = %i, jiffies = %li\n", timeout, jiffies);
601 #endif
602 time = HZ / 4;
603 while (snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) {
604 spin_unlock_irqrestore(&chip->lock, flags);
605 if (time <= 0) {
606 snd_printk("mce_down - auto calibration time out (2)\n");
607 return;
608 }
609 set_current_state(TASK_INTERRUPTIBLE);
610 time = schedule_timeout(time);
611 spin_lock_irqsave(&chip->lock, flags);
612 }
613 #if 0
614 printk("(3) jiffies = %li\n", jiffies);
615 #endif
616 time = HZ / 10;
617 while (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) {
618 spin_unlock_irqrestore(&chip->lock, flags);
619 if (time <= 0) {
620 snd_printk("mce_down - auto calibration time out (3)\n");
621 return;
622 }
623 set_current_state(TASK_INTERRUPTIBLE);
624 time = schedule_timeout(time);
625 spin_lock_irqsave(&chip->lock, flags);
626 }
627 spin_unlock_irqrestore(&chip->lock, flags);
628 #if 0
629 printk("(4) jiffies = %li\n", jiffies);
630 snd_printk("mce_down - exit = 0x%x\n", __cs4231_readb(chip, CS4231P(chip, REGSEL)));
631 #endif
632 }
633
634 #if 0 /* Unused for now... */
635 static unsigned int snd_cs4231_get_count(unsigned char format, unsigned int size)
636 {
637 switch (format & 0xe0) {
638 case CS4231_LINEAR_16:
639 case CS4231_LINEAR_16_BIG:
640 size >>= 1;
641 break;
642 case CS4231_ADPCM_16:
643 return size >> 2;
644 }
645 if (format & CS4231_STEREO)
646 size >>= 1;
647 return size;
648 }
649 #endif
650
651 #ifdef EBUS_SUPPORT
652 static void snd_cs4231_ebus_advance_dma(struct ebus_dma_info *p, snd_pcm_substream_t *substream, unsigned int *periods_sent)
653 {
654 snd_pcm_runtime_t *runtime = substream->runtime;
655
656 while (1) {
657 unsigned int dma_size = snd_pcm_lib_period_bytes(substream);
658 unsigned int offset = dma_size * (*periods_sent);
659
660 if (dma_size >= (1 << 24))
661 BUG();
662
663 if (ebus_dma_request(p, runtime->dma_addr + offset, dma_size))
664 return;
665 #if 0
666 printk("ebus_advance: Sent period %u (size[%x] offset[%x])\n",
667 (*periods_sent), dma_size, offset);
668 #endif
669 (*periods_sent) = ((*periods_sent) + 1) % runtime->periods;
670 }
671 }
672 #endif
673
674 static void cs4231_dma_trigger(cs4231_t *chip, unsigned int what, int on)
675 {
676 #ifdef EBUS_SUPPORT
677 if (chip->flags & CS4231_FLAG_EBUS) {
678 if (what & CS4231_PLAYBACK_ENABLE) {
679 if (on) {
680 ebus_dma_prepare(&chip->eb2p, 0);
681 ebus_dma_enable(&chip->eb2p, 1);
682 snd_cs4231_ebus_advance_dma(&chip->eb2p,
683 chip->playback_substream,
684 &chip->p_periods_sent);
685 } else {
686 ebus_dma_enable(&chip->eb2p, 0);
687 }
688 }
689 if (what & CS4231_RECORD_ENABLE) {
690 if (on) {
691 ebus_dma_prepare(&chip->eb2c, 1);
692 ebus_dma_enable(&chip->eb2c, 1);
693 snd_cs4231_ebus_advance_dma(&chip->eb2c,
694 chip->capture_substream,
695 &chip->c_periods_sent);
696 } else {
697 ebus_dma_enable(&chip->eb2c, 0);
698 }
699 }
700 } else {
701 #endif
702 #ifdef SBUS_SUPPORT
703 #endif
704 #ifdef EBUS_SUPPORT
705 }
706 #endif
707 }
708
709 static int snd_cs4231_trigger(snd_pcm_substream_t *substream, int cmd)
710 {
711 cs4231_t *chip = snd_pcm_substream_chip(substream);
712 int result = 0;
713
714 switch (cmd) {
715 case SNDRV_PCM_TRIGGER_START:
716 case SNDRV_PCM_TRIGGER_STOP:
717 {
718 unsigned int what = 0;
719 snd_pcm_substream_t *s;
720 struct list_head *pos;
721 unsigned long flags;
722
723 snd_pcm_group_for_each(pos, substream) {
724 s = snd_pcm_group_substream_entry(pos);
725 if (s == chip->playback_substream) {
726 what |= CS4231_PLAYBACK_ENABLE;
727 snd_pcm_trigger_done(s, substream);
728 } else if (s == chip->capture_substream) {
729 what |= CS4231_RECORD_ENABLE;
730 snd_pcm_trigger_done(s, substream);
731 }
732 }
733
734 #if 0
735 printk("TRIGGER: what[%x] on(%d)\n",
736 what, (cmd == SNDRV_PCM_TRIGGER_START));
737 #endif
738
739 spin_lock_irqsave(&chip->lock, flags);
740 if (cmd == SNDRV_PCM_TRIGGER_START) {
741 cs4231_dma_trigger(chip, what, 1);
742 chip->image[CS4231_IFACE_CTRL] |= what;
743 if (what & CS4231_PLAYBACK_ENABLE) {
744 snd_cs4231_out(chip, CS4231_PLY_LWR_CNT, 0xff);
745 snd_cs4231_out(chip, CS4231_PLY_UPR_CNT, 0xff);
746 }
747 if (what & CS4231_RECORD_ENABLE) {
748 snd_cs4231_out(chip, CS4231_REC_LWR_CNT, 0xff);
749 snd_cs4231_out(chip, CS4231_REC_UPR_CNT, 0xff);
750 }
751 } else {
752 cs4231_dma_trigger(chip, what, 0);
753 chip->image[CS4231_IFACE_CTRL] &= ~what;
754 }
755 snd_cs4231_out(chip, CS4231_IFACE_CTRL,
756 chip->image[CS4231_IFACE_CTRL]);
757 spin_unlock_irqrestore(&chip->lock, flags);
758 break;
759 }
760 default:
761 result = -EINVAL;
762 break;
763 }
764 #if 0
765 snd_cs4231_debug(chip);
766 #endif
767 return result;
768 }
769
770 /*
771 * CODEC I/O
772 */
773
774 static unsigned char snd_cs4231_get_rate(unsigned int rate)
775 {
776 int i;
777
778 for (i = 0; i < 14; i++)
779 if (rate == rates[i])
780 return freq_bits[i];
781 // snd_BUG();
782 return freq_bits[13];
783 }
784
785 static unsigned char snd_cs4231_get_format(cs4231_t *chip, int format, int channels)
786 {
787 unsigned char rformat;
788
789 rformat = CS4231_LINEAR_8;
790 switch (format) {
791 case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break;
792 case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break;
793 case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break;
794 case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break;
795 case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break;
796 }
797 if (channels > 1)
798 rformat |= CS4231_STEREO;
799 #if 0
800 snd_printk("get_format: 0x%x (mode=0x%x)\n", format, mode);
801 #endif
802 return rformat;
803 }
804
805 static void snd_cs4231_calibrate_mute(cs4231_t *chip, int mute)
806 {
807 unsigned long flags;
808
809 mute = mute ? 1 : 0;
810 spin_lock_irqsave(&chip->lock, flags);
811 if (chip->calibrate_mute == mute) {
812 spin_unlock_irqrestore(&chip->lock, flags);
813 return;
814 }
815 if (!mute) {
816 snd_cs4231_dout(chip, CS4231_LEFT_INPUT,
817 chip->image[CS4231_LEFT_INPUT]);
818 snd_cs4231_dout(chip, CS4231_RIGHT_INPUT,
819 chip->image[CS4231_RIGHT_INPUT]);
820 snd_cs4231_dout(chip, CS4231_LOOPBACK,
821 chip->image[CS4231_LOOPBACK]);
822 }
823 snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT,
824 mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
825 snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT,
826 mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
827 snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT,
828 mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
829 snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT,
830 mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
831 snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT,
832 mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
833 snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT,
834 mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
835 snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN,
836 mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
837 snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN,
838 mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
839 snd_cs4231_dout(chip, CS4231_MONO_CTRL,
840 mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
841 chip->calibrate_mute = mute;
842 spin_unlock_irqrestore(&chip->lock, flags);
843 }
844
845 static void snd_cs4231_playback_format(cs4231_t *chip, snd_pcm_hw_params_t *params,
846 unsigned char pdfr)
847 {
848 unsigned long flags;
849
850 down(&chip->mce_mutex);
851 snd_cs4231_calibrate_mute(chip, 1);
852
853 snd_cs4231_mce_up(chip);
854
855 spin_lock_irqsave(&chip->lock, flags);
856 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
857 (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ?
858 (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) :
859 pdfr);
860 spin_unlock_irqrestore(&chip->lock, flags);
861
862 snd_cs4231_mce_down(chip);
863
864 snd_cs4231_calibrate_mute(chip, 0);
865 up(&chip->mce_mutex);
866 }
867
868 static void snd_cs4231_capture_format(cs4231_t *chip, snd_pcm_hw_params_t *params,
869 unsigned char cdfr)
870 {
871 unsigned long flags;
872
873 down(&chip->mce_mutex);
874 snd_cs4231_calibrate_mute(chip, 1);
875
876 snd_cs4231_mce_up(chip);
877
878 spin_lock_irqsave(&chip->lock, flags);
879 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
880 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
881 ((chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) |
882 (cdfr & 0x0f));
883 spin_unlock_irqrestore(&chip->lock, flags);
884 snd_cs4231_mce_down(chip);
885 snd_cs4231_mce_up(chip);
886 spin_lock_irqsave(&chip->lock, flags);
887 }
888 snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr);
889 spin_unlock_irqrestore(&chip->lock, flags);
890
891 snd_cs4231_mce_down(chip);
892
893 snd_cs4231_calibrate_mute(chip, 0);
894 up(&chip->mce_mutex);
895 }
896
897 /*
898 * Timer interface
899 */
900
901 static unsigned long snd_cs4231_timer_resolution(snd_timer_t *timer)
902 {
903 cs4231_t *chip = snd_timer_chip(timer);
904
905 return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
906 }
907
908 static int snd_cs4231_timer_start(snd_timer_t *timer)
909 {
910 unsigned long flags;
911 unsigned int ticks;
912 cs4231_t *chip = snd_timer_chip(timer);
913
914 spin_lock_irqsave(&chip->lock, flags);
915 ticks = timer->sticks;
916 if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
917 (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
918 (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
919 snd_cs4231_out(chip, CS4231_TIMER_HIGH,
920 chip->image[CS4231_TIMER_HIGH] =
921 (unsigned char) (ticks >> 8));
922 snd_cs4231_out(chip, CS4231_TIMER_LOW,
923 chip->image[CS4231_TIMER_LOW] =
924 (unsigned char) ticks);
925 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
926 chip->image[CS4231_ALT_FEATURE_1] | CS4231_TIMER_ENABLE);
927 }
928 spin_unlock_irqrestore(&chip->lock, flags);
929
930 return 0;
931 }
932
933 static int snd_cs4231_timer_stop(snd_timer_t *timer)
934 {
935 unsigned long flags;
936 cs4231_t *chip = snd_timer_chip(timer);
937
938 spin_lock_irqsave(&chip->lock, flags);
939 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
940 chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE);
941 spin_unlock_irqrestore(&chip->lock, flags);
942
943 return 0;
944 }
945
946 static void snd_cs4231_init(cs4231_t *chip)
947 {
948 unsigned long flags;
949
950 snd_cs4231_mce_down(chip);
951
952 #ifdef SNDRV_DEBUG_MCE
953 snd_printk("init: (1)\n");
954 #endif
955 snd_cs4231_mce_up(chip);
956 spin_lock_irqsave(&chip->lock, flags);
957 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
958 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO |
959 CS4231_CALIB_MODE);
960 chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
961 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
962 spin_unlock_irqrestore(&chip->lock, flags);
963 snd_cs4231_mce_down(chip);
964
965 #ifdef SNDRV_DEBUG_MCE
966 snd_printk("init: (2)\n");
967 #endif
968
969 snd_cs4231_mce_up(chip);
970 spin_lock_irqsave(&chip->lock, flags);
971 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);
972 spin_unlock_irqrestore(&chip->lock, flags);
973 snd_cs4231_mce_down(chip);
974
975 #ifdef SNDRV_DEBUG_MCE
976 snd_printk("init: (3) - afei = 0x%x\n", chip->image[CS4231_ALT_FEATURE_1]);
977 #endif
978
979 spin_lock_irqsave(&chip->lock, flags);
980 snd_cs4231_out(chip, CS4231_ALT_FEATURE_2, chip->image[CS4231_ALT_FEATURE_2]);
981 spin_unlock_irqrestore(&chip->lock, flags);
982
983 snd_cs4231_mce_up(chip);
984 spin_lock_irqsave(&chip->lock, flags);
985 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT]);
986 spin_unlock_irqrestore(&chip->lock, flags);
987 snd_cs4231_mce_down(chip);
988
989 #ifdef SNDRV_DEBUG_MCE
990 snd_printk("init: (4)\n");
991 #endif
992
993 snd_cs4231_mce_up(chip);
994 spin_lock_irqsave(&chip->lock, flags);
995 snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]);
996 spin_unlock_irqrestore(&chip->lock, flags);
997 snd_cs4231_mce_down(chip);
998
999 #ifdef SNDRV_DEBUG_MCE
1000 snd_printk("init: (5)\n");
1001 #endif
1002 }
1003
1004 static int snd_cs4231_open(cs4231_t *chip, unsigned int mode)
1005 {
1006 unsigned long flags;
1007
1008 down(&chip->open_mutex);
1009 if ((chip->mode & mode)) {
1010 up(&chip->open_mutex);
1011 return -EAGAIN;
1012 }
1013 if (chip->mode & CS4231_MODE_OPEN) {
1014 chip->mode |= mode;
1015 up(&chip->open_mutex);
1016 return 0;
1017 }
1018 /* ok. now enable and ack CODEC IRQ */
1019 spin_lock_irqsave(&chip->lock, flags);
1020 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
1021 CS4231_RECORD_IRQ |
1022 CS4231_TIMER_IRQ);
1023 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
1024 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
1025 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
1026
1027 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
1028 CS4231_RECORD_IRQ |
1029 CS4231_TIMER_IRQ);
1030 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
1031 spin_unlock_irqrestore(&chip->lock, flags);
1032
1033 chip->mode = mode;
1034 up(&chip->open_mutex);
1035 return 0;
1036 }
1037
1038 static void snd_cs4231_close(cs4231_t *chip, unsigned int mode)
1039 {
1040 unsigned long flags;
1041
1042 down(&chip->open_mutex);
1043 chip->mode &= ~mode;
1044 if (chip->mode & CS4231_MODE_OPEN) {
1045 up(&chip->open_mutex);
1046 return;
1047 }
1048 snd_cs4231_calibrate_mute(chip, 1);
1049
1050 /* disable IRQ */
1051 spin_lock_irqsave(&chip->lock, flags);
1052 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
1053 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
1054 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
1055
1056 /* now disable record & playback */
1057
1058 if (chip->image[CS4231_IFACE_CTRL] &
1059 (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
1060 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
1061 spin_unlock_irqrestore(&chip->lock, flags);
1062 snd_cs4231_mce_up(chip);
1063 spin_lock_irqsave(&chip->lock, flags);
1064 chip->image[CS4231_IFACE_CTRL] &=
1065 ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
1066 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
1067 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
1068 spin_unlock_irqrestore(&chip->lock, flags);
1069 snd_cs4231_mce_down(chip);
1070 spin_lock_irqsave(&chip->lock, flags);
1071 }
1072
1073 /* clear IRQ again */
1074 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
1075 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
1076 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
1077 spin_unlock_irqrestore(&chip->lock, flags);
1078
1079 snd_cs4231_calibrate_mute(chip, 0);
1080
1081 chip->mode = 0;
1082 up(&chip->open_mutex);
1083 }
1084
1085 /*
1086 * timer open/close
1087 */
1088
1089 static int snd_cs4231_timer_open(snd_timer_t *timer)
1090 {
1091 cs4231_t *chip = snd_timer_chip(timer);
1092 snd_cs4231_open(chip, CS4231_MODE_TIMER);
1093 return 0;
1094 }
1095
1096 static int snd_cs4231_timer_close(snd_timer_t * timer)
1097 {
1098 cs4231_t *chip = snd_timer_chip(timer);
1099 snd_cs4231_close(chip, CS4231_MODE_TIMER);
1100 return 0;
1101 }
1102
1103 static struct _snd_timer_hardware snd_cs4231_timer_table =
1104 {
1105 .flags = SNDRV_TIMER_HW_AUTO,
1106 .resolution = 9945,
1107 .ticks = 65535,
1108 .open = snd_cs4231_timer_open,
1109 .close = snd_cs4231_timer_close,
1110 .c_resolution = snd_cs4231_timer_resolution,
1111 .start = snd_cs4231_timer_start,
1112 .stop = snd_cs4231_timer_stop,
1113 };
1114
1115 /*
1116 * ok.. exported functions..
1117 */
1118
1119 static int snd_cs4231_playback_hw_params(snd_pcm_substream_t *substream,
1120 snd_pcm_hw_params_t *hw_params)
1121 {
1122 cs4231_t *chip = snd_pcm_substream_chip(substream);
1123 unsigned char new_pdfr;
1124 int err;
1125
1126 if ((err = snd_pcm_lib_malloc_pages(substream,
1127 params_buffer_bytes(hw_params))) < 0)
1128 return err;
1129 new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params),
1130 params_channels(hw_params)) |
1131 snd_cs4231_get_rate(params_rate(hw_params));
1132 snd_cs4231_playback_format(chip, hw_params, new_pdfr);
1133
1134 return 0;
1135 }
1136
1137 static int snd_cs4231_playback_hw_free(snd_pcm_substream_t *substream)
1138 {
1139 return snd_pcm_lib_free_pages(substream);
1140 }
1141
1142 static int snd_cs4231_playback_prepare(snd_pcm_substream_t *substream)
1143 {
1144 cs4231_t *chip = snd_pcm_substream_chip(substream);
1145 unsigned long flags;
1146
1147 spin_lock_irqsave(&chip->lock, flags);
1148 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
1149 CS4231_PLAYBACK_PIO);
1150 spin_unlock_irqrestore(&chip->lock, flags);
1151
1152 return 0;
1153 }
1154
1155 static int snd_cs4231_capture_hw_params(snd_pcm_substream_t *substream,
1156 snd_pcm_hw_params_t *hw_params)
1157 {
1158 cs4231_t *chip = snd_pcm_substream_chip(substream);
1159 unsigned char new_cdfr;
1160 int err;
1161
1162 if ((err = snd_pcm_lib_malloc_pages(substream,
1163 params_buffer_bytes(hw_params))) < 0)
1164 return err;
1165 new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params),
1166 params_channels(hw_params)) |
1167 snd_cs4231_get_rate(params_rate(hw_params));
1168 snd_cs4231_capture_format(chip, hw_params, new_cdfr);
1169
1170 return 0;
1171 }
1172
1173 static int snd_cs4231_capture_hw_free(snd_pcm_substream_t *substream)
1174 {
1175 return snd_pcm_lib_free_pages(substream);
1176 }
1177
1178 static int snd_cs4231_capture_prepare(snd_pcm_substream_t *substream)
1179 {
1180 cs4231_t *chip = snd_pcm_substream_chip(substream);
1181 unsigned long flags;
1182
1183 spin_lock_irqsave(&chip->lock, flags);
1184 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE |
1185 CS4231_RECORD_PIO);
1186
1187 spin_unlock_irqrestore(&chip->lock, flags);
1188
1189 return 0;
1190 }
1191
1192 static void snd_cs4231_overrange(cs4231_t *chip)
1193 {
1194 unsigned long flags;
1195 unsigned char res;
1196
1197 spin_lock_irqsave(&chip->lock, flags);
1198 res = snd_cs4231_in(chip, CS4231_TEST_INIT);
1199 spin_unlock_irqrestore(&chip->lock, flags);
1200
1201 if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */
1202 chip->capture_substream->runtime->overrange++;
1203 }
1204
1205 static void snd_cs4231_generic_interrupt(cs4231_t *chip)
1206 {
1207 unsigned long flags;
1208 unsigned char status;
1209
1210 status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
1211 if (!status)
1212 return;
1213
1214 if (status & CS4231_TIMER_IRQ) {
1215 if (chip->timer)
1216 snd_timer_interrupt(chip->timer, chip->timer->sticks);
1217 }
1218 if (status & CS4231_PLAYBACK_IRQ)
1219 snd_pcm_period_elapsed(chip->playback_substream);
1220 if (status & CS4231_RECORD_IRQ) {
1221 snd_cs4231_overrange(chip);
1222 snd_pcm_period_elapsed(chip->capture_substream);
1223 }
1224
1225 /* ACK the CS4231 interrupt. */
1226 spin_lock_irqsave(&chip->lock, flags);
1227 snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
1228 spin_unlock_irqrestore(&chip->lock, flags);
1229 }
1230
1231 #ifdef SBUS_SUPPORT
1232 static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1233 {
1234 cs4231_t *chip = snd_magic_cast(cs4231_t, dev_id, return);
1235 u32 csr;
1236
1237 csr = sbus_readl(chip->port + APCCSR);
1238 if (!(csr & (APC_INT_PENDING |
1239 APC_PLAY_INT |
1240 APC_CAPT_INT |
1241 APC_GENL_INT |
1242 APC_XINT_PEMP |
1243 APC_XINT_CEMP)))
1244 return IRQ_NONE;
1245
1246 /* ACK the APC interrupt. */
1247 sbus_writel(csr, chip->port + APCCSR);
1248
1249 snd_cs4231_generic_interrupt(chip);
1250
1251 return IRQ_HANDLED;
1252 }
1253 #endif
1254
1255 #ifdef EBUS_SUPPORT
1256 static void snd_cs4231_ebus_play_callback(struct ebus_dma_info *p, int event, void *cookie)
1257 {
1258 cs4231_t *chip = snd_magic_cast(cs4231_t, cookie, return);
1259
1260 if (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) {
1261 snd_pcm_period_elapsed(chip->playback_substream);
1262 snd_cs4231_ebus_advance_dma(p, chip->playback_substream,
1263 &chip->p_periods_sent);
1264 }
1265 }
1266
1267 static void snd_cs4231_ebus_capture_callback(struct ebus_dma_info *p, int event, void *cookie)
1268 {
1269 cs4231_t *chip = snd_magic_cast(cs4231_t, cookie, return);
1270
1271 if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) {
1272 snd_pcm_period_elapsed(chip->capture_substream);
1273 snd_cs4231_ebus_advance_dma(p, chip->capture_substream,
1274 &chip->c_periods_sent);
1275 }
1276 }
1277 #endif
1278
1279 static snd_pcm_uframes_t snd_cs4231_playback_pointer(snd_pcm_substream_t *substream)
1280 {
1281 cs4231_t *chip = snd_pcm_substream_chip(substream);
1282 size_t ptr, residue, period_bytes;
1283
1284 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
1285 return 0;
1286 period_bytes = snd_pcm_lib_period_bytes(substream);
1287 ptr = period_bytes * chip->p_periods_sent;
1288 #ifdef EBUS_SUPPORT
1289 if (chip->flags & CS4231_FLAG_EBUS) {
1290 residue = ebus_dma_residue(&chip->eb2p);
1291 } else {
1292 #endif
1293 #ifdef SBUS_SUPPORT
1294 residue = sbus_readl(chip->port + APCPC);
1295 #endif
1296 #ifdef EBUS_SUPPORT
1297 }
1298 #endif
1299 ptr += (period_bytes - residue);
1300 return bytes_to_frames(substream->runtime, ptr);
1301 }
1302
1303 static snd_pcm_uframes_t snd_cs4231_capture_pointer(snd_pcm_substream_t * substream)
1304 {
1305 cs4231_t *chip = snd_pcm_substream_chip(substream);
1306 size_t ptr, residue, period_bytes;
1307
1308 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
1309 return 0;
1310 period_bytes = snd_pcm_lib_period_bytes(substream);
1311 ptr = period_bytes * chip->c_periods_sent;
1312 #ifdef EBUS_SUPPORT
1313 if (chip->flags & CS4231_FLAG_EBUS) {
1314 residue = ebus_dma_residue(&chip->eb2c);
1315 } else {
1316 #endif
1317 #ifdef SBUS_SUPPORT
1318 residue = sbus_readl(chip->port + APCCC);
1319 #endif
1320 #ifdef EBUS_SUPPORT
1321 }
1322 #endif
1323 ptr += (period_bytes - residue);
1324 return bytes_to_frames(substream->runtime, ptr);
1325 }
1326
1327 /*
1328
1329 */
1330
1331 static int snd_cs4231_probe(cs4231_t *chip)
1332 {
1333 unsigned long flags;
1334 int i, id, vers;
1335 unsigned char *ptr;
1336
1337 #if 0
1338 snd_cs4231_debug(chip);
1339 #endif
1340 id = vers = 0;
1341 for (i = 0; i < 50; i++) {
1342 mb();
1343 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
1344 udelay(2000);
1345 else {
1346 spin_lock_irqsave(&chip->lock, flags);
1347 snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
1348 id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f;
1349 vers = snd_cs4231_in(chip, CS4231_VERSION);
1350 spin_unlock_irqrestore(&chip->lock, flags);
1351 if (id == 0x0a)
1352 break; /* this is valid value */
1353 }
1354 }
1355 snd_printdd("cs4231: port = 0x%lx, id = 0x%x\n", chip->port, id);
1356 if (id != 0x0a)
1357 return -ENODEV; /* no valid device found */
1358
1359 spin_lock_irqsave(&chip->lock, flags);
1360
1361
1362 /* Reset DMA engine. */
1363 #ifdef EBUS_SUPPORT
1364 if (chip->flags & CS4231_FLAG_EBUS) {
1365 /* Done by ebus_dma_register */
1366 } else {
1367 #endif
1368 #ifdef SBUS_SUPPORT
1369 sbus_writel(APC_CHIP_RESET, chip->port + APCCSR);
1370 sbus_writel(0x00, chip->port + APCCSR);
1371 sbus_writel(sbus_readl(chip->port + APCCSR) | APC_CDC_RESET,
1372 chip->port + APCCSR);
1373
1374 udelay(20);
1375
1376 sbus_writel(sbus_readl(chip->port + APCCSR) & ~APC_CDC_RESET,
1377 chip->port + APCCSR);
1378 sbus_writel(sbus_readl(chip->port + APCCSR) | (APC_XINT_ENA |
1379 APC_XINT_PENA |
1380 APC_XINT_CENA),
1381 chip->port + APCCSR);
1382 #endif
1383 #ifdef EBUS_SUPPORT
1384 }
1385 #endif
1386
1387 __cs4231_readb(chip, CS4231P(chip, STATUS)); /* clear any pendings IRQ */
1388 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS));
1389 mb();
1390
1391 spin_unlock_irqrestore(&chip->lock, flags);
1392
1393 chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
1394 chip->image[CS4231_IFACE_CTRL] =
1395 chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA;
1396 chip->image[CS4231_ALT_FEATURE_1] = 0x80;
1397 chip->image[CS4231_ALT_FEATURE_2] = 0x01;
1398 if (vers & 0x20)
1399 chip->image[CS4231_ALT_FEATURE_2] |= 0x02;
1400
1401 ptr = (unsigned char *) &chip->image;
1402
1403 snd_cs4231_mce_down(chip);
1404
1405 spin_lock_irqsave(&chip->lock, flags);
1406
1407 for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */
1408 snd_cs4231_out(chip, i, *ptr++);
1409
1410 spin_unlock_irqrestore(&chip->lock, flags);
1411
1412 snd_cs4231_mce_up(chip);
1413
1414 snd_cs4231_mce_down(chip);
1415
1416 mdelay(2);
1417
1418 return 0; /* all things are ok.. */
1419 }
1420
1421 static snd_pcm_hardware_t snd_cs4231_playback =
1422 {
1423 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1424 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1425 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
1426 SNDRV_PCM_FMTBIT_IMA_ADPCM |
1427 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |
1428 SNDRV_PCM_FMTBIT_S16_BE),
1429 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1430 .rate_min = 5510,
1431 .rate_max = 48000,
1432 .channels_min = 1,
1433 .channels_max = 2,
1434 .buffer_bytes_max = (32*1024),
1435 .period_bytes_min = 4096,
1436 .period_bytes_max = (32*1024),
1437 .periods_min = 1,
1438 .periods_max = 1024,
1439 };
1440
1441 static snd_pcm_hardware_t snd_cs4231_capture =
1442 {
1443 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1444 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1445 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
1446 SNDRV_PCM_FMTBIT_IMA_ADPCM |
1447 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |
1448 SNDRV_PCM_FMTBIT_S16_BE),
1449 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1450 .rate_min = 5510,
1451 .rate_max = 48000,
1452 .channels_min = 1,
1453 .channels_max = 2,
1454 .buffer_bytes_max = (32*1024),
1455 .period_bytes_min = 4096,
1456 .period_bytes_max = (32*1024),
1457 .periods_min = 1,
1458 .periods_max = 1024,
1459 };
1460
1461 static int snd_cs4231_playback_open(snd_pcm_substream_t *substream)
1462 {
1463 cs4231_t *chip = snd_pcm_substream_chip(substream);
1464 snd_pcm_runtime_t *runtime = substream->runtime;
1465 int err;
1466
1467 runtime->hw = snd_cs4231_playback;
1468
1469 if ((err = snd_cs4231_open(chip, CS4231_MODE_PLAY)) < 0) {
1470 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1471 return err;
1472 }
1473 chip->playback_substream = substream;
1474 chip->p_periods_sent = 0;
1475 snd_pcm_set_sync(substream);
1476 snd_cs4231_xrate(runtime);
1477
1478 return 0;
1479 }
1480
1481 static int snd_cs4231_capture_open(snd_pcm_substream_t *substream)
1482 {
1483 cs4231_t *chip = snd_pcm_substream_chip(substream);
1484 snd_pcm_runtime_t *runtime = substream->runtime;
1485 int err;
1486
1487 runtime->hw = snd_cs4231_capture;
1488
1489 if ((err = snd_cs4231_open(chip, CS4231_MODE_RECORD)) < 0) {
1490 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1491 return err;
1492 }
1493 chip->capture_substream = substream;
1494 chip->c_periods_sent = 0;
1495 snd_pcm_set_sync(substream);
1496 snd_cs4231_xrate(runtime);
1497
1498 return 0;
1499 }
1500
1501 static int snd_cs4231_playback_close(snd_pcm_substream_t *substream)
1502 {
1503 cs4231_t *chip = snd_pcm_substream_chip(substream);
1504
1505 chip->playback_substream = NULL;
1506 snd_cs4231_close(chip, CS4231_MODE_PLAY);
1507
1508 return 0;
1509 }
1510
1511 static int snd_cs4231_capture_close(snd_pcm_substream_t *substream)
1512 {
1513 cs4231_t *chip = snd_pcm_substream_chip(substream);
1514
1515 chip->capture_substream = NULL;
1516 snd_cs4231_close(chip, CS4231_MODE_RECORD);
1517
1518 return 0;
1519 }
1520
1521 /* XXX We can do some power-management, in particular on EBUS using
1522 * XXX the audio AUXIO register...
1523 */
1524
1525 static snd_pcm_ops_t snd_cs4231_playback_ops = {
1526 .open = snd_cs4231_playback_open,
1527 .close = snd_cs4231_playback_close,
1528 .ioctl = snd_pcm_lib_ioctl,
1529 .hw_params = snd_cs4231_playback_hw_params,
1530 .hw_free = snd_cs4231_playback_hw_free,
1531 .prepare = snd_cs4231_playback_prepare,
1532 .trigger = snd_cs4231_trigger,
1533 .pointer = snd_cs4231_playback_pointer,
1534 };
1535
1536 static snd_pcm_ops_t snd_cs4231_capture_ops = {
1537 .open = snd_cs4231_capture_open,
1538 .close = snd_cs4231_capture_close,
1539 .ioctl = snd_pcm_lib_ioctl,
1540 .hw_params = snd_cs4231_capture_hw_params,
1541 .hw_free = snd_cs4231_capture_hw_free,
1542 .prepare = snd_cs4231_capture_prepare,
1543 .trigger = snd_cs4231_trigger,
1544 .pointer = snd_cs4231_capture_pointer,
1545 };
1546
1547 static void snd_cs4231_pcm_free(snd_pcm_t *pcm)
1548 {
1549 cs4231_t *chip = snd_magic_cast(cs4231_t, pcm->private_data, return);
1550 chip->pcm = NULL;
1551 snd_pcm_lib_preallocate_free_for_all(pcm);
1552 }
1553
1554 int snd_cs4231_pcm(cs4231_t *chip)
1555 {
1556 snd_pcm_t *pcm;
1557 int err;
1558
1559 if ((err = snd_pcm_new(chip->card, "CS4231", 0, 1, 1, &pcm)) < 0)
1560 return err;
1561
1562 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4231_playback_ops);
1563 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4231_capture_ops);
1564
1565 /* global setup */
1566 pcm->private_data = chip;
1567 pcm->private_free = snd_cs4231_pcm_free;
1568 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1569 strcpy(pcm->name, "CS4231");
1570
1571 #ifdef EBUS_SUPPORT
1572 if (chip->flags & CS4231_FLAG_EBUS) {
1573 snd_pcm_lib_preallocate_pci_pages_for_all(chip->dev_u.pdev, pcm,
1574 64*1024, 128*1024);
1575 } else {
1576 #endif
1577 #ifdef SBUS_SUPPORT
1578 snd_pcm_lib_preallocate_sbus_pages_for_all(chip->dev_u.sdev, pcm,
1579 64*1024, 128*1024);
1580 #endif
1581 #ifdef EBUS_SUPPORT
1582 }
1583 #endif
1584
1585 chip->pcm = pcm;
1586
1587 return 0;
1588 }
1589
1590 static void snd_cs4231_timer_free(snd_timer_t *timer)
1591 {
1592 cs4231_t *chip = snd_magic_cast(cs4231_t, timer->private_data, return);
1593 chip->timer = NULL;
1594 }
1595
1596 int snd_cs4231_timer(cs4231_t *chip)
1597 {
1598 snd_timer_t *timer;
1599 snd_timer_id_t tid;
1600 int err;
1601
1602 /* Timer initialization */
1603 tid.dev_class = SNDRV_TIMER_CLASS_CARD;
1604 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
1605 tid.card = chip->card->number;
1606 tid.device = 0;
1607 tid.subdevice = 0;
1608 if ((err = snd_timer_new(chip->card, "CS4231", &tid, &timer)) < 0)
1609 return err;
1610 strcpy(timer->name, "CS4231");
1611 timer->private_data = chip;
1612 timer->private_free = snd_cs4231_timer_free;
1613 timer->hw = snd_cs4231_timer_table;
1614 chip->timer = timer;
1615
1616 return 0;
1617 }
1618
1619 /*
1620 * MIXER part
1621 */
1622
1623 static int snd_cs4231_info_mux(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1624 {
1625 static char *texts[4] = {
1626 "Line", "CD", "Mic", "Mix"
1627 };
1628 cs4231_t *chip = snd_kcontrol_chip(kcontrol);
1629
1630 snd_assert(chip->card != NULL, return -EINVAL);
1631 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1632 uinfo->count = 2;
1633 uinfo->value.enumerated.items = 4;
1634 if (uinfo->value.enumerated.item > 3)
1635 uinfo->value.enumerated.item = 3;
1636 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1637
1638 return 0;
1639 }
1640
1641 static int snd_cs4231_get_mux(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
1642 {
1643 cs4231_t *chip = snd_kcontrol_chip(kcontrol);
1644 unsigned long flags;
1645
1646 spin_lock_irqsave(&chip->lock, flags);
1647 ucontrol->value.enumerated.item[0] =
1648 (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
1649 ucontrol->value.enumerated.item[1] =
1650 (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
1651 spin_unlock_irqrestore(&chip->lock, flags);
1652
1653 return 0;
1654 }
1655
1656 static int snd_cs4231_put_mux(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
1657 {
1658 cs4231_t *chip = snd_kcontrol_chip(kcontrol);
1659 unsigned long flags;
1660 unsigned short left, right;
1661 int change;
1662
1663 if (ucontrol->value.enumerated.item[0] > 3 ||
1664 ucontrol->value.enumerated.item[1] > 3)
1665 return -EINVAL;
1666 left = ucontrol->value.enumerated.item[0] << 6;
1667 right = ucontrol->value.enumerated.item[1] << 6;
1668
1669 spin_lock_irqsave(&chip->lock, flags);
1670
1671 left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
1672 right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
1673 change = left != chip->image[CS4231_LEFT_INPUT] ||
1674 right != chip->image[CS4231_RIGHT_INPUT];
1675 snd_cs4231_out(chip, CS4231_LEFT_INPUT, left);
1676 snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right);
1677
1678 spin_unlock_irqrestore(&chip->lock, flags);
1679
1680 return change;
1681 }
1682
1683 int snd_cs4231_info_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1684 {
1685 int mask = (kcontrol->private_value >> 16) & 0xff;
1686
1687 uinfo->type = (mask == 1) ?
1688 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1689 uinfo->count = 1;
1690 uinfo->value.integer.min = 0;
1691 uinfo->value.integer.max = mask;
1692
1693 return 0;
1694 }
1695
1696 int snd_cs4231_get_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
1697 {
1698 cs4231_t *chip = snd_kcontrol_chip(kcontrol);
1699 unsigned long flags;
1700 int reg = kcontrol->private_value & 0xff;
1701 int shift = (kcontrol->private_value >> 8) & 0xff;
1702 int mask = (kcontrol->private_value >> 16) & 0xff;
1703 int invert = (kcontrol->private_value >> 24) & 0xff;
1704
1705 spin_lock_irqsave(&chip->lock, flags);
1706
1707 ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
1708
1709 spin_unlock_irqrestore(&chip->lock, flags);
1710
1711 if (invert)
1712 ucontrol->value.integer.value[0] =
1713 (mask - ucontrol->value.integer.value[0]);
1714
1715 return 0;
1716 }
1717
1718 int snd_cs4231_put_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
1719 {
1720 cs4231_t *chip = snd_kcontrol_chip(kcontrol);
1721 unsigned long flags;
1722 int reg = kcontrol->private_value & 0xff;
1723 int shift = (kcontrol->private_value >> 8) & 0xff;
1724 int mask = (kcontrol->private_value >> 16) & 0xff;
1725 int invert = (kcontrol->private_value >> 24) & 0xff;
1726 int change;
1727 unsigned short val;
1728
1729 val = (ucontrol->value.integer.value[0] & mask);
1730 if (invert)
1731 val = mask - val;
1732 val <<= shift;
1733
1734 spin_lock_irqsave(&chip->lock, flags);
1735
1736 val = (chip->image[reg] & ~(mask << shift)) | val;
1737 change = val != chip->image[reg];
1738 snd_cs4231_out(chip, reg, val);
1739
1740 spin_unlock_irqrestore(&chip->lock, flags);
1741
1742 return change;
1743 }
1744
1745 int snd_cs4231_info_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1746 {
1747 int mask = (kcontrol->private_value >> 24) & 0xff;
1748
1749 uinfo->type = mask == 1 ?
1750 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1751 uinfo->count = 2;
1752 uinfo->value.integer.min = 0;
1753 uinfo->value.integer.max = mask;
1754
1755 return 0;
1756 }
1757
1758 int snd_cs4231_get_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
1759 {
1760 cs4231_t *chip = snd_kcontrol_chip(kcontrol);
1761 unsigned long flags;
1762 int left_reg = kcontrol->private_value & 0xff;
1763 int right_reg = (kcontrol->private_value >> 8) & 0xff;
1764 int shift_left = (kcontrol->private_value >> 16) & 0x07;
1765 int shift_right = (kcontrol->private_value >> 19) & 0x07;
1766 int mask = (kcontrol->private_value >> 24) & 0xff;
1767 int invert = (kcontrol->private_value >> 22) & 1;
1768
1769 spin_lock_irqsave(&chip->lock, flags);
1770
1771 ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
1772 ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
1773
1774 spin_unlock_irqrestore(&chip->lock, flags);
1775
1776 if (invert) {
1777 ucontrol->value.integer.value[0] =
1778 (mask - ucontrol->value.integer.value[0]);
1779 ucontrol->value.integer.value[1] =
1780 (mask - ucontrol->value.integer.value[1]);
1781 }
1782
1783 return 0;
1784 }
1785
1786 int snd_cs4231_put_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
1787 {
1788 cs4231_t *chip = snd_kcontrol_chip(kcontrol);
1789 unsigned long flags;
1790 int left_reg = kcontrol->private_value & 0xff;
1791 int right_reg = (kcontrol->private_value >> 8) & 0xff;
1792 int shift_left = (kcontrol->private_value >> 16) & 0x07;
1793 int shift_right = (kcontrol->private_value >> 19) & 0x07;
1794 int mask = (kcontrol->private_value >> 24) & 0xff;
1795 int invert = (kcontrol->private_value >> 22) & 1;
1796 int change;
1797 unsigned short val1, val2;
1798
1799 val1 = ucontrol->value.integer.value[0] & mask;
1800 val2 = ucontrol->value.integer.value[1] & mask;
1801 if (invert) {
1802 val1 = mask - val1;
1803 val2 = mask - val2;
1804 }
1805 val1 <<= shift_left;
1806 val2 <<= shift_right;
1807
1808 spin_lock_irqsave(&chip->lock, flags);
1809
1810 val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
1811 val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
1812 change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg];
1813 snd_cs4231_out(chip, left_reg, val1);
1814 snd_cs4231_out(chip, right_reg, val2);
1815
1816 spin_unlock_irqrestore(&chip->lock, flags);
1817
1818 return change;
1819 }
1820
1821 #define CS4231_CONTROLS (sizeof(snd_cs4231_controls)/sizeof(snd_kcontrol_new_t))
1822
1823 #define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
1824 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1825 .info = snd_cs4231_info_single, \
1826 .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \
1827 .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
1828
1829 #define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
1830 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1831 .info = snd_cs4231_info_double, \
1832 .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \
1833 .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
1834
1835 static snd_kcontrol_new_t snd_cs4231_controls[] = {
1836 CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
1837 CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
1838 CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
1839 CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
1840 CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
1841 CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
1842 CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
1843 CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
1844 CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1),
1845 CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
1846 CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1),
1847 CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0),
1848 CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
1849 {
1850 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1851 .name = "Capture Source",
1852 .info = snd_cs4231_info_mux,
1853 .get = snd_cs4231_get_mux,
1854 .put = snd_cs4231_put_mux,
1855 },
1856 CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
1857 CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
1858 CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1),
1859 /* SPARC specific uses of XCTL{0,1} general purpose outputs. */
1860 CS4231_SINGLE("Line Out Switch", 0, CS4231_PIN_CTRL, 6, 1, 1),
1861 CS4231_SINGLE("Headphone Out Switch", 0, CS4231_PIN_CTRL, 7, 1, 1)
1862 };
1863
1864 int snd_cs4231_mixer(cs4231_t *chip)
1865 {
1866 snd_card_t *card;
1867 int err, idx;
1868
1869 snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL);
1870
1871 card = chip->card;
1872
1873 strcpy(card->mixername, chip->pcm->name);
1874
1875 for (idx = 0; idx < CS4231_CONTROLS; idx++) {
1876 if ((err = snd_ctl_add(card,
1877 snd_ctl_new1(&snd_cs4231_controls[idx],
1878 chip))) < 0)
1879 return err;
1880 }
1881 return 0;
1882 }
1883
1884 static int dev;
1885
1886 static int cs4231_attach_begin(snd_card_t **rcard)
1887 {
1888 snd_card_t *card;
1889
1890 *rcard = NULL;
1891
1892 if (dev >= SNDRV_CARDS)
1893 return -ENODEV;
1894
1895 if (!enable[dev]) {
1896 dev++;
1897 return -ENOENT;
1898 }
1899
1900 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1901 if (card == NULL)
1902 return -ENOMEM;
1903
1904 strcpy(card->driver, "CS4231");
1905 strcpy(card->shortname, "Sun CS4231");
1906
1907 *rcard = card;
1908 return 0;
1909 }
1910
1911 static int cs4231_attach_finish(snd_card_t *card, cs4231_t *chip)
1912 {
1913 int err;
1914
1915 if ((err = snd_cs4231_pcm(chip)) < 0)
1916 goto out_err;
1917
1918 if ((err = snd_cs4231_mixer(chip)) < 0)
1919 goto out_err;
1920
1921 if ((err = snd_cs4231_timer(chip)) < 0)
1922 goto out_err;
1923
1924 if ((err = snd_card_register(card)) < 0)
1925 goto out_err;
1926
1927 chip->next = cs4231_list;
1928 cs4231_list = chip;
1929
1930 dev++;
1931 return 0;
1932
1933 out_err:
1934 snd_card_free(card);
1935 return err;
1936 }
1937
1938 #ifdef SBUS_SUPPORT
1939 static int snd_cs4231_sbus_free(cs4231_t *chip)
1940 {
1941 if (chip->irq[0])
1942 free_irq(chip->irq[0], chip);
1943
1944 if (chip->port)
1945 sbus_iounmap(chip->port, chip->regs_size);
1946
1947 if (chip->timer)
1948 snd_device_free(chip->card, chip->timer);
1949
1950 snd_magic_kfree(chip);
1951
1952 return 0;
1953 }
1954
1955 static int snd_cs4231_sbus_dev_free(snd_device_t *device)
1956 {
1957 cs4231_t *cp = snd_magic_cast(cs4231_t, device->device_data, return -ENXIO);
1958
1959 return snd_cs4231_sbus_free(cp);
1960 }
1961
1962 static snd_device_ops_t snd_cs4231_sbus_dev_ops = {
1963 .dev_free = snd_cs4231_sbus_dev_free,
1964 };
1965
1966 static int __init snd_cs4231_sbus_create(snd_card_t *card,
1967 struct sbus_dev *sdev,
1968 int dev,
1969 cs4231_t **rchip)
1970 {
1971 cs4231_t *chip;
1972 int err;
1973
1974 *rchip = NULL;
1975 chip = snd_magic_kcalloc(cs4231_t, 0, GFP_KERNEL);
1976 if (chip == NULL)
1977 return -ENOMEM;
1978
1979 spin_lock_init(&chip->lock);
1980 init_MUTEX(&chip->mce_mutex);
1981 init_MUTEX(&chip->open_mutex);
1982 chip->card = card;
1983 chip->dev_u.sdev = sdev;
1984 chip->regs_size = sdev->reg_addrs[0].reg_size;
1985 memcpy(&chip->image, &snd_cs4231_original_image,
1986 sizeof(snd_cs4231_original_image));
1987
1988 chip->port = sbus_ioremap(&sdev->resource[0], 0,
1989 chip->regs_size, "cs4231");
1990 if (!chip->port) {
1991 snd_printk("cs4231-%d: Unable to map chip registers.\n", dev);
1992 return -EIO;
1993 }
1994
1995 if (request_irq(sdev->irqs[0], snd_cs4231_sbus_interrupt,
1996 SA_SHIRQ, "cs4231", chip)) {
1997 snd_cs4231_sbus_free(chip);
1998 snd_printk("cs4231-%d: Unable to grab SBUS IRQ %s\n",
1999 dev,
2000 __irq_itoa(sdev->irqs[0]));
2001 return -EBUSY;
2002 }
2003 chip->irq[0] = sdev->irqs[0];
2004
2005 if (snd_cs4231_probe(chip) < 0) {
2006 snd_cs4231_sbus_free(chip);
2007 return -ENODEV;
2008 }
2009 snd_cs4231_init(chip);
2010
2011 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
2012 chip, &snd_cs4231_sbus_dev_ops)) < 0) {
2013 snd_cs4231_sbus_free(chip);
2014 return err;
2015 }
2016
2017 *rchip = chip;
2018 return 0;
2019 }
2020
2021 static int cs4231_sbus_attach(struct sbus_dev *sdev)
2022 {
2023 struct resource *rp = &sdev->resource[0];
2024 cs4231_t *cp;
2025 snd_card_t *card;
2026 int err;
2027
2028 err = cs4231_attach_begin(&card);
2029 if (err)
2030 return err;
2031
2032 sprintf(card->longname, "%s at 0x%02lx:0x%08lx, irq %s",
2033 card->shortname,
2034 rp->flags & 0xffL,
2035 rp->start,
2036 __irq_itoa(sdev->irqs[0]));
2037
2038 if ((err = snd_cs4231_sbus_create(card, sdev, dev, &cp)) < 0) {
2039 snd_card_free(card);
2040 return err;
2041 }
2042
2043 return cs4231_attach_finish(card, cp);
2044 }
2045 #endif
2046
2047 #ifdef EBUS_SUPPORT
2048 static int snd_cs4231_ebus_free(cs4231_t *chip)
2049 {
2050 if (chip->eb2c.regs) {
2051 ebus_dma_unregister(&chip->eb2c);
2052 iounmap(chip->eb2c.regs);
2053 }
2054 if (chip->eb2p.regs) {
2055 ebus_dma_unregister(&chip->eb2p);
2056 iounmap(chip->eb2p.regs);
2057 }
2058
2059 if (chip->port)
2060 iounmap(chip->port);
2061 if (chip->timer)
2062 snd_device_free(chip->card, chip->timer);
2063
2064 snd_magic_kfree(chip);
2065
2066 return 0;
2067 }
2068
2069 static int snd_cs4231_ebus_dev_free(snd_device_t *device)
2070 {
2071 cs4231_t *cp = snd_magic_cast(cs4231_t, device->device_data, return -ENXIO);
2072
2073 return snd_cs4231_ebus_free(cp);
2074 }
2075
2076 static snd_device_ops_t snd_cs4231_ebus_dev_ops = {
2077 .dev_free = snd_cs4231_ebus_dev_free,
2078 };
2079
2080 static int __init snd_cs4231_ebus_create(snd_card_t *card,
2081 struct linux_ebus_device *edev,
2082 int dev,
2083 cs4231_t **rchip)
2084 {
2085 cs4231_t *chip;
2086 int err;
2087
2088 *rchip = NULL;
2089 chip = snd_magic_kcalloc(cs4231_t, 0, GFP_KERNEL);
2090 if (chip == NULL)
2091 return -ENOMEM;
2092
2093 spin_lock_init(&chip->lock);
2094 spin_lock_init(&chip->eb2c.lock);
2095 spin_lock_init(&chip->eb2p.lock);
2096 init_MUTEX(&chip->mce_mutex);
2097 init_MUTEX(&chip->open_mutex);
2098 chip->flags |= CS4231_FLAG_EBUS;
2099 chip->card = card;
2100 chip->dev_u.pdev = edev->bus->self;
2101 memcpy(&chip->image, &snd_cs4231_original_image,
2102 sizeof(snd_cs4231_original_image));
2103 strcpy(chip->eb2c.name, "cs4231(capture)");
2104 chip->eb2c.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
2105 chip->eb2c.callback = snd_cs4231_ebus_capture_callback;
2106 chip->eb2c.client_cookie = chip;
2107 chip->eb2c.irq = edev->irqs[0];
2108 strcpy(chip->eb2p.name, "cs4231(play)");
2109 chip->eb2p.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
2110 chip->eb2p.callback = snd_cs4231_ebus_play_callback;
2111 chip->eb2p.client_cookie = chip;
2112 chip->eb2p.irq = edev->irqs[1];
2113
2114 chip->port = (unsigned long) ioremap(edev->resource[0].start, 0x10);
2115 chip->eb2p.regs = (unsigned long) ioremap(edev->resource[1].start, 0x10);
2116 chip->eb2c.regs = (unsigned long) ioremap(edev->resource[2].start, 0x10);
2117 if (!chip->port || !chip->eb2p.regs || !chip->eb2c.regs) {
2118 snd_cs4231_ebus_free(chip);
2119 snd_printk("cs4231-%d: Unable to map chip registers.\n", dev);
2120 return -EIO;
2121 }
2122
2123 if (ebus_dma_register(&chip->eb2c)) {
2124 snd_cs4231_ebus_free(chip);
2125 snd_printk("cs4231-%d: Unable to register EBUS capture DMA\n", dev);
2126 return -EBUSY;
2127 }
2128 if (ebus_dma_irq_enable(&chip->eb2c, 1)) {
2129 snd_cs4231_ebus_free(chip);
2130 snd_printk("cs4231-%d: Unable to enable EBUS capture IRQ\n", dev);
2131 return -EBUSY;
2132 }
2133
2134 if (ebus_dma_register(&chip->eb2p)) {
2135 snd_cs4231_ebus_free(chip);
2136 snd_printk("cs4231-%d: Unable to register EBUS play DMA\n", dev);
2137 return -EBUSY;
2138 }
2139 if (ebus_dma_irq_enable(&chip->eb2p, 1)) {
2140 snd_cs4231_ebus_free(chip);
2141 snd_printk("cs4231-%d: Unable to enable EBUS play IRQ\n", dev);
2142 return -EBUSY;
2143 }
2144
2145 if (snd_cs4231_probe(chip) < 0) {
2146 snd_cs4231_ebus_free(chip);
2147 return -ENODEV;
2148 }
2149 snd_cs4231_init(chip);
2150
2151 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
2152 chip, &snd_cs4231_ebus_dev_ops)) < 0) {
2153 snd_cs4231_ebus_free(chip);
2154 return err;
2155 }
2156
2157 *rchip = chip;
2158 return 0;
2159 }
2160
2161 static int cs4231_ebus_attach(struct linux_ebus_device *edev)
2162 {
2163 snd_card_t *card;
2164 cs4231_t *chip;
2165 int err;
2166
2167 err = cs4231_attach_begin(&card);
2168 if (err)
2169 return err;
2170
2171 sprintf(card->longname, "%s at 0x%lx, irq %s",
2172 card->shortname,
2173 edev->resource[0].start,
2174 __irq_itoa(edev->irqs[0]));
2175
2176 if ((err = snd_cs4231_ebus_create(card, edev, dev, &chip)) < 0) {
2177 snd_card_free(card);
2178 return err;
2179 }
2180
2181 return cs4231_attach_finish(card, chip);
2182 }
2183 #endif
2184
2185 static int __init cs4231_init(void)
2186 {
2187 #ifdef SBUS_SUPPORT
2188 struct sbus_bus *sbus;
2189 struct sbus_dev *sdev;
2190 #endif
2191 #ifdef EBUS_SUPPORT
2192 struct linux_ebus *ebus;
2193 struct linux_ebus_device *edev;
2194 #endif
2195 int found;
2196
2197 found = 0;
2198
2199 #ifdef SBUS_SUPPORT
2200 for_all_sbusdev(sdev, sbus) {
2201 if (!strcmp(sdev->prom_name, "SUNW,CS4231")) {
2202 if (cs4231_sbus_attach(sdev) == 0)
2203 found++;
2204 }
2205 }
2206 #endif
2207 #ifdef EBUS_SUPPORT
2208 for_each_ebus(ebus) {
2209 for_each_ebusdev(edev, ebus) {
2210 int match = 0;
2211
2212 if (!strcmp(edev->prom_name, "SUNW,CS4231")) {
2213 match = 1;
2214 } else if (!strcmp(edev->prom_name, "audio")) {
2215 char compat[16];
2216
2217 prom_getstring(edev->prom_node, "compatible",
2218 compat, sizeof(compat));
2219 compat[15] = '\0';
2220 if (!strcmp(compat, "SUNW,CS4231"))
2221 match = 1;
2222 }
2223
2224 if (match &&
2225 cs4231_ebus_attach(edev) == 0)
2226 found++;
2227 }
2228 }
2229 #endif
2230
2231
2232 return (found > 0) ? 0 : -EIO;
2233 }
2234
2235 static void __exit cs4231_exit(void)
2236 {
2237 cs4231_t *p = cs4231_list;
2238
2239 while (p != NULL) {
2240 cs4231_t *next = p->next;
2241
2242 snd_card_free(p->card);
2243
2244 p = next;
2245 }
2246
2247 cs4231_list = NULL;
2248 }
2249
2250 module_init(cs4231_init);
2251 module_exit(cs4231_exit);
2252
2253 #ifndef MODULE
2254
2255 /* format is: snd-sun-cs4231=index,id,enable */
2256
2257 static int __init alsa_card_sun_cs4231_setup(char *str)
2258 {
2259 static unsigned __initdata nr_dev = 0;
2260
2261 if (nr_dev >= SNDRV_CARDS)
2262 return 0;
2263 (void)(get_option(&str,&index[nr_dev]) == 2 &&
2264 get_option(&str,&id[nr_dev]) == 2 &&
2265 get_id(&str,&enable[nr_dev]) == 2);
2266 nr_dev++;
2267 return 1;
2268 }
2269
2270 __setup("snd-sun-cs4231=", alsa_card_sun_cs4231_setup);
2271
2272 #endif /* ifndef MODULE */
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