drivers/char/drm/i830_drm.h

   1 #ifndef _I830_DRM_H_
   2 #define _I830_DRM_H_
   3
   4 /* WARNING: These defines must be the same as what the Xserver uses.
   5  * if you change them, you must change the defines in the Xserver.
   6  */
   7
   8 #ifndef _I830_DEFINES_
   9 #define _I830_DEFINES_
  10
  11 #define I830_DMA_BUF_ORDER              12
  12 #define I830_DMA_BUF_SZ                 (1<<I830_DMA_BUF_ORDER)
  13 #define I830_DMA_BUF_NR                 256
  14 #define I830_NR_SAREA_CLIPRECTS         8
  15
  16 /* Each region is a minimum of 64k, and there are at most 64 of them.
  17  */
  18 #define I830_NR_TEX_REGIONS 64
  19 #define I830_LOG_MIN_TEX_REGION_SIZE 16
  20
  21 /* if defining I830_ENABLE_4_TEXTURES, do it in i830_3d_reg.h, too */
  22 #if !defined(I830_ENABLE_4_TEXTURES)
  23 #define I830_TEXTURE_COUNT      2
  24 #define I830_TEXBLEND_COUNT     2       /* always same as TEXTURE_COUNT? */
  25 #else /* defined(I830_ENABLE_4_TEXTURES) */
  26 #define I830_TEXTURE_COUNT      4
  27 #define I830_TEXBLEND_COUNT     4       /* always same as TEXTURE_COUNT? */
  28 #endif /* I830_ENABLE_4_TEXTURES */
  29
  30 #define I830_TEXBLEND_SIZE      12      /* (4 args + op) * 2 + COLOR_FACTOR */
  31
  32 #define I830_UPLOAD_CTX                 0x1
  33 #define I830_UPLOAD_BUFFERS             0x2
  34 #define I830_UPLOAD_CLIPRECTS           0x4
  35 #define I830_UPLOAD_TEX0_IMAGE          0x100 /* handled clientside */
  36 #define I830_UPLOAD_TEX0_CUBE           0x200 /* handled clientside */
  37 #define I830_UPLOAD_TEX1_IMAGE          0x400 /* handled clientside */
  38 #define I830_UPLOAD_TEX1_CUBE           0x800 /* handled clientside */
  39 #define I830_UPLOAD_TEX2_IMAGE          0x1000 /* handled clientside */
  40 #define I830_UPLOAD_TEX2_CUBE           0x2000 /* handled clientside */
  41 #define I830_UPLOAD_TEX3_IMAGE          0x4000 /* handled clientside */
  42 #define I830_UPLOAD_TEX3_CUBE           0x8000 /* handled clientside */
  43 #define I830_UPLOAD_TEX_N_IMAGE(n)      (0x100 << (n * 2))
  44 #define I830_UPLOAD_TEX_N_CUBE(n)       (0x200 << (n * 2))
  45 #define I830_UPLOAD_TEXIMAGE_MASK       0xff00
  46 #define I830_UPLOAD_TEX0                        0x10000
  47 #define I830_UPLOAD_TEX1                        0x20000
  48 #define I830_UPLOAD_TEX2                        0x40000
  49 #define I830_UPLOAD_TEX3                        0x80000
  50 #define I830_UPLOAD_TEX_N(n)            (0x10000 << (n))
  51 #define I830_UPLOAD_TEX_MASK            0xf0000
  52 #define I830_UPLOAD_TEXBLEND0           0x100000
  53 #define I830_UPLOAD_TEXBLEND1           0x200000
  54 #define I830_UPLOAD_TEXBLEND2           0x400000
  55 #define I830_UPLOAD_TEXBLEND3           0x800000
  56 #define I830_UPLOAD_TEXBLEND_N(n)       (0x100000 << (n))
  57 #define I830_UPLOAD_TEXBLEND_MASK       0xf00000
  58 #define I830_UPLOAD_TEX_PALETTE_N(n)    (0x1000000 << (n))
  59 #define I830_UPLOAD_TEX_PALETTE_SHARED  0x4000000
  60
  61 /* Indices into buf.Setup where various bits of state are mirrored per
  62  * context and per buffer.  These can be fired at the card as a unit,
  63  * or in a piecewise fashion as required.
  64  */
  65
  66 /* Destbuffer state
  67  *    - backbuffer linear offset and pitch -- invarient in the current dri
  68  *    - zbuffer linear offset and pitch -- also invarient
  69  *    - drawing origin in back and depth buffers.
  70  *
  71  * Keep the depth/back buffer state here to acommodate private buffers
  72  * in the future.
  73  */
  74
  75 #define I830_DESTREG_CBUFADDR 0
  76 /* Invarient */
  77 #define I830_DESTREG_DBUFADDR 1
  78 #define I830_DESTREG_DV0 2
  79 #define I830_DESTREG_DV1 3
  80 #define I830_DESTREG_SENABLE 4
  81 #define I830_DESTREG_SR0 5
  82 #define I830_DESTREG_SR1 6
  83 #define I830_DESTREG_SR2 7
  84 #define I830_DESTREG_DR0 8
  85 #define I830_DESTREG_DR1 9
  86 #define I830_DESTREG_DR2 10
  87 #define I830_DESTREG_DR3 11
  88 #define I830_DESTREG_DR4 12
  89 #define I830_DEST_SETUP_SIZE 13
  90
  91 /* Context state
  92  */
  93 #define I830_CTXREG_STATE1              0
  94 #define I830_CTXREG_STATE2              1
  95 #define I830_CTXREG_STATE3              2
  96 #define I830_CTXREG_STATE4              3
  97 #define I830_CTXREG_STATE5              4
  98 #define I830_CTXREG_IALPHAB             5
  99 #define I830_CTXREG_STENCILTST          6
 100 #define I830_CTXREG_ENABLES_1           7
 101 #define I830_CTXREG_ENABLES_2           8
 102 #define I830_CTXREG_AA                  9
 103 #define I830_CTXREG_FOGCOLOR            10
 104 #define I830_CTXREG_BLENDCOLR0          11
 105 #define I830_CTXREG_BLENDCOLR           12 /* Dword 1 of 2 dword command */
 106 #define I830_CTXREG_VF                  13
 107 #define I830_CTXREG_VF2                 14
 108 #define I830_CTXREG_MCSB0               15
 109 #define I830_CTXREG_MCSB1               16
 110 #define I830_CTX_SETUP_SIZE             17
 111
 112 /* Texture state (per tex unit)
 113  */
 114
 115 #define I830_TEXREG_MI0 0       /* GFX_OP_MAP_INFO (6 dwords) */
 116 #define I830_TEXREG_MI1 1
 117 #define I830_TEXREG_MI2 2
 118 #define I830_TEXREG_MI3 3
 119 #define I830_TEXREG_MI4 4
 120 #define I830_TEXREG_MI5 5
 121 #define I830_TEXREG_MF  6       /* GFX_OP_MAP_FILTER */
 122 #define I830_TEXREG_MLC 7       /* GFX_OP_MAP_LOD_CTL */
 123 #define I830_TEXREG_MLL 8       /* GFX_OP_MAP_LOD_LIMITS */
 124 #define I830_TEXREG_MCS 9       /* GFX_OP_MAP_COORD_SETS */
 125 #define I830_TEX_SETUP_SIZE 10
 126
 127 #define I830_FRONT   0x1
 128 #define I830_BACK    0x2
 129 #define I830_DEPTH   0x4
 130
 131 #endif /* _I830_DEFINES_ */
 132
 133 typedef struct _drm_i830_init {
 134         enum {
 135                 I830_INIT_DMA = 0x01,
 136                 I830_CLEANUP_DMA = 0x02
 137         } func;
 138         unsigned int mmio_offset;
 139         unsigned int buffers_offset;
 140         int sarea_priv_offset;
 141         unsigned int ring_start;
 142         unsigned int ring_end;
 143         unsigned int ring_size;
 144         unsigned int front_offset;
 145         unsigned int back_offset;
 146         unsigned int depth_offset;
 147         unsigned int w;
 148         unsigned int h;
 149         unsigned int pitch;
 150         unsigned int pitch_bits;
 151         unsigned int back_pitch;
 152         unsigned int depth_pitch;
 153         unsigned int cpp;
 154 } drm_i830_init_t;
 155
 156 /* Warning: If you change the SAREA structure you must change the Xserver
 157  * structure as well */
 158
 159 typedef struct _drm_i830_tex_region {
 160         unsigned char next, prev; /* indices to form a circular LRU  */
 161         unsigned char in_use;   /* owned by a client, or free? */
 162         int age;                /* tracked by clients to update local LRU's */
 163 } drm_i830_tex_region_t;
 164
 165 typedef struct _drm_i830_sarea {
 166         unsigned int ContextState[I830_CTX_SETUP_SIZE];
 167         unsigned int BufferState[I830_DEST_SETUP_SIZE];
 168         unsigned int TexState[I830_TEXTURE_COUNT][I830_TEX_SETUP_SIZE];
 169         unsigned int TexBlendState[I830_TEXBLEND_COUNT][I830_TEXBLEND_SIZE];
 170         unsigned int TexBlendStateWordsUsed[I830_TEXBLEND_COUNT];
 171         unsigned int Palette[2][256];
 172         unsigned int dirty;
 173
 174         unsigned int nbox;
 175         drm_clip_rect_t boxes[I830_NR_SAREA_CLIPRECTS];
 176
 177         /* Maintain an LRU of contiguous regions of texture space.  If
 178          * you think you own a region of texture memory, and it has an
 179          * age different to the one you set, then you are mistaken and
 180          * it has been stolen by another client.  If global texAge
 181          * hasn't changed, there is no need to walk the list.
 182          *
 183          * These regions can be used as a proxy for the fine-grained
 184          * texture information of other clients - by maintaining them
 185          * in the same lru which is used to age their own textures,
 186          * clients have an approximate lru for the whole of global
 187          * texture space, and can make informed decisions as to which
 188          * areas to kick out.  There is no need to choose whether to
 189          * kick out your own texture or someone else's - simply eject
 190          * them all in LRU order.
 191          */
 192
 193         drm_i830_tex_region_t texList[I830_NR_TEX_REGIONS+1];
 194                                 /* Last elt is sentinal */
 195         int texAge;             /* last time texture was uploaded */
 196         int last_enqueue;       /* last time a buffer was enqueued */
 197         int last_dispatch;      /* age of the most recently dispatched buffer */
 198         int last_quiescent;     /*  */
 199         int ctxOwner;           /* last context to upload state */
 200
 201         int vertex_prim;
 202 } drm_i830_sarea_t;
 203
 204 /* I830 specific ioctls
 205  * The device specific ioctl range is 0x40 to 0x79.
 206  */
 207 #define DRM_IOCTL_I830_INIT             DRM_IOW( 0x40, drm_i830_init_t)
 208 #define DRM_IOCTL_I830_VERTEX           DRM_IOW( 0x41, drm_i830_vertex_t)
 209 #define DRM_IOCTL_I830_CLEAR            DRM_IOW( 0x42, drm_i830_clear_t)
 210 #define DRM_IOCTL_I830_FLUSH            DRM_IO ( 0x43)
 211 #define DRM_IOCTL_I830_GETAGE           DRM_IO ( 0x44)
 212 #define DRM_IOCTL_I830_GETBUF           DRM_IOWR(0x45, drm_i830_dma_t)
 213 #define DRM_IOCTL_I830_SWAP             DRM_IO ( 0x46)
 214 #define DRM_IOCTL_I830_COPY             DRM_IOW( 0x47, drm_i830_copy_t)
 215 #define DRM_IOCTL_I830_DOCOPY           DRM_IO ( 0x48)
 216
 217 typedef struct _drm_i830_clear {
 218         int clear_color;
 219         int clear_depth;
 220         int flags;
 221         unsigned int clear_colormask;
 222         unsigned int clear_depthmask;
 223 } drm_i830_clear_t;
 224
 225
 226
 227 /* These may be placeholders if we have more cliprects than
 228  * I830_NR_SAREA_CLIPRECTS.  In that case, the client sets discard to
 229  * false, indicating that the buffer will be dispatched again with a
 230  * new set of cliprects.
 231  */
 232 typedef struct _drm_i830_vertex {
 233         int idx;                /* buffer index */
 234         int used;               /* nr bytes in use */
 235         int discard;            /* client is finished with the buffer? */
 236 } drm_i830_vertex_t;
 237
 238 typedef struct _drm_i830_copy_t {
 239         int idx;                /* buffer index */
 240         int used;               /* nr bytes in use */
 241         void *address;          /* Address to copy from */
 242 } drm_i830_copy_t;
 243
 244 typedef struct drm_i830_dma {
 245         void *virtual;
 246         int request_idx;
 247         int request_size;
 248         int granted;
 249 } drm_i830_dma_t;
 250
 251 #endif /* _I830_DRM_H_ */