?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge with Linux 2.5.48.
[linux-2.6/linux-mips.git] / drivers / atm / idt77252.c
blobe337c9e68ed4b974878a00dd0edf7965941ae6c7
1 /*******************************************************************
2 * ident "$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $"
3 *
4 * $Author: ecd $
5 * $Date: 2001/11/11 08:13:54 $
6 *
7 * Copyright (c) 2000 ATecoM GmbH
8 *
9 * The author may be reached at ecd@atecom.com.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 *******************************************************************/
32 static char const rcsid[] =
33 "$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $";
34
35
36 #include <linux/module.h>
37 #include <linux/config.h>
38 #include <linux/pci.h>
39 #include <linux/skbuff.h>
40 #include <linux/kernel.h>
41 #include <linux/vmalloc.h>
42 #include <linux/netdevice.h>
43 #include <linux/atmdev.h>
44 #include <linux/atm.h>
45 #include <linux/delay.h>
46 #include <linux/init.h>
47 #include <linux/bitops.h>
48 #include <linux/wait.h>
49 #include <asm/semaphore.h>
50 #include <asm/io.h>
51 #include <asm/uaccess.h>
52 #include <asm/atomic.h>
53 #include <asm/byteorder.h>
54
55 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
56 #include "suni.h"
57 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
58
59
60 #include "idt77252.h"
61 #include "idt77252_tables.h"
62
63 static unsigned int vpibits = 1;
64
65
66 #define CONFIG_ATM_IDT77252_SEND_IDLE 1
67
68
69 /*
70 * Debug HACKs.
71 */
72 #define DEBUG_MODULE 1
73 #undef HAVE_EEPROM /* does not work, yet. */
74
75 #ifdef CONFIG_ATM_IDT77252_DEBUG
76 static unsigned long debug = DBG_GENERAL;
77 #endif
78
79
80 #define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY)
81
82
83 /*
84 * SCQ Handling.
85 */
86 static struct scq_info *alloc_scq(struct idt77252_dev *, int);
87 static void free_scq(struct idt77252_dev *, struct scq_info *);
88 static int queue_skb(struct idt77252_dev *, struct vc_map *,
89 struct sk_buff *, int oam);
90 static void drain_scq(struct idt77252_dev *, struct vc_map *);
91 static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *);
92 static void fill_scd(struct idt77252_dev *, struct scq_info *, int);
93
94 /*
95 * FBQ Handling.
96 */
97 static int push_rx_skb(struct idt77252_dev *,
98 struct sk_buff *, int queue);
99 static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *);
100 static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *);
101 static void recycle_rx_pool_skb(struct idt77252_dev *,
102 struct rx_pool *);
103 static void add_rx_skb(struct idt77252_dev *, int queue,
104 unsigned int size, unsigned int count);
105
106 /*
107 * RSQ Handling.
108 */
109 static int init_rsq(struct idt77252_dev *);
110 static void deinit_rsq(struct idt77252_dev *);
111 static void idt77252_rx(struct idt77252_dev *);
112
113 /*
114 * TSQ handling.
115 */
116 static int init_tsq(struct idt77252_dev *);
117 static void deinit_tsq(struct idt77252_dev *);
118 static void idt77252_tx(struct idt77252_dev *);
119
120
121 /*
122 * ATM Interface.
123 */
124 static void idt77252_dev_close(struct atm_dev *dev);
125 static int idt77252_open(struct atm_vcc *vcc, short vpi, int vci);
126 static void idt77252_close(struct atm_vcc *vcc);
127 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb);
128 static int idt77252_send_oam(struct atm_vcc *vcc, void *cell,
129 int flags);
130 static void idt77252_phy_put(struct atm_dev *dev, unsigned char value,
131 unsigned long addr);
132 static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr);
133 static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos,
134 int flags);
135 static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos,
136 char *page);
137 static void idt77252_interrupt(int irq, void *dev_id,
138 struct pt_regs *regs);
139 static void idt77252_softint(void *dev_id);
140
141
142 static struct atmdev_ops idt77252_ops =
143 {
144 .dev_close = idt77252_dev_close,
145 .open = idt77252_open,
146 .close = idt77252_close,
147 .send = idt77252_send,
148 .send_oam = idt77252_send_oam,
149 .phy_put = idt77252_phy_put,
150 .phy_get = idt77252_phy_get,
151 .change_qos = idt77252_change_qos,
152 .proc_read = idt77252_proc_read
153 };
154
155 static struct idt77252_dev *idt77252_chain = NULL;
156 static unsigned int idt77252_sram_write_errors = 0;
157
158 /*****************************************************************************/
159 /* */
160 /* I/O and Utility Bus */
161 /* */
162 /*****************************************************************************/
163
164 static void
165 waitfor_idle(struct idt77252_dev *card)
166 {
167 u32 stat;
168
169 stat = readl(SAR_REG_STAT);
170 while (stat & SAR_STAT_CMDBZ)
171 stat = readl(SAR_REG_STAT);
172 }
173
174 static u32
175 read_sram(struct idt77252_dev *card, unsigned long addr)
176 {
177 unsigned long flags;
178 u32 value;
179
180 spin_lock_irqsave(&card->cmd_lock, flags);
181 writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD);
182 waitfor_idle(card);
183 value = readl(SAR_REG_DR0);
184 spin_unlock_irqrestore(&card->cmd_lock, flags);
185 return value;
186 }
187
188 static void
189 write_sram(struct idt77252_dev *card, unsigned long addr, u32 value)
190 {
191 unsigned long flags;
192
193 if ((idt77252_sram_write_errors == 0) &&
194 (((addr > card->tst[0] + card->tst_size - 2) &&
195 (addr < card->tst[0] + card->tst_size)) ||
196 ((addr > card->tst[1] + card->tst_size - 2) &&
197 (addr < card->tst[1] + card->tst_size)))) {
198 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n",
199 card->name, addr, value);
200 }
201
202 spin_lock_irqsave(&card->cmd_lock, flags);
203 writel(value, SAR_REG_DR0);
204 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
205 waitfor_idle(card);
206 spin_unlock_irqrestore(&card->cmd_lock, flags);
207 }
208
209 static u8
210 read_utility(void *dev, unsigned long ubus_addr)
211 {
212 struct idt77252_dev *card = dev;
213 unsigned long flags;
214 u8 value;
215
216 if (!card) {
217 printk("Error: No such device.\n");
218 return -1;
219 }
220
221 spin_lock_irqsave(&card->cmd_lock, flags);
222 writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD);
223 waitfor_idle(card);
224 value = readl(SAR_REG_DR0);
225 spin_unlock_irqrestore(&card->cmd_lock, flags);
226 return value;
227 }
228
229 static void
230 write_utility(void *dev, unsigned long ubus_addr, u8 value)
231 {
232 struct idt77252_dev *card = dev;
233 unsigned long flags;
234
235 if (!card) {
236 printk("Error: No such device.\n");
237 return;
238 }
239
240 spin_lock_irqsave(&card->cmd_lock, flags);
241 writel((u32) value, SAR_REG_DR0);
242 writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD);
243 waitfor_idle(card);
244 spin_unlock_irqrestore(&card->cmd_lock, flags);
245 }
246
247 #ifdef HAVE_EEPROM
248 static u32 rdsrtab[] =
249 {
250 SAR_GP_EECS | SAR_GP_EESCLK,
251 0,
252 SAR_GP_EESCLK, /* 0 */
253 0,
254 SAR_GP_EESCLK, /* 0 */
255 0,
256 SAR_GP_EESCLK, /* 0 */
257 0,
258 SAR_GP_EESCLK, /* 0 */
259 0,
260 SAR_GP_EESCLK, /* 0 */
261 SAR_GP_EEDO,
262 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
263 0,
264 SAR_GP_EESCLK, /* 0 */
265 SAR_GP_EEDO,
266 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
267 };
268
269 static u32 wrentab[] =
270 {
271 SAR_GP_EECS | SAR_GP_EESCLK,
272 0,
273 SAR_GP_EESCLK, /* 0 */
274 0,
275 SAR_GP_EESCLK, /* 0 */
276 0,
277 SAR_GP_EESCLK, /* 0 */
278 0,
279 SAR_GP_EESCLK, /* 0 */
280 SAR_GP_EEDO,
281 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
282 SAR_GP_EEDO,
283 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
284 0,
285 SAR_GP_EESCLK, /* 0 */
286 0,
287 SAR_GP_EESCLK /* 0 */
288 };
289
290 static u32 rdtab[] =
291 {
292 SAR_GP_EECS | SAR_GP_EESCLK,
293 0,
294 SAR_GP_EESCLK, /* 0 */
295 0,
296 SAR_GP_EESCLK, /* 0 */
297 0,
298 SAR_GP_EESCLK, /* 0 */
299 0,
300 SAR_GP_EESCLK, /* 0 */
301 0,
302 SAR_GP_EESCLK, /* 0 */
303 0,
304 SAR_GP_EESCLK, /* 0 */
305 SAR_GP_EEDO,
306 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
307 SAR_GP_EEDO,
308 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
309 };
310
311 static u32 wrtab[] =
312 {
313 SAR_GP_EECS | SAR_GP_EESCLK,
314 0,
315 SAR_GP_EESCLK, /* 0 */
316 0,
317 SAR_GP_EESCLK, /* 0 */
318 0,
319 SAR_GP_EESCLK, /* 0 */
320 0,
321 SAR_GP_EESCLK, /* 0 */
322 0,
323 SAR_GP_EESCLK, /* 0 */
324 0,
325 SAR_GP_EESCLK, /* 0 */
326 SAR_GP_EEDO,
327 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
328 0,
329 SAR_GP_EESCLK /* 0 */
330 };
331
332 static u32 clktab[] =
333 {
334 0,
335 SAR_GP_EESCLK,
336 0,
337 SAR_GP_EESCLK,
338 0,
339 SAR_GP_EESCLK,
340 0,
341 SAR_GP_EESCLK,
342 0,
343 SAR_GP_EESCLK,
344 0,
345 SAR_GP_EESCLK,
346 0,
347 SAR_GP_EESCLK,
348 0,
349 SAR_GP_EESCLK,
350 0
351 };
352
353 static u32
354 idt77252_read_gp(struct idt77252_dev *card)
355 {
356 u32 gp;
357
358 gp = readl(SAR_REG_GP);
359 #if 0
360 printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0");
361 #endif
362 return gp;
363 }
364
365 static void
366 idt77252_write_gp(struct idt77252_dev *card, u32 value)
367 {
368 unsigned long flags;
369
370 #if 0
371 printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS",
372 value & SAR_GP_EESCLK ? "HIGH" : "LOW ",
373 value & SAR_GP_EEDO ? "1" : "0");
374 #endif
375
376 spin_lock_irqsave(&card->cmd_lock, flags);
377 waitfor_idle(card);
378 writel(value, SAR_REG_GP);
379 spin_unlock_irqrestore(&card->cmd_lock, flags);
380 }
381
382 static u8
383 idt77252_eeprom_read_status(struct idt77252_dev *card)
384 {
385 u8 byte;
386 u32 gp;
387 int i, j;
388
389 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
390
391 for (i = 0; i < sizeof(rdsrtab)/sizeof(rdsrtab[0]); i++) {
392 idt77252_write_gp(card, gp | rdsrtab[i]);
393 udelay(5);
394 }
395 idt77252_write_gp(card, gp | SAR_GP_EECS);
396 udelay(5);
397
398 byte = 0;
399 for (i = 0, j = 0; i < 8; i++) {
400 byte <<= 1;
401
402 idt77252_write_gp(card, gp | clktab[j++]);
403 udelay(5);
404
405 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
406
407 idt77252_write_gp(card, gp | clktab[j++]);
408 udelay(5);
409 }
410 idt77252_write_gp(card, gp | SAR_GP_EECS);
411 udelay(5);
412
413 return byte;
414 }
415
416 static u8
417 idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset)
418 {
419 u8 byte;
420 u32 gp;
421 int i, j;
422
423 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
424
425 for (i = 0; i < sizeof(rdtab)/sizeof(rdtab[0]); i++) {
426 idt77252_write_gp(card, gp | rdtab[i]);
427 udelay(5);
428 }
429 idt77252_write_gp(card, gp | SAR_GP_EECS);
430 udelay(5);
431
432 for (i = 0, j = 0; i < 8; i++) {
433 idt77252_write_gp(card, gp | clktab[j++] |
434 (offset & 1 ? SAR_GP_EEDO : 0));
435 udelay(5);
436
437 idt77252_write_gp(card, gp | clktab[j++] |
438 (offset & 1 ? SAR_GP_EEDO : 0));
439 udelay(5);
440
441 offset >>= 1;
442 }
443 idt77252_write_gp(card, gp | SAR_GP_EECS);
444 udelay(5);
445
446 byte = 0;
447 for (i = 0, j = 0; i < 8; i++) {
448 byte <<= 1;
449
450 idt77252_write_gp(card, gp | clktab[j++]);
451 udelay(5);
452
453 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
454
455 idt77252_write_gp(card, gp | clktab[j++]);
456 udelay(5);
457 }
458 idt77252_write_gp(card, gp | SAR_GP_EECS);
459 udelay(5);
460
461 return byte;
462 }
463
464 static void
465 idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data)
466 {
467 u32 gp;
468 int i, j;
469
470 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
471
472 for (i = 0; i < sizeof(wrentab)/sizeof(wrentab[0]); i++) {
473 idt77252_write_gp(card, gp | wrentab[i]);
474 udelay(5);
475 }
476 idt77252_write_gp(card, gp | SAR_GP_EECS);
477 udelay(5);
478
479 for (i = 0; i < sizeof(wrtab)/sizeof(wrtab[0]); i++) {
480 idt77252_write_gp(card, gp | wrtab[i]);
481 udelay(5);
482 }
483 idt77252_write_gp(card, gp | SAR_GP_EECS);
484 udelay(5);
485
486 for (i = 0, j = 0; i < 8; i++) {
487 idt77252_write_gp(card, gp | clktab[j++] |
488 (offset & 1 ? SAR_GP_EEDO : 0));
489 udelay(5);
490
491 idt77252_write_gp(card, gp | clktab[j++] |
492 (offset & 1 ? SAR_GP_EEDO : 0));
493 udelay(5);
494
495 offset >>= 1;
496 }
497 idt77252_write_gp(card, gp | SAR_GP_EECS);
498 udelay(5);
499
500 for (i = 0, j = 0; i < 8; i++) {
501 idt77252_write_gp(card, gp | clktab[j++] |
502 (data & 1 ? SAR_GP_EEDO : 0));
503 udelay(5);
504
505 idt77252_write_gp(card, gp | clktab[j++] |
506 (data & 1 ? SAR_GP_EEDO : 0));
507 udelay(5);
508
509 data >>= 1;
510 }
511 idt77252_write_gp(card, gp | SAR_GP_EECS);
512 udelay(5);
513 }
514
515 static void
516 idt77252_eeprom_init(struct idt77252_dev *card)
517 {
518 u32 gp;
519
520 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
521
522 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
523 udelay(5);
524 idt77252_write_gp(card, gp | SAR_GP_EECS);
525 udelay(5);
526 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
527 udelay(5);
528 idt77252_write_gp(card, gp | SAR_GP_EECS);
529 udelay(5);
530 }
531 #endif /* HAVE_EEPROM */
532
533
534 #ifdef CONFIG_ATM_IDT77252_DEBUG
535 static void
536 dump_tct(struct idt77252_dev *card, int index)
537 {
538 unsigned long tct;
539 int i;
540
541 tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE);
542
543 printk("%s: TCT %x:", card->name, index);
544 for (i = 0; i < 8; i++) {
545 printk(" %08x", read_sram(card, tct + i));
546 }
547 printk("\n");
548 }
549
550 static void
551 idt77252_tx_dump(struct idt77252_dev *card)
552 {
553 struct atm_vcc *vcc;
554 struct vc_map *vc;
555 int i;
556
557 printk("%s\n", __FUNCTION__);
558 for (i = 0; i < card->tct_size; i++) {
559 vc = card->vcs[i];
560 if (!vc)
561 continue;
562
563 vcc = NULL;
564 if (vc->rx_vcc)
565 vcc = vc->rx_vcc;
566 else if (vc->tx_vcc)
567 vcc = vc->tx_vcc;
568
569 if (!vcc)
570 continue;
571
572 printk("%s: Connection %d:\n", card->name, vc->index);
573 dump_tct(card, vc->index);
574 }
575 }
576 #endif
577
578
579 /*****************************************************************************/
580 /* */
581 /* SCQ Handling */
582 /* */
583 /*****************************************************************************/
584
585 static int
586 sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue)
587 {
588 struct sb_pool *pool = &card->sbpool[queue];
589 int index;
590
591 index = pool->index;
592 while (pool->skb[index]) {
593 index = (index + 1) & FBQ_MASK;
594 if (index == pool->index)
595 return -ENOBUFS;
596 }
597
598 pool->skb[index] = skb;
599 IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index);
600
601 pool->index = (index + 1) & FBQ_MASK;
602 return 0;
603 }
604
605 static void
606 sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb)
607 {
608 unsigned int queue, index;
609 u32 handle;
610
611 handle = IDT77252_PRV_POOL(skb);
612
613 queue = POOL_QUEUE(handle);
614 if (queue > 3)
615 return;
616
617 index = POOL_INDEX(handle);
618 if (index > FBQ_SIZE - 1)
619 return;
620
621 card->sbpool[queue].skb[index] = NULL;
622 }
623
624 static struct sk_buff *
625 sb_pool_skb(struct idt77252_dev *card, u32 handle)
626 {
627 unsigned int queue, index;
628
629 queue = POOL_QUEUE(handle);
630 if (queue > 3)
631 return NULL;
632
633 index = POOL_INDEX(handle);
634 if (index > FBQ_SIZE - 1)
635 return NULL;
636
637 return card->sbpool[queue].skb[index];
638 }
639
640 static struct scq_info *
641 alloc_scq(struct idt77252_dev *card, int class)
642 {
643 struct scq_info *scq;
644
645 scq = (struct scq_info *) kmalloc(sizeof(struct scq_info), GFP_KERNEL);
646 if (!scq)
647 return NULL;
648 memset(scq, 0, sizeof(struct scq_info));
649
650 scq->base = pci_alloc_consistent(card->pcidev, SCQ_SIZE,
651 &scq->paddr);
652 if (scq->base == NULL) {
653 kfree(scq);
654 return NULL;
655 }
656 memset(scq->base, 0, SCQ_SIZE);
657
658 scq->next = scq->base;
659 scq->last = scq->base + (SCQ_ENTRIES - 1);
660 atomic_set(&scq->used, 0);
661
662 spin_lock_init(&scq->lock);
663 spin_lock_init(&scq->skblock);
664
665 skb_queue_head_init(&scq->transmit);
666 skb_queue_head_init(&scq->pending);
667
668 TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08x\n",
669 scq->base, scq->next, scq->last, scq->paddr);
670
671 return scq;
672 }
673
674 static void
675 free_scq(struct idt77252_dev *card, struct scq_info *scq)
676 {
677 struct sk_buff *skb;
678 struct atm_vcc *vcc;
679
680 pci_free_consistent(card->pcidev, SCQ_SIZE,
681 scq->base, scq->paddr);
682
683 while ((skb = skb_dequeue(&scq->transmit))) {
684 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
685 skb->len, PCI_DMA_TODEVICE);
686
687 vcc = ATM_SKB(skb)->vcc;
688 if (vcc->pop)
689 vcc->pop(vcc, skb);
690 else
691 dev_kfree_skb(skb);
692 }
693
694 while ((skb = skb_dequeue(&scq->pending))) {
695 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
696 skb->len, PCI_DMA_TODEVICE);
697
698 vcc = ATM_SKB(skb)->vcc;
699 if (vcc->pop)
700 vcc->pop(vcc, skb);
701 else
702 dev_kfree_skb(skb);
703 }
704
705 kfree(scq);
706 }
707
708
709 static int
710 push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb)
711 {
712 struct scq_info *scq = vc->scq;
713 unsigned long flags;
714 struct scqe *tbd;
715 int entries;
716
717 TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next);
718
719 atomic_inc(&scq->used);
720 entries = atomic_read(&scq->used);
721 if (entries > (SCQ_ENTRIES - 1)) {
722 atomic_dec(&scq->used);
723 goto out;
724 }
725
726 skb_queue_tail(&scq->transmit, skb);
727
728 spin_lock_irqsave(&vc->lock, flags);
729 if (vc->estimator) {
730 struct atm_vcc *vcc = vc->tx_vcc;
731
732 vc->estimator->cells += (skb->len + 47) / 48;
733 if (atomic_read(&vcc->tx_inuse) > (vcc->sk->sndbuf >> 1)) {
734 u32 cps = vc->estimator->maxcps;
735
736 vc->estimator->cps = cps;
737 vc->estimator->avcps = cps << 5;
738 if (vc->lacr < vc->init_er) {
739 vc->lacr = vc->init_er;
740 writel(TCMDQ_LACR | (vc->lacr << 16) |
741 vc->index, SAR_REG_TCMDQ);
742 }
743 }
744 }
745 spin_unlock_irqrestore(&vc->lock, flags);
746
747 tbd = &IDT77252_PRV_TBD(skb);
748
749 spin_lock_irqsave(&scq->lock, flags);
750 scq->next->word_1 = cpu_to_le32(tbd->word_1 |
751 SAR_TBD_TSIF | SAR_TBD_GTSI);
752 scq->next->word_2 = cpu_to_le32(tbd->word_2);
753 scq->next->word_3 = cpu_to_le32(tbd->word_3);
754 scq->next->word_4 = cpu_to_le32(tbd->word_4);
755
756 if (scq->next == scq->last)
757 scq->next = scq->base;
758 else
759 scq->next++;
760
761 write_sram(card, scq->scd,
762 scq->paddr +
763 (u32)((unsigned long)scq->next - (unsigned long)scq->base));
764 spin_unlock_irqrestore(&scq->lock, flags);
765
766 scq->trans_start = jiffies;
767
768 if (test_and_clear_bit(VCF_IDLE, &vc->flags)) {
769 writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index,
770 SAR_REG_TCMDQ);
771 }
772
773 TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used));
774
775 XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n",
776 card->name, atomic_read(&scq->used),
777 read_sram(card, scq->scd + 1), scq->next);
778
779 return 0;
780
781 out:
782 if (jiffies - scq->trans_start > HZ) {
783 printk("%s: Error pushing TBD for %d.%d\n",
784 card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci);
785 #ifdef CONFIG_ATM_IDT77252_DEBUG
786 idt77252_tx_dump(card);
787 #endif
788 scq->trans_start = jiffies;
789 }
790
791 return -ENOBUFS;
792 }
793
794
795 static void
796 drain_scq(struct idt77252_dev *card, struct vc_map *vc)
797 {
798 struct scq_info *scq = vc->scq;
799 struct sk_buff *skb;
800 struct atm_vcc *vcc;
801
802 TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n",
803 card->name, atomic_read(&scq->used), scq->next);
804
805 skb = skb_dequeue(&scq->transmit);
806 if (skb) {
807 TXPRINTK("%s: freeing skb at %p.\n", card->name, skb);
808
809 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
810 skb->len, PCI_DMA_TODEVICE);
811
812 vcc = ATM_SKB(skb)->vcc;
813
814 if (vcc->pop)
815 vcc->pop(vcc, skb);
816 else
817 dev_kfree_skb(skb);
818
819 atomic_inc(&vcc->stats->tx);
820 }
821
822 atomic_dec(&scq->used);
823
824 spin_lock(&scq->skblock);
825 while ((skb = skb_dequeue(&scq->pending))) {
826 if (push_on_scq(card, vc, skb)) {
827 skb_queue_head(&vc->scq->pending, skb);
828 break;
829 }
830 }
831 spin_unlock(&scq->skblock);
832 }
833
834 static int
835 queue_skb(struct idt77252_dev *card, struct vc_map *vc,
836 struct sk_buff *skb, int oam)
837 {
838 struct atm_vcc *vcc;
839 struct scqe *tbd;
840 unsigned long flags;
841 int error;
842 int aal;
843
844 if (skb->len == 0) {
845 printk("%s: invalid skb->len (%d)\n", card->name, skb->len);
846 return -EINVAL;
847 }
848
849 TXPRINTK("%s: Sending %d bytes of data.\n",
850 card->name, skb->len);
851
852 tbd = &IDT77252_PRV_TBD(skb);
853 vcc = ATM_SKB(skb)->vcc;
854
855 IDT77252_PRV_PADDR(skb) = pci_map_single(card->pcidev, skb->data,
856 skb->len, PCI_DMA_TODEVICE);
857
858 error = -EINVAL;
859
860 if (oam) {
861 if (skb->len != 52)
862 goto errout;
863
864 tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU;
865 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
866 tbd->word_3 = 0x00000000;
867 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
868 (skb->data[2] << 8) | (skb->data[3] << 0);
869
870 if (test_bit(VCF_RSV, &vc->flags))
871 vc = card->vcs[0];
872
873 goto done;
874 }
875
876 if (test_bit(VCF_RSV, &vc->flags)) {
877 printk("%s: Trying to transmit on reserved VC\n", card->name);
878 goto errout;
879 }
880
881 aal = vcc->qos.aal;
882
883 switch (aal) {
884 case ATM_AAL0:
885 case ATM_AAL34:
886 if (skb->len > 52)
887 goto errout;
888
889 if (aal == ATM_AAL0)
890 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 |
891 ATM_CELL_PAYLOAD;
892 else
893 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 |
894 ATM_CELL_PAYLOAD;
895
896 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
897 tbd->word_3 = 0x00000000;
898 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
899 (skb->data[2] << 8) | (skb->data[3] << 0);
900 break;
901
902 case ATM_AAL5:
903 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len;
904 tbd->word_2 = IDT77252_PRV_PADDR(skb);
905 tbd->word_3 = skb->len;
906 tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) |
907 (vcc->vci << SAR_TBD_VCI_SHIFT);
908 break;
909
910 case ATM_AAL1:
911 case ATM_AAL2:
912 default:
913 printk("%s: Traffic type not supported.\n", card->name);
914 error = -EPROTONOSUPPORT;
915 goto errout;
916 }
917
918 done:
919 spin_lock_irqsave(&vc->scq->skblock, flags);
920 skb_queue_tail(&vc->scq->pending, skb);
921
922 while ((skb = skb_dequeue(&vc->scq->pending))) {
923 if (push_on_scq(card, vc, skb)) {
924 skb_queue_head(&vc->scq->pending, skb);
925 break;
926 }
927 }
928 spin_unlock_irqrestore(&vc->scq->skblock, flags);
929
930 return 0;
931
932 errout:
933 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
934 skb->len, PCI_DMA_TODEVICE);
935 return error;
936 }
937
938 static unsigned long
939 get_free_scd(struct idt77252_dev *card, struct vc_map *vc)
940 {
941 int i;
942
943 for (i = 0; i < card->scd_size; i++) {
944 if (!card->scd2vc[i]) {
945 card->scd2vc[i] = vc;
946 vc->scd_index = i;
947 return card->scd_base + i * SAR_SRAM_SCD_SIZE;
948 }
949 }
950 return 0;
951 }
952
953 static void
954 fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
955 {
956 write_sram(card, scq->scd, scq->paddr);
957 write_sram(card, scq->scd + 1, 0x00000000);
958 write_sram(card, scq->scd + 2, 0xffffffff);
959 write_sram(card, scq->scd + 3, 0x00000000);
960 }
961
962 static void
963 clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
964 {
965 return;
966 }
967
968 /*****************************************************************************/
969 /* */
970 /* RSQ Handling */
971 /* */
972 /*****************************************************************************/
973
974 static int
975 init_rsq(struct idt77252_dev *card)
976 {
977 struct rsq_entry *rsqe;
978
979 card->rsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
980 &card->rsq.paddr);
981 if (card->rsq.base == NULL) {
982 printk("%s: can't allocate RSQ.\n", card->name);
983 return -1;
984 }
985 memset(card->rsq.base, 0, RSQSIZE);
986
987 card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1;
988 card->rsq.next = card->rsq.last;
989 for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++)
990 rsqe->word_4 = 0;
991
992 writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base,
993 SAR_REG_RSQH);
994 writel(card->rsq.paddr, SAR_REG_RSQB);
995
996 IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name,
997 (unsigned long) card->rsq.base,
998 readl(SAR_REG_RSQB));
999 IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n",
1000 card->name,
1001 readl(SAR_REG_RSQH),
1002 readl(SAR_REG_RSQB),
1003 readl(SAR_REG_RSQT));
1004
1005 return 0;
1006 }
1007
1008 static void
1009 deinit_rsq(struct idt77252_dev *card)
1010 {
1011 pci_free_consistent(card->pcidev, RSQSIZE,
1012 card->rsq.base, card->rsq.paddr);
1013 }
1014
1015 static void
1016 dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe)
1017 {
1018 struct atm_vcc *vcc;
1019 struct sk_buff *skb;
1020 struct rx_pool *rpp;
1021 struct vc_map *vc;
1022 u32 header, vpi, vci;
1023 u32 stat;
1024 int i;
1025
1026 stat = le32_to_cpu(rsqe->word_4);
1027
1028 if (stat & SAR_RSQE_IDLE) {
1029 RXPRINTK("%s: message about inactive connection.\n",
1030 card->name);
1031 return;
1032 }
1033
1034 skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2));
1035 if (skb == NULL) {
1036 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n",
1037 card->name, __FUNCTION__,
1038 le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2),
1039 le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4));
1040 return;
1041 }
1042
1043 header = le32_to_cpu(rsqe->word_1);
1044 vpi = (header >> 16) & 0x00ff;
1045 vci = (header >> 0) & 0xffff;
1046
1047 RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n",
1048 card->name, vpi, vci, skb, skb->data);
1049
1050 if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) {
1051 printk("%s: SDU received for out-of-range vc %u.%u\n",
1052 card->name, vpi, vci);
1053 recycle_rx_skb(card, skb);
1054 return;
1055 }
1056
1057 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1058 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1059 printk("%s: SDU received on non RX vc %u.%u\n",
1060 card->name, vpi, vci);
1061 recycle_rx_skb(card, skb);
1062 return;
1063 }
1064
1065 vcc = vc->rx_vcc;
1066
1067 pci_dma_sync_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1068 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1069
1070 if ((vcc->qos.aal == ATM_AAL0) ||
1071 (vcc->qos.aal == ATM_AAL34)) {
1072 struct sk_buff *sb;
1073 unsigned char *cell;
1074 u32 aal0;
1075
1076 cell = skb->data;
1077 for (i = (stat & SAR_RSQE_CELLCNT); i; i--) {
1078 if ((sb = dev_alloc_skb(64)) == NULL) {
1079 printk("%s: Can't allocate buffers for aal0.\n",
1080 card->name);
1081 atomic_add(i, &vcc->stats->rx_drop);
1082 break;
1083 }
1084 if (!atm_charge(vcc, sb->truesize)) {
1085 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n",
1086 card->name);
1087 atomic_add(i - 1, &vcc->stats->rx_drop);
1088 dev_kfree_skb(sb);
1089 break;
1090 }
1091 aal0 = (vpi << ATM_HDR_VPI_SHIFT) |
1092 (vci << ATM_HDR_VCI_SHIFT);
1093 aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0;
1094 aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0;
1095
1096 *((u32 *) sb->data) = aal0;
1097 skb_put(sb, sizeof(u32));
1098 memcpy(skb_put(sb, ATM_CELL_PAYLOAD),
1099 cell, ATM_CELL_PAYLOAD);
1100
1101 ATM_SKB(sb)->vcc = vcc;
1102 do_gettimeofday(&sb->stamp);
1103 vcc->push(vcc, sb);
1104 atomic_inc(&vcc->stats->rx);
1105
1106 cell += ATM_CELL_PAYLOAD;
1107 }
1108
1109 recycle_rx_skb(card, skb);
1110 return;
1111 }
1112 if (vcc->qos.aal != ATM_AAL5) {
1113 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n",
1114 card->name, vcc->qos.aal);
1115 recycle_rx_skb(card, skb);
1116 return;
1117 }
1118 skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD;
1119
1120 rpp = &vc->rcv.rx_pool;
1121
1122 rpp->len += skb->len;
1123 if (!rpp->count++)
1124 rpp->first = skb;
1125 *rpp->last = skb;
1126 rpp->last = &skb->next;
1127
1128 if (stat & SAR_RSQE_EPDU) {
1129 unsigned char *l1l2;
1130 unsigned int len;
1131
1132 l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6);
1133
1134 len = (l1l2[0] << 8) | l1l2[1];
1135 len = len ? len : 0x10000;
1136
1137 RXPRINTK("%s: PDU has %d bytes.\n", card->name, len);
1138
1139 if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) {
1140 RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. "
1141 "(CDC: %08x)\n",
1142 card->name, len, rpp->len, readl(SAR_REG_CDC));
1143 recycle_rx_pool_skb(card, rpp);
1144 atomic_inc(&vcc->stats->rx_err);
1145 return;
1146 }
1147 if (stat & SAR_RSQE_CRC) {
1148 RXPRINTK("%s: AAL5 CRC error.\n", card->name);
1149 recycle_rx_pool_skb(card, rpp);
1150 atomic_inc(&vcc->stats->rx_err);
1151 return;
1152 }
1153 if (rpp->count > 1) {
1154 struct sk_buff *sb;
1155
1156 skb = dev_alloc_skb(rpp->len);
1157 if (!skb) {
1158 RXPRINTK("%s: Can't alloc RX skb.\n",
1159 card->name);
1160 recycle_rx_pool_skb(card, rpp);
1161 atomic_inc(&vcc->stats->rx_err);
1162 return;
1163 }
1164 if (!atm_charge(vcc, skb->truesize)) {
1165 recycle_rx_pool_skb(card, rpp);
1166 dev_kfree_skb(skb);
1167 return;
1168 }
1169 sb = rpp->first;
1170 for (i = 0; i < rpp->count; i++) {
1171 memcpy(skb_put(skb, sb->len),
1172 sb->data, sb->len);
1173 sb = sb->next;
1174 }
1175
1176 recycle_rx_pool_skb(card, rpp);
1177
1178 skb_trim(skb, len);
1179 ATM_SKB(skb)->vcc = vcc;
1180 do_gettimeofday(&skb->stamp);
1181
1182 vcc->push(vcc, skb);
1183 atomic_inc(&vcc->stats->rx);
1184
1185 return;
1186 }
1187
1188 skb->next = NULL;
1189 flush_rx_pool(card, rpp);
1190
1191 if (!atm_charge(vcc, skb->truesize)) {
1192 recycle_rx_skb(card, skb);
1193 return;
1194 }
1195
1196 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1197 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1198 sb_pool_remove(card, skb);
1199
1200 skb_trim(skb, len);
1201 ATM_SKB(skb)->vcc = vcc;
1202 do_gettimeofday(&skb->stamp);
1203
1204 vcc->push(vcc, skb);
1205 atomic_inc(&vcc->stats->rx);
1206
1207 if (skb->truesize > SAR_FB_SIZE_3)
1208 add_rx_skb(card, 3, SAR_FB_SIZE_3, 1);
1209 else if (skb->truesize > SAR_FB_SIZE_2)
1210 add_rx_skb(card, 2, SAR_FB_SIZE_2, 1);
1211 else if (skb->truesize > SAR_FB_SIZE_1)
1212 add_rx_skb(card, 1, SAR_FB_SIZE_1, 1);
1213 else
1214 add_rx_skb(card, 0, SAR_FB_SIZE_0, 1);
1215 return;
1216 }
1217 }
1218
1219 static void
1220 idt77252_rx(struct idt77252_dev *card)
1221 {
1222 struct rsq_entry *rsqe;
1223
1224 if (card->rsq.next == card->rsq.last)
1225 rsqe = card->rsq.base;
1226 else
1227 rsqe = card->rsq.next + 1;
1228
1229 if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) {
1230 RXPRINTK("%s: no entry in RSQ.\n", card->name);
1231 return;
1232 }
1233
1234 do {
1235 dequeue_rx(card, rsqe);
1236 rsqe->word_4 = 0;
1237 card->rsq.next = rsqe;
1238 if (card->rsq.next == card->rsq.last)
1239 rsqe = card->rsq.base;
1240 else
1241 rsqe = card->rsq.next + 1;
1242 } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID);
1243
1244 writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base,
1245 SAR_REG_RSQH);
1246 }
1247
1248 static void
1249 idt77252_rx_raw(struct idt77252_dev *card)
1250 {
1251 struct sk_buff *queue;
1252 u32 head, tail;
1253 struct atm_vcc *vcc;
1254 struct vc_map *vc;
1255 struct sk_buff *sb;
1256
1257 if (card->raw_cell_head == NULL) {
1258 u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1));
1259 card->raw_cell_head = sb_pool_skb(card, handle);
1260 }
1261
1262 queue = card->raw_cell_head;
1263 if (!queue)
1264 return;
1265
1266 head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16);
1267 tail = readl(SAR_REG_RAWCT);
1268
1269 pci_dma_sync_single(card->pcidev, IDT77252_PRV_PADDR(queue),
1270 queue->end - queue->head - 16, PCI_DMA_FROMDEVICE);
1271
1272 while (head != tail) {
1273 unsigned int vpi, vci, pti;
1274 u32 header;
1275
1276 header = le32_to_cpu(*(u32 *) &queue->data[0]);
1277
1278 vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT;
1279 vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT;
1280 pti = (header & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT;
1281
1282 #ifdef CONFIG_ATM_IDT77252_DEBUG
1283 if (debug & DBG_RAW_CELL) {
1284 int i;
1285
1286 printk("%s: raw cell %x.%02x.%04x.%x.%x\n",
1287 card->name, (header >> 28) & 0x000f,
1288 (header >> 20) & 0x00ff,
1289 (header >> 4) & 0xffff,
1290 (header >> 1) & 0x0007,
1291 (header >> 0) & 0x0001);
1292 for (i = 16; i < 64; i++)
1293 printk(" %02x", queue->data[i]);
1294 printk("\n");
1295 }
1296 #endif
1297
1298 if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) {
1299 RPRINTK("%s: SDU received for out-of-range vc %u.%u\n",
1300 card->name, vpi, vci);
1301 goto drop;
1302 }
1303
1304 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1305 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1306 RPRINTK("%s: SDU received on non RX vc %u.%u\n",
1307 card->name, vpi, vci);
1308 goto drop;
1309 }
1310
1311 vcc = vc->rx_vcc;
1312
1313 if (vcc->qos.aal != ATM_AAL0) {
1314 RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n",
1315 card->name, vpi, vci);
1316 atomic_inc(&vcc->stats->rx_drop);
1317 goto drop;
1318 }
1319
1320 if ((sb = dev_alloc_skb(64)) == NULL) {
1321 printk("%s: Can't allocate buffers for AAL0.\n",
1322 card->name);
1323 atomic_inc(&vcc->stats->rx_err);
1324 goto drop;
1325 }
1326
1327 if ((vcc->sk != NULL) && !atm_charge(vcc, sb->truesize)) {
1328 RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n",
1329 card->name);
1330 dev_kfree_skb(sb);
1331 goto drop;
1332 }
1333
1334 *((u32 *) sb->data) = header;
1335 skb_put(sb, sizeof(u32));
1336 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), &(queue->data[16]),
1337 ATM_CELL_PAYLOAD);
1338
1339 ATM_SKB(sb)->vcc = vcc;
1340 do_gettimeofday(&sb->stamp);
1341 vcc->push(vcc, sb);
1342 atomic_inc(&vcc->stats->rx);
1343
1344 drop:
1345 skb_pull(queue, 64);
1346
1347 head = IDT77252_PRV_PADDR(queue)
1348 + (queue->data - queue->head - 16);
1349
1350 if (queue->len < 128) {
1351 struct sk_buff *next;
1352 u32 handle;
1353
1354 head = le32_to_cpu(*(u32 *) &queue->data[0]);
1355 handle = le32_to_cpu(*(u32 *) &queue->data[4]);
1356
1357 next = sb_pool_skb(card, handle);
1358 recycle_rx_skb(card, queue);
1359
1360 if (next) {
1361 card->raw_cell_head = next;
1362 queue = card->raw_cell_head;
1363 pci_dma_sync_single(card->pcidev,
1364 IDT77252_PRV_PADDR(queue),
1365 queue->end - queue->data,
1366 PCI_DMA_FROMDEVICE);
1367 } else {
1368 card->raw_cell_head = NULL;
1369 printk("%s: raw cell queue overrun\n",
1370 card->name);
1371 break;
1372 }
1373 }
1374 }
1375 }
1376
1377
1378 /*****************************************************************************/
1379 /* */
1380 /* TSQ Handling */
1381 /* */
1382 /*****************************************************************************/
1383
1384 static int
1385 init_tsq(struct idt77252_dev *card)
1386 {
1387 struct tsq_entry *tsqe;
1388
1389 card->tsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
1390 &card->tsq.paddr);
1391 if (card->tsq.base == NULL) {
1392 printk("%s: can't allocate TSQ.\n", card->name);
1393 return -1;
1394 }
1395 memset(card->tsq.base, 0, TSQSIZE);
1396
1397 card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1;
1398 card->tsq.next = card->tsq.last;
1399 for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++)
1400 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1401
1402 writel(card->tsq.paddr, SAR_REG_TSQB);
1403 writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base,
1404 SAR_REG_TSQH);
1405
1406 return 0;
1407 }
1408
1409 static void
1410 deinit_tsq(struct idt77252_dev *card)
1411 {
1412 pci_free_consistent(card->pcidev, TSQSIZE,
1413 card->tsq.base, card->tsq.paddr);
1414 }
1415
1416 static void
1417 idt77252_tx(struct idt77252_dev *card)
1418 {
1419 struct tsq_entry *tsqe;
1420 unsigned int vpi, vci;
1421 struct vc_map *vc;
1422 u32 conn, stat;
1423
1424 if (card->tsq.next == card->tsq.last)
1425 tsqe = card->tsq.base;
1426 else
1427 tsqe = card->tsq.next + 1;
1428
1429 TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe,
1430 card->tsq.base, card->tsq.next, card->tsq.last);
1431 TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n",
1432 readl(SAR_REG_TSQB),
1433 readl(SAR_REG_TSQT),
1434 readl(SAR_REG_TSQH));
1435
1436 stat = le32_to_cpu(tsqe->word_2);
1437
1438 if (stat & SAR_TSQE_INVALID)
1439 return;
1440
1441 do {
1442 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe,
1443 le32_to_cpu(tsqe->word_1),
1444 le32_to_cpu(tsqe->word_2));
1445
1446 switch (stat & SAR_TSQE_TYPE) {
1447 case SAR_TSQE_TYPE_TIMER:
1448 TXPRINTK("%s: Timer RollOver detected.\n", card->name);
1449 break;
1450
1451 case SAR_TSQE_TYPE_IDLE:
1452
1453 conn = le32_to_cpu(tsqe->word_1);
1454
1455 if (SAR_TSQE_TAG(stat) == 0x10) {
1456 #ifdef NOTDEF
1457 printk("%s: Connection %d halted.\n",
1458 card->name,
1459 le32_to_cpu(tsqe->word_1) & 0x1fff);
1460 #endif
1461 break;
1462 }
1463
1464 vc = card->vcs[conn & 0x1fff];
1465 if (!vc) {
1466 printk("%s: could not find VC from conn %d\n",
1467 card->name, conn & 0x1fff);
1468 break;
1469 }
1470
1471 printk("%s: Connection %d IDLE.\n",
1472 card->name, vc->index);
1473
1474 set_bit(VCF_IDLE, &vc->flags);
1475 break;
1476
1477 case SAR_TSQE_TYPE_TSR:
1478
1479 conn = le32_to_cpu(tsqe->word_1);
1480
1481 vc = card->vcs[conn & 0x1fff];
1482 if (!vc) {
1483 printk("%s: no VC at index %d\n",
1484 card->name,
1485 le32_to_cpu(tsqe->word_1) & 0x1fff);
1486 break;
1487 }
1488
1489 drain_scq(card, vc);
1490 break;
1491
1492 case SAR_TSQE_TYPE_TBD_COMP:
1493
1494 conn = le32_to_cpu(tsqe->word_1);
1495
1496 vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff;
1497 vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff;
1498
1499 if (vpi >= (1 << card->vpibits) ||
1500 vci >= (1 << card->vcibits)) {
1501 printk("%s: TBD complete: "
1502 "out of range VPI.VCI %u.%u\n",
1503 card->name, vpi, vci);
1504 break;
1505 }
1506
1507 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1508 if (!vc) {
1509 printk("%s: TBD complete: "
1510 "no VC at VPI.VCI %u.%u\n",
1511 card->name, vpi, vci);
1512 break;
1513 }
1514
1515 drain_scq(card, vc);
1516 break;
1517 }
1518
1519 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1520
1521 card->tsq.next = tsqe;
1522 if (card->tsq.next == card->tsq.last)
1523 tsqe = card->tsq.base;
1524 else
1525 tsqe = card->tsq.next + 1;
1526
1527 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe,
1528 card->tsq.base, card->tsq.next, card->tsq.last);
1529
1530 stat = le32_to_cpu(tsqe->word_2);
1531
1532 } while (!(stat & SAR_TSQE_INVALID));
1533
1534 writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base,
1535 SAR_REG_TSQH);
1536
1537 XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n",
1538 card->index, readl(SAR_REG_TSQH),
1539 readl(SAR_REG_TSQT), card->tsq.next);
1540 }
1541
1542
1543 static void
1544 tst_timer(unsigned long data)
1545 {
1546 struct idt77252_dev *card = (struct idt77252_dev *)data;
1547 unsigned long base, idle, jump;
1548 unsigned long flags;
1549 u32 pc;
1550 int e;
1551
1552 spin_lock_irqsave(&card->tst_lock, flags);
1553
1554 base = card->tst[card->tst_index];
1555 idle = card->tst[card->tst_index ^ 1];
1556
1557 if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) {
1558 jump = base + card->tst_size - 2;
1559
1560 pc = readl(SAR_REG_NOW) >> 2;
1561 if ((pc ^ idle) & ~(card->tst_size - 1)) {
1562 mod_timer(&card->tst_timer, jiffies + 1);
1563 goto out;
1564 }
1565
1566 clear_bit(TST_SWITCH_WAIT, &card->tst_state);
1567
1568 card->tst_index ^= 1;
1569 write_sram(card, jump, TSTE_OPC_JMP | (base << 2));
1570
1571 base = card->tst[card->tst_index];
1572 idle = card->tst[card->tst_index ^ 1];
1573
1574 for (e = 0; e < card->tst_size - 2; e++) {
1575 if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) {
1576 write_sram(card, idle + e,
1577 card->soft_tst[e].tste & TSTE_MASK);
1578 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE);
1579 }
1580 }
1581 }
1582
1583 if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) {
1584
1585 for (e = 0; e < card->tst_size - 2; e++) {
1586 if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) {
1587 write_sram(card, idle + e,
1588 card->soft_tst[e].tste & TSTE_MASK);
1589 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE);
1590 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1591 }
1592 }
1593
1594 jump = base + card->tst_size - 2;
1595
1596 write_sram(card, jump, TSTE_OPC_NULL);
1597 set_bit(TST_SWITCH_WAIT, &card->tst_state);
1598
1599 mod_timer(&card->tst_timer, jiffies + 1);
1600 }
1601
1602 out:
1603 spin_unlock_irqrestore(&card->tst_lock, flags);
1604 }
1605
1606 static int
1607 __fill_tst(struct idt77252_dev *card, struct vc_map *vc,
1608 int n, unsigned int opc)
1609 {
1610 unsigned long cl, avail;
1611 unsigned long idle;
1612 int e, r;
1613 u32 data;
1614
1615 avail = card->tst_size - 2;
1616 for (e = 0; e < avail; e++) {
1617 if (card->soft_tst[e].vc == NULL)
1618 break;
1619 }
1620 if (e >= avail) {
1621 printk("%s: No free TST entries found\n", card->name);
1622 return -1;
1623 }
1624
1625 NPRINTK("%s: conn %d: first TST entry at %d.\n",
1626 card->name, vc ? vc->index : -1, e);
1627
1628 r = n;
1629 cl = avail;
1630 data = opc & TSTE_OPC_MASK;
1631 if (vc && (opc != TSTE_OPC_NULL))
1632 data = opc | vc->index;
1633
1634 idle = card->tst[card->tst_index ^ 1];
1635
1636 /*
1637 * Fill Soft TST.
1638 */
1639 while (r > 0) {
1640 if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) {
1641 if (vc)
1642 card->soft_tst[e].vc = vc;
1643 else
1644 card->soft_tst[e].vc = (void *)-1;
1645
1646 card->soft_tst[e].tste = data;
1647 if (timer_pending(&card->tst_timer))
1648 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1649 else {
1650 write_sram(card, idle + e, data);
1651 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1652 }
1653
1654 cl -= card->tst_size;
1655 r--;
1656 }
1657
1658 if (++e == avail)
1659 e = 0;
1660 cl += n;
1661 }
1662
1663 return 0;
1664 }
1665
1666 static int
1667 fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc)
1668 {
1669 unsigned long flags;
1670 int res;
1671
1672 spin_lock_irqsave(&card->tst_lock, flags);
1673
1674 res = __fill_tst(card, vc, n, opc);
1675
1676 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1677 if (!timer_pending(&card->tst_timer))
1678 mod_timer(&card->tst_timer, jiffies + 1);
1679
1680 spin_unlock_irqrestore(&card->tst_lock, flags);
1681 return res;
1682 }
1683
1684 static int
1685 __clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1686 {
1687 unsigned long idle;
1688 int e;
1689
1690 idle = card->tst[card->tst_index ^ 1];
1691
1692 for (e = 0; e < card->tst_size - 2; e++) {
1693 if (card->soft_tst[e].vc == vc) {
1694 card->soft_tst[e].vc = NULL;
1695
1696 card->soft_tst[e].tste = TSTE_OPC_VAR;
1697 if (timer_pending(&card->tst_timer))
1698 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1699 else {
1700 write_sram(card, idle + e, TSTE_OPC_VAR);
1701 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1702 }
1703 }
1704 }
1705
1706 return 0;
1707 }
1708
1709 static int
1710 clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1711 {
1712 unsigned long flags;
1713 int res;
1714
1715 spin_lock_irqsave(&card->tst_lock, flags);
1716
1717 res = __clear_tst(card, vc);
1718
1719 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1720 if (!timer_pending(&card->tst_timer))
1721 mod_timer(&card->tst_timer, jiffies + 1);
1722
1723 spin_unlock_irqrestore(&card->tst_lock, flags);
1724 return res;
1725 }
1726
1727 static int
1728 change_tst(struct idt77252_dev *card, struct vc_map *vc,
1729 int n, unsigned int opc)
1730 {
1731 unsigned long flags;
1732 int res;
1733
1734 spin_lock_irqsave(&card->tst_lock, flags);
1735
1736 __clear_tst(card, vc);
1737 res = __fill_tst(card, vc, n, opc);
1738
1739 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1740 if (!timer_pending(&card->tst_timer))
1741 mod_timer(&card->tst_timer, jiffies + 1);
1742
1743 spin_unlock_irqrestore(&card->tst_lock, flags);
1744 return res;
1745 }
1746
1747
1748 static int
1749 set_tct(struct idt77252_dev *card, struct vc_map *vc)
1750 {
1751 unsigned long tct;
1752
1753 tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE);
1754
1755 switch (vc->class) {
1756 case SCHED_CBR:
1757 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1758 card->name, tct, vc->scq->scd);
1759
1760 write_sram(card, tct + 0, TCT_CBR | vc->scq->scd);
1761 write_sram(card, tct + 1, 0);
1762 write_sram(card, tct + 2, 0);
1763 write_sram(card, tct + 3, 0);
1764 write_sram(card, tct + 4, 0);
1765 write_sram(card, tct + 5, 0);
1766 write_sram(card, tct + 6, 0);
1767 write_sram(card, tct + 7, 0);
1768 break;
1769
1770 case SCHED_UBR:
1771 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1772 card->name, tct, vc->scq->scd);
1773
1774 write_sram(card, tct + 0, TCT_UBR | vc->scq->scd);
1775 write_sram(card, tct + 1, 0);
1776 write_sram(card, tct + 2, TCT_TSIF);
1777 write_sram(card, tct + 3, TCT_HALT | TCT_IDLE);
1778 write_sram(card, tct + 4, 0);
1779 write_sram(card, tct + 5, vc->init_er);
1780 write_sram(card, tct + 6, 0);
1781 write_sram(card, tct + 7, TCT_FLAG_UBR);
1782 break;
1783
1784 case SCHED_VBR:
1785 case SCHED_ABR:
1786 default:
1787 return -ENOSYS;
1788 }
1789
1790 return 0;
1791 }
1792
1793 /*****************************************************************************/
1794 /* */
1795 /* FBQ Handling */
1796 /* */
1797 /*****************************************************************************/
1798
1799 static __inline__ int
1800 idt77252_fbq_level(struct idt77252_dev *card, int queue)
1801 {
1802 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f;
1803 }
1804
1805 static __inline__ int
1806 idt77252_fbq_full(struct idt77252_dev *card, int queue)
1807 {
1808 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f;
1809 }
1810
1811 static int
1812 push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue)
1813 {
1814 unsigned long flags;
1815 u32 handle;
1816 u32 addr;
1817
1818 skb->data = skb->tail = skb->head;
1819 skb->len = 0;
1820
1821 skb_reserve(skb, 16);
1822
1823 switch (queue) {
1824 case 0:
1825 skb_put(skb, SAR_FB_SIZE_0);
1826 break;
1827 case 1:
1828 skb_put(skb, SAR_FB_SIZE_1);
1829 break;
1830 case 2:
1831 skb_put(skb, SAR_FB_SIZE_2);
1832 break;
1833 case 3:
1834 skb_put(skb, SAR_FB_SIZE_3);
1835 break;
1836 default:
1837 dev_kfree_skb(skb);
1838 return -1;
1839 }
1840
1841 if (idt77252_fbq_full(card, queue))
1842 return -1;
1843
1844 memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32));
1845
1846 handle = IDT77252_PRV_POOL(skb);
1847 addr = IDT77252_PRV_PADDR(skb);
1848
1849 spin_lock_irqsave(&card->cmd_lock, flags);
1850 writel(handle, card->fbq[queue]);
1851 writel(addr, card->fbq[queue]);
1852 spin_unlock_irqrestore(&card->cmd_lock, flags);
1853
1854 return 0;
1855 }
1856
1857 static void
1858 add_rx_skb(struct idt77252_dev *card, int queue,
1859 unsigned int size, unsigned int count)
1860 {
1861 struct sk_buff *skb;
1862 dma_addr_t paddr;
1863 u32 handle;
1864
1865 while (count--) {
1866 skb = dev_alloc_skb(size);
1867 if (!skb)
1868 return;
1869
1870 if (sb_pool_add(card, skb, queue)) {
1871 printk("%s: SB POOL full\n", __FUNCTION__);
1872 goto outfree;
1873 }
1874
1875 paddr = pci_map_single(card->pcidev, skb->data,
1876 skb->end - skb->data,
1877 PCI_DMA_FROMDEVICE);
1878 IDT77252_PRV_PADDR(skb) = paddr;
1879
1880 if (push_rx_skb(card, skb, queue)) {
1881 printk("%s: FB QUEUE full\n", __FUNCTION__);
1882 goto outunmap;
1883 }
1884 }
1885
1886 return;
1887
1888 outunmap:
1889 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1890 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1891
1892 handle = IDT77252_PRV_POOL(skb);
1893 card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL;
1894
1895 outfree:
1896 dev_kfree_skb(skb);
1897 }
1898
1899
1900 static void
1901 recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb)
1902 {
1903 u32 handle = IDT77252_PRV_POOL(skb);
1904 int err;
1905
1906 err = push_rx_skb(card, skb, POOL_QUEUE(handle));
1907 if (err) {
1908 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1909 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1910 sb_pool_remove(card, skb);
1911 dev_kfree_skb(skb);
1912 }
1913 }
1914
1915 static void
1916 flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp)
1917 {
1918 rpp->len = 0;
1919 rpp->count = 0;
1920 rpp->first = NULL;
1921 rpp->last = &rpp->first;
1922 }
1923
1924 static void
1925 recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp)
1926 {
1927 struct sk_buff *skb, *next;
1928 int i;
1929
1930 skb = rpp->first;
1931 for (i = 0; i < rpp->count; i++) {
1932 next = skb->next;
1933 skb->next = NULL;
1934 recycle_rx_skb(card, skb);
1935 skb = next;
1936 }
1937 flush_rx_pool(card, rpp);
1938 }
1939
1940 /*****************************************************************************/
1941 /* */
1942 /* ATM Interface */
1943 /* */
1944 /*****************************************************************************/
1945
1946 static void
1947 idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr)
1948 {
1949 write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value);
1950 }
1951
1952 static unsigned char
1953 idt77252_phy_get(struct atm_dev *dev, unsigned long addr)
1954 {
1955 return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff));
1956 }
1957
1958 static int
1959 idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam)
1960 {
1961 struct atm_dev *dev = vcc->dev;
1962 struct idt77252_dev *card = dev->dev_data;
1963 struct vc_map *vc = vcc->dev_data;
1964 int err;
1965
1966 if (vc == NULL) {
1967 printk("%s: NULL connection in send().\n", card->name);
1968 atomic_inc(&vcc->stats->tx_err);
1969 dev_kfree_skb(skb);
1970 return -EINVAL;
1971 }
1972 if (!test_bit(VCF_TX, &vc->flags)) {
1973 printk("%s: Trying to transmit on a non-tx VC.\n", card->name);
1974 atomic_inc(&vcc->stats->tx_err);
1975 dev_kfree_skb(skb);
1976 return -EINVAL;
1977 }
1978
1979 switch (vcc->qos.aal) {
1980 case ATM_AAL0:
1981 case ATM_AAL1:
1982 case ATM_AAL5:
1983 break;
1984 default:
1985 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
1986 atomic_inc(&vcc->stats->tx_err);
1987 dev_kfree_skb(skb);
1988 return -EINVAL;
1989 }
1990
1991 if (ATM_SKB(skb)->iovcnt != 0) {
1992 printk("%s: No scatter-gather yet.\n", card->name);
1993 atomic_inc(&vcc->stats->tx_err);
1994 dev_kfree_skb(skb);
1995 return -EINVAL;
1996 }
1997 ATM_SKB(skb)->vcc = vcc;
1998
1999 err = queue_skb(card, vc, skb, oam);
2000 if (err) {
2001 atomic_inc(&vcc->stats->tx_err);
2002 dev_kfree_skb(skb);
2003 return err;
2004 }
2005
2006 return 0;
2007 }
2008
2009 int
2010 idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb)
2011 {
2012 return idt77252_send_skb(vcc, skb, 0);
2013 }
2014
2015 static int
2016 idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags)
2017 {
2018 struct atm_dev *dev = vcc->dev;
2019 struct idt77252_dev *card = dev->dev_data;
2020 struct sk_buff *skb;
2021
2022 skb = dev_alloc_skb(64);
2023 if (!skb) {
2024 printk("%s: Out of memory in send_oam().\n", card->name);
2025 atomic_inc(&vcc->stats->tx_err);
2026 return -ENOMEM;
2027 }
2028 atomic_add(skb->truesize + ATM_PDU_OVHD, &vcc->tx_inuse);
2029 ATM_SKB(skb)->iovcnt = 0;
2030
2031 memcpy(skb_put(skb, 52), cell, 52);
2032
2033 return idt77252_send_skb(vcc, skb, 1);
2034 }
2035
2036 static __inline__ unsigned int
2037 idt77252_fls(unsigned int x)
2038 {
2039 int r = 1;
2040
2041 if (x == 0)
2042 return 0;
2043 if (x & 0xffff0000) {
2044 x >>= 16;
2045 r += 16;
2046 }
2047 if (x & 0xff00) {
2048 x >>= 8;
2049 r += 8;
2050 }
2051 if (x & 0xf0) {
2052 x >>= 4;
2053 r += 4;
2054 }
2055 if (x & 0xc) {
2056 x >>= 2;
2057 r += 2;
2058 }
2059 if (x & 0x2)
2060 r += 1;
2061 return r;
2062 }
2063
2064 static u16
2065 idt77252_int_to_atmfp(unsigned int rate)
2066 {
2067 u16 m, e;
2068
2069 if (rate == 0)
2070 return 0;
2071 e = idt77252_fls(rate) - 1;
2072 if (e < 9)
2073 m = (rate - (1 << e)) << (9 - e);
2074 else if (e == 9)
2075 m = (rate - (1 << e));
2076 else /* e > 9 */
2077 m = (rate - (1 << e)) >> (e - 9);
2078 return 0x4000 | (e << 9) | m;
2079 }
2080
2081 static u8
2082 idt77252_rate_logindex(struct idt77252_dev *card, int pcr)
2083 {
2084 u16 afp;
2085
2086 afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr);
2087 if (pcr < 0)
2088 return rate_to_log[(afp >> 5) & 0x1ff];
2089 return rate_to_log[((afp >> 5) + 1) & 0x1ff];
2090 }
2091
2092 static void
2093 idt77252_est_timer(unsigned long data)
2094 {
2095 struct vc_map *vc = (struct vc_map *)data;
2096 struct idt77252_dev *card = vc->card;
2097 struct rate_estimator *est;
2098 unsigned long flags;
2099 u32 rate, cps;
2100 u64 ncells;
2101 u8 lacr;
2102
2103 spin_lock_irqsave(&vc->lock, flags);
2104 est = vc->estimator;
2105 if (!est)
2106 goto out;
2107
2108 ncells = est->cells;
2109
2110 rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval);
2111 est->last_cells = ncells;
2112 est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log;
2113 est->cps = (est->avcps + 0x1f) >> 5;
2114
2115 cps = est->cps;
2116 if (cps < (est->maxcps >> 4))
2117 cps = est->maxcps >> 4;
2118
2119 lacr = idt77252_rate_logindex(card, cps);
2120 if (lacr > vc->max_er)
2121 lacr = vc->max_er;
2122
2123 if (lacr != vc->lacr) {
2124 vc->lacr = lacr;
2125 writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ);
2126 }
2127
2128 est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2129 add_timer(&est->timer);
2130
2131 out:
2132 spin_unlock_irqrestore(&vc->lock, flags);
2133 }
2134
2135 static struct rate_estimator *
2136 idt77252_init_est(struct vc_map *vc, int pcr)
2137 {
2138 struct rate_estimator *est;
2139
2140 est = kmalloc(sizeof(struct rate_estimator), GFP_KERNEL);
2141 if (!est)
2142 return NULL;
2143 memset(est, 0, sizeof(*est));
2144
2145 est->maxcps = pcr < 0 ? -pcr : pcr;
2146 est->cps = est->maxcps;
2147 est->avcps = est->cps << 5;
2148
2149 est->interval = 2; /* XXX: make this configurable */
2150 est->ewma_log = 2; /* XXX: make this configurable */
2151 init_timer(&est->timer);
2152 est->timer.data = (unsigned long)vc;
2153 est->timer.function = idt77252_est_timer;
2154
2155 est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2156 add_timer(&est->timer);
2157
2158 return est;
2159 }
2160
2161 static int
2162 idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc,
2163 struct atm_vcc *vcc, struct atm_qos *qos)
2164 {
2165 int tst_free, tst_used, tst_entries;
2166 unsigned long tmpl, modl;
2167 int tcr, tcra;
2168
2169 if ((qos->txtp.max_pcr == 0) &&
2170 (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) {
2171 printk("%s: trying to open a CBR VC with cell rate = 0\n",
2172 card->name);
2173 return -EINVAL;
2174 }
2175
2176 tst_used = 0;
2177 tst_free = card->tst_free;
2178 if (test_bit(VCF_TX, &vc->flags))
2179 tst_used = vc->ntste;
2180 tst_free += tst_used;
2181
2182 tcr = atm_pcr_goal(&qos->txtp);
2183 tcra = tcr >= 0 ? tcr : -tcr;
2184
2185 TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra);
2186
2187 tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2);
2188 modl = tmpl % (unsigned long)card->utopia_pcr;
2189
2190 tst_entries = (int) (tmpl / card->utopia_pcr);
2191 if (tcr > 0) {
2192 if (modl > 0)
2193 tst_entries++;
2194 } else if (tcr == 0) {
2195 tst_entries = tst_free - SAR_TST_RESERVED;
2196 if (tst_entries <= 0) {
2197 printk("%s: no CBR bandwidth free.\n", card->name);
2198 return -ENOSR;
2199 }
2200 }
2201
2202 if (tst_entries == 0) {
2203 printk("%s: selected CBR bandwidth < granularity.\n",
2204 card->name);
2205 return -EINVAL;
2206 }
2207
2208 if (tst_entries > (tst_free - SAR_TST_RESERVED)) {
2209 printk("%s: not enough CBR bandwidth free.\n", card->name);
2210 return -ENOSR;
2211 }
2212
2213 vc->ntste = tst_entries;
2214
2215 card->tst_free = tst_free - tst_entries;
2216 if (test_bit(VCF_TX, &vc->flags)) {
2217 if (tst_used == tst_entries)
2218 return 0;
2219
2220 OPRINTK("%s: modify %d -> %d entries in TST.\n",
2221 card->name, tst_used, tst_entries);
2222 change_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2223 return 0;
2224 }
2225
2226 OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries);
2227 fill_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2228 return 0;
2229 }
2230
2231 static int
2232 idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc,
2233 struct atm_vcc *vcc, struct atm_qos *qos)
2234 {
2235 unsigned long flags;
2236 int tcr;
2237
2238 spin_lock_irqsave(&vc->lock, flags);
2239 if (vc->estimator) {
2240 del_timer(&vc->estimator->timer);
2241 kfree(vc->estimator);
2242 vc->estimator = NULL;
2243 }
2244 spin_unlock_irqrestore(&vc->lock, flags);
2245
2246 tcr = atm_pcr_goal(&qos->txtp);
2247 if (tcr == 0)
2248 tcr = card->link_pcr;
2249
2250 vc->estimator = idt77252_init_est(vc, tcr);
2251
2252 vc->class = SCHED_UBR;
2253 vc->init_er = idt77252_rate_logindex(card, tcr);
2254 vc->lacr = vc->init_er;
2255 if (tcr < 0)
2256 vc->max_er = vc->init_er;
2257 else
2258 vc->max_er = 0xff;
2259
2260 return 0;
2261 }
2262
2263 static int
2264 idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc,
2265 struct atm_vcc *vcc, struct atm_qos *qos)
2266 {
2267 int error;
2268
2269 if (test_bit(VCF_TX, &vc->flags))
2270 return -EBUSY;
2271
2272 switch (qos->txtp.traffic_class) {
2273 case ATM_CBR:
2274 vc->class = SCHED_CBR;
2275 break;
2276
2277 case ATM_UBR:
2278 vc->class = SCHED_UBR;
2279 break;
2280
2281 case ATM_VBR:
2282 case ATM_ABR:
2283 default:
2284 return -EPROTONOSUPPORT;
2285 }
2286
2287 vc->scq = alloc_scq(card, vc->class);
2288 if (!vc->scq) {
2289 printk("%s: can't get SCQ.\n", card->name);
2290 return -ENOMEM;
2291 }
2292
2293 vc->scq->scd = get_free_scd(card, vc);
2294 if (vc->scq->scd == 0) {
2295 printk("%s: no SCD available.\n", card->name);
2296 free_scq(card, vc->scq);
2297 return -ENOMEM;
2298 }
2299
2300 fill_scd(card, vc->scq, vc->class);
2301
2302 if (set_tct(card, vc)) {
2303 printk("%s: class %d not supported.\n",
2304 card->name, qos->txtp.traffic_class);
2305
2306 card->scd2vc[vc->scd_index] = NULL;
2307 free_scq(card, vc->scq);
2308 return -EPROTONOSUPPORT;
2309 }
2310
2311 switch (vc->class) {
2312 case SCHED_CBR:
2313 error = idt77252_init_cbr(card, vc, vcc, qos);
2314 if (error) {
2315 card->scd2vc[vc->scd_index] = NULL;
2316 free_scq(card, vc->scq);
2317 return error;
2318 }
2319
2320 clear_bit(VCF_IDLE, &vc->flags);
2321 writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ);
2322 break;
2323
2324 case SCHED_UBR:
2325 error = idt77252_init_ubr(card, vc, vcc, qos);
2326 if (error) {
2327 card->scd2vc[vc->scd_index] = NULL;
2328 free_scq(card, vc->scq);
2329 return error;
2330 }
2331
2332 set_bit(VCF_IDLE, &vc->flags);
2333 break;
2334 }
2335
2336 vc->tx_vcc = vcc;
2337 set_bit(VCF_TX, &vc->flags);
2338 return 0;
2339 }
2340
2341 static int
2342 idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc,
2343 struct atm_vcc *vcc, struct atm_qos *qos)
2344 {
2345 unsigned long flags;
2346 unsigned long addr;
2347 u32 rcte = 0;
2348
2349 if (test_bit(VCF_RX, &vc->flags))
2350 return -EBUSY;
2351
2352 vc->rx_vcc = vcc;
2353 set_bit(VCF_RX, &vc->flags);
2354
2355 if ((vcc->vci == 3) || (vcc->vci == 4))
2356 return 0;
2357
2358 flush_rx_pool(card, &vc->rcv.rx_pool);
2359
2360 rcte |= SAR_RCTE_CONNECTOPEN;
2361 rcte |= SAR_RCTE_RAWCELLINTEN;
2362
2363 switch (qos->aal) {
2364 case ATM_AAL0:
2365 rcte |= SAR_RCTE_RCQ;
2366 break;
2367 case ATM_AAL1:
2368 rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */
2369 break;
2370 case ATM_AAL34:
2371 rcte |= SAR_RCTE_AAL34;
2372 break;
2373 case ATM_AAL5:
2374 rcte |= SAR_RCTE_AAL5;
2375 break;
2376 default:
2377 rcte |= SAR_RCTE_RCQ;
2378 break;
2379 }
2380
2381 if (qos->aal != ATM_AAL5)
2382 rcte |= SAR_RCTE_FBP_1;
2383 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2)
2384 rcte |= SAR_RCTE_FBP_3;
2385 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1)
2386 rcte |= SAR_RCTE_FBP_2;
2387 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0)
2388 rcte |= SAR_RCTE_FBP_1;
2389 else
2390 rcte |= SAR_RCTE_FBP_01;
2391
2392 addr = card->rct_base + (vc->index << 2);
2393
2394 OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr);
2395 write_sram(card, addr, rcte);
2396
2397 spin_lock_irqsave(&card->cmd_lock, flags);
2398 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD);
2399 waitfor_idle(card);
2400 spin_unlock_irqrestore(&card->cmd_lock, flags);
2401
2402 return 0;
2403 }
2404
2405 static int
2406 idt77252_find_vcc(struct atm_vcc *vcc, short *vpi, int *vci)
2407 {
2408 struct atm_vcc *walk;
2409
2410 if (*vpi == ATM_VPI_ANY) {
2411 *vpi = 0;
2412 walk = vcc->dev->vccs;
2413 while (walk) {
2414 if ((walk->vci == *vci) && (walk->vpi == *vpi)) {
2415 (*vpi)++;
2416 walk = vcc->dev->vccs;
2417 continue;
2418 }
2419 walk = walk->next;
2420 }
2421 }
2422
2423 if (*vci == ATM_VCI_ANY) {
2424 *vci = ATM_NOT_RSV_VCI;
2425 walk = vcc->dev->vccs;
2426 while (walk) {
2427 if ((walk->vci == *vci) && (walk->vpi == *vpi)) {
2428 (*vci)++;
2429 walk = vcc->dev->vccs;
2430 continue;
2431 }
2432 walk = walk->next;
2433 }
2434 }
2435
2436 return 0;
2437 }
2438
2439 static int
2440 idt77252_open(struct atm_vcc *vcc, short vpi, int vci)
2441 {
2442 struct atm_dev *dev = vcc->dev;
2443 struct idt77252_dev *card = dev->dev_data;
2444 struct vc_map *vc;
2445 unsigned int index;
2446 unsigned int inuse;
2447 int error;
2448
2449 idt77252_find_vcc(vcc, &vpi, &vci);
2450
2451 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC)
2452 return 0;
2453
2454 if (vpi >= (1 << card->vpibits)) {
2455 printk("%s: unsupported VPI: %d\n", card->name, vpi);
2456 return -EINVAL;
2457 }
2458
2459 if (vci >= (1 << card->vcibits)) {
2460 printk("%s: unsupported VCI: %d\n", card->name, vci);
2461 return -EINVAL;
2462 }
2463
2464 vcc->vpi = vpi;
2465 vcc->vci = vci;
2466 set_bit(ATM_VF_ADDR, &vcc->flags);
2467
2468 down(&card->mutex);
2469
2470 OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci);
2471
2472 switch (vcc->qos.aal) {
2473 case ATM_AAL0:
2474 case ATM_AAL1:
2475 case ATM_AAL5:
2476 break;
2477 default:
2478 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
2479 up(&card->mutex);
2480 return -EPROTONOSUPPORT;
2481 }
2482
2483 index = VPCI2VC(card, vpi, vci);
2484 if (!card->vcs[index]) {
2485 card->vcs[index] = kmalloc(sizeof(struct vc_map), GFP_KERNEL);
2486 if (!card->vcs[index]) {
2487 printk("%s: can't alloc vc in open()\n", card->name);
2488 up(&card->mutex);
2489 return -ENOMEM;
2490 }
2491 memset(card->vcs[index], 0, sizeof(struct vc_map));
2492
2493 card->vcs[index]->card = card;
2494 card->vcs[index]->index = index;
2495
2496 spin_lock_init(&card->vcs[index]->lock);
2497 }
2498 vc = card->vcs[index];
2499
2500 vcc->dev_data = vc;
2501
2502 IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n",
2503 card->name, vc->index, vcc->vpi, vcc->vci,
2504 vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--",
2505 vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--",
2506 vcc->qos.rxtp.max_sdu);
2507
2508 inuse = 0;
2509 if (vcc->qos.txtp.traffic_class != ATM_NONE &&
2510 test_bit(VCF_TX, &vc->flags))
2511 inuse = 1;
2512 if (vcc->qos.rxtp.traffic_class != ATM_NONE &&
2513 test_bit(VCF_RX, &vc->flags))
2514 inuse += 2;
2515
2516 if (inuse) {
2517 printk("%s: %s vci already in use.\n", card->name,
2518 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
2519 up(&card->mutex);
2520 return -EADDRINUSE;
2521 }
2522
2523 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2524 error = idt77252_init_tx(card, vc, vcc, &vcc->qos);
2525 if (error) {
2526 up(&card->mutex);
2527 return error;
2528 }
2529 }
2530
2531 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2532 error = idt77252_init_rx(card, vc, vcc, &vcc->qos);
2533 if (error) {
2534 up(&card->mutex);
2535 return error;
2536 }
2537 }
2538
2539 set_bit(ATM_VF_READY, &vcc->flags);
2540 MOD_INC_USE_COUNT;
2541
2542 up(&card->mutex);
2543 return 0;
2544 }
2545
2546 static void
2547 idt77252_close(struct atm_vcc *vcc)
2548 {
2549 struct atm_dev *dev = vcc->dev;
2550 struct idt77252_dev *card = dev->dev_data;
2551 struct vc_map *vc = vcc->dev_data;
2552 unsigned long flags;
2553 unsigned long addr;
2554 int timeout;
2555
2556 down(&card->mutex);
2557
2558 IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n",
2559 card->name, vc->index, vcc->vpi, vcc->vci);
2560
2561 clear_bit(ATM_VF_READY, &vcc->flags);
2562
2563 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2564
2565 spin_lock_irqsave(&vc->lock, flags);
2566 clear_bit(VCF_RX, &vc->flags);
2567 vc->rx_vcc = NULL;
2568 spin_unlock_irqrestore(&vc->lock, flags);
2569
2570 if ((vcc->vci == 3) || (vcc->vci == 4))
2571 goto done;
2572
2573 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2574
2575 spin_lock_irqsave(&card->cmd_lock, flags);
2576 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD);
2577 waitfor_idle(card);
2578 spin_unlock_irqrestore(&card->cmd_lock, flags);
2579
2580 if (vc->rcv.rx_pool.count) {
2581 DPRINTK("%s: closing a VC with pending rx buffers.\n",
2582 card->name);
2583
2584 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2585 }
2586 }
2587
2588 done:
2589 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2590
2591 spin_lock_irqsave(&vc->lock, flags);
2592 clear_bit(VCF_TX, &vc->flags);
2593 clear_bit(VCF_IDLE, &vc->flags);
2594 clear_bit(VCF_RSV, &vc->flags);
2595 vc->tx_vcc = NULL;
2596
2597 if (vc->estimator) {
2598 del_timer(&vc->estimator->timer);
2599 kfree(vc->estimator);
2600 vc->estimator = NULL;
2601 }
2602 spin_unlock_irqrestore(&vc->lock, flags);
2603
2604 timeout = 5 * HZ;
2605 while (atomic_read(&vc->scq->used) > 0) {
2606 timeout = schedule_timeout(timeout);
2607 if (!timeout)
2608 break;
2609 }
2610 if (!timeout)
2611 printk("%s: SCQ drain timeout: %u used\n",
2612 card->name, atomic_read(&vc->scq->used));
2613
2614 writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ);
2615 clear_scd(card, vc->scq, vc->class);
2616
2617 if (vc->class == SCHED_CBR) {
2618 clear_tst(card, vc);
2619 card->tst_free += vc->ntste;
2620 vc->ntste = 0;
2621 }
2622
2623 card->scd2vc[vc->scd_index] = NULL;
2624 free_scq(card, vc->scq);
2625 }
2626
2627 MOD_DEC_USE_COUNT;
2628 up(&card->mutex);
2629 }
2630
2631 static int
2632 idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
2633 {
2634 struct atm_dev *dev = vcc->dev;
2635 struct idt77252_dev *card = dev->dev_data;
2636 struct vc_map *vc = vcc->dev_data;
2637 int error = 0;
2638
2639 down(&card->mutex);
2640
2641 if (qos->txtp.traffic_class != ATM_NONE) {
2642 if (!test_bit(VCF_TX, &vc->flags)) {
2643 error = idt77252_init_tx(card, vc, vcc, qos);
2644 if (error)
2645 goto out;
2646 } else {
2647 switch (qos->txtp.traffic_class) {
2648 case ATM_CBR:
2649 error = idt77252_init_cbr(card, vc, vcc, qos);
2650 if (error)
2651 goto out;
2652 break;
2653
2654 case ATM_UBR:
2655 error = idt77252_init_ubr(card, vc, vcc, qos);
2656 if (error)
2657 goto out;
2658
2659 if (!test_bit(VCF_IDLE, &vc->flags)) {
2660 writel(TCMDQ_LACR | (vc->lacr << 16) |
2661 vc->index, SAR_REG_TCMDQ);
2662 }
2663 break;
2664
2665 case ATM_VBR:
2666 case ATM_ABR:
2667 error = -EOPNOTSUPP;
2668 goto out;
2669 }
2670 }
2671 }
2672
2673 if ((qos->rxtp.traffic_class != ATM_NONE) &&
2674 !test_bit(VCF_RX, &vc->flags)) {
2675 error = idt77252_init_rx(card, vc, vcc, qos);
2676 if (error)
2677 goto out;
2678 }
2679
2680 memcpy(&vcc->qos, qos, sizeof(struct atm_qos));
2681
2682 set_bit(ATM_VF_HASQOS, &vcc->flags);
2683
2684 out:
2685 up(&card->mutex);
2686 return error;
2687 }
2688
2689 static int
2690 idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2691 {
2692 struct idt77252_dev *card = dev->dev_data;
2693 int i, left;
2694
2695 left = (int) *pos;
2696 if (!left--)
2697 return sprintf(page, "IDT77252 Interrupts:\n");
2698 if (!left--)
2699 return sprintf(page, "TSIF: %lu\n", card->irqstat[15]);
2700 if (!left--)
2701 return sprintf(page, "TXICP: %lu\n", card->irqstat[14]);
2702 if (!left--)
2703 return sprintf(page, "TSQF: %lu\n", card->irqstat[12]);
2704 if (!left--)
2705 return sprintf(page, "TMROF: %lu\n", card->irqstat[11]);
2706 if (!left--)
2707 return sprintf(page, "PHYI: %lu\n", card->irqstat[10]);
2708 if (!left--)
2709 return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]);
2710 if (!left--)
2711 return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]);
2712 if (!left--)
2713 return sprintf(page, "RSQF: %lu\n", card->irqstat[6]);
2714 if (!left--)
2715 return sprintf(page, "EPDU: %lu\n", card->irqstat[5]);
2716 if (!left--)
2717 return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]);
2718 if (!left--)
2719 return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]);
2720 if (!left--)
2721 return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]);
2722 if (!left--)
2723 return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]);
2724 if (!left--)
2725 return sprintf(page, "IDT77252 Transmit Connection Table:\n");
2726
2727 for (i = 0; i < card->tct_size; i++) {
2728 unsigned long tct;
2729 struct atm_vcc *vcc;
2730 struct vc_map *vc;
2731 char *p;
2732
2733 vc = card->vcs[i];
2734 if (!vc)
2735 continue;
2736
2737 vcc = NULL;
2738 if (vc->tx_vcc)
2739 vcc = vc->tx_vcc;
2740 if (!vcc)
2741 continue;
2742 if (left--)
2743 continue;
2744
2745 p = page;
2746 p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci);
2747 tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE);
2748
2749 for (i = 0; i < 8; i++)
2750 p += sprintf(p, " %08x", read_sram(card, tct + i));
2751 p += sprintf(p, "\n");
2752 return p - page;
2753 }
2754 return 0;
2755 }
2756
2757 /*****************************************************************************/
2758 /* */
2759 /* Interrupt handler */
2760 /* */
2761 /*****************************************************************************/
2762
2763 static void
2764 idt77252_collect_stat(struct idt77252_dev *card)
2765 {
2766 u32 cdc, vpec, icc;
2767
2768 cdc = readl(SAR_REG_CDC);
2769 vpec = readl(SAR_REG_VPEC);
2770 icc = readl(SAR_REG_ICC);
2771
2772 #ifdef NOTDEF
2773 printk("%s:", card->name);
2774
2775 if (cdc & 0x7f0000) {
2776 char *s = "";
2777
2778 printk(" [");
2779 if (cdc & (1 << 22)) {
2780 printk("%sRM ID", s);
2781 s = " | ";
2782 }
2783 if (cdc & (1 << 21)) {
2784 printk("%sCON TAB", s);
2785 s = " | ";
2786 }
2787 if (cdc & (1 << 20)) {
2788 printk("%sNO FB", s);
2789 s = " | ";
2790 }
2791 if (cdc & (1 << 19)) {
2792 printk("%sOAM CRC", s);
2793 s = " | ";
2794 }
2795 if (cdc & (1 << 18)) {
2796 printk("%sRM CRC", s);
2797 s = " | ";
2798 }
2799 if (cdc & (1 << 17)) {
2800 printk("%sRM FIFO", s);
2801 s = " | ";
2802 }
2803 if (cdc & (1 << 16)) {
2804 printk("%sRX FIFO", s);
2805 s = " | ";
2806 }
2807 printk("]");
2808 }
2809
2810 printk(" CDC %04x, VPEC %04x, ICC: %04x\n",
2811 cdc & 0xffff, vpec & 0xffff, icc & 0xffff);
2812 #endif
2813 }
2814
2815 static void
2816 idt77252_interrupt(int irq, void *dev_id, struct pt_regs *ptregs)
2817 {
2818 struct idt77252_dev *card = dev_id;
2819 u32 stat;
2820
2821 stat = readl(SAR_REG_STAT) & 0xffff;
2822 if (!stat) /* no interrupt for us */
2823 return;
2824
2825 if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) {
2826 printk("%s: Re-entering irq_handler()\n", card->name);
2827 goto out;
2828 }
2829
2830 writel(stat, SAR_REG_STAT); /* reset interrupt */
2831
2832 if (stat & SAR_STAT_TSIF) { /* entry written to TSQ */
2833 INTPRINTK("%s: TSIF\n", card->name);
2834 card->irqstat[15]++;
2835 idt77252_tx(card);
2836 }
2837 if (stat & SAR_STAT_TXICP) { /* Incomplete CS-PDU has */
2838 INTPRINTK("%s: TXICP\n", card->name);
2839 card->irqstat[14]++;
2840 #ifdef CONFIG_ATM_IDT77252_DEBUG
2841 idt77252_tx_dump(card);
2842 #endif
2843 }
2844 if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full */
2845 INTPRINTK("%s: TSQF\n", card->name);
2846 card->irqstat[12]++;
2847 idt77252_tx(card);
2848 }
2849 if (stat & SAR_STAT_TMROF) { /* Timer overflow */
2850 INTPRINTK("%s: TMROF\n", card->name);
2851 card->irqstat[11]++;
2852 idt77252_collect_stat(card);
2853 }
2854
2855 if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU */
2856 INTPRINTK("%s: EPDU\n", card->name);
2857 card->irqstat[5]++;
2858 idt77252_rx(card);
2859 }
2860 if (stat & SAR_STAT_RSQAF) { /* RSQ is 7/8 full */
2861 INTPRINTK("%s: RSQAF\n", card->name);
2862 card->irqstat[1]++;
2863 idt77252_rx(card);
2864 }
2865 if (stat & SAR_STAT_RSQF) { /* RSQ is full */
2866 INTPRINTK("%s: RSQF\n", card->name);
2867 card->irqstat[6]++;
2868 idt77252_rx(card);
2869 }
2870 if (stat & SAR_STAT_RAWCF) { /* Raw cell received */
2871 INTPRINTK("%s: RAWCF\n", card->name);
2872 card->irqstat[4]++;
2873 idt77252_rx_raw(card);
2874 }
2875
2876 if (stat & SAR_STAT_PHYI) { /* PHY device interrupt */
2877 INTPRINTK("%s: PHYI", card->name);
2878 card->irqstat[10]++;
2879 if (card->atmdev->phy && card->atmdev->phy->interrupt)
2880 card->atmdev->phy->interrupt(card->atmdev);
2881 }
2882
2883 if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A |
2884 SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) {
2885
2886 writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG);
2887
2888 INTPRINTK("%s: FBQA: %04x\n", card->name, stat);
2889
2890 if (stat & SAR_STAT_FBQ0A)
2891 card->irqstat[2]++;
2892 if (stat & SAR_STAT_FBQ1A)
2893 card->irqstat[3]++;
2894 if (stat & SAR_STAT_FBQ2A)
2895 card->irqstat[7]++;
2896 if (stat & SAR_STAT_FBQ3A)
2897 card->irqstat[8]++;
2898
2899 schedule_work(&card->tqueue);
2900 }
2901
2902 out:
2903 clear_bit(IDT77252_BIT_INTERRUPT, &card->flags);
2904 }
2905
2906 static void
2907 idt77252_softint(void *dev_id)
2908 {
2909 struct idt77252_dev *card = dev_id;
2910 u32 stat;
2911 int done;
2912
2913 for (done = 1; ; done = 1) {
2914 stat = readl(SAR_REG_STAT) >> 16;
2915
2916 if ((stat & 0x0f) < SAR_FBQ0_HIGH) {
2917 add_rx_skb(card, 0, SAR_FB_SIZE_0, 32);
2918 done = 0;
2919 }
2920
2921 stat >>= 4;
2922 if ((stat & 0x0f) < SAR_FBQ1_HIGH) {
2923 add_rx_skb(card, 1, SAR_FB_SIZE_1, 32);
2924 done = 0;
2925 }
2926
2927 stat >>= 4;
2928 if ((stat & 0x0f) < SAR_FBQ2_HIGH) {
2929 add_rx_skb(card, 2, SAR_FB_SIZE_2, 32);
2930 done = 0;
2931 }
2932
2933 stat >>= 4;
2934 if ((stat & 0x0f) < SAR_FBQ3_HIGH) {
2935 add_rx_skb(card, 3, SAR_FB_SIZE_3, 32);
2936 done = 0;
2937 }
2938
2939 if (done)
2940 break;
2941 }
2942
2943 writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG);
2944 }
2945
2946
2947 static int
2948 open_card_oam(struct idt77252_dev *card)
2949 {
2950 unsigned long flags;
2951 unsigned long addr;
2952 struct vc_map *vc;
2953 int vpi, vci;
2954 int index;
2955 u32 rcte;
2956
2957 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2958 for (vci = 3; vci < 5; vci++) {
2959 index = VPCI2VC(card, vpi, vci);
2960
2961 vc = kmalloc(sizeof(struct vc_map), GFP_KERNEL);
2962 if (!vc) {
2963 printk("%s: can't alloc vc\n", card->name);
2964 return -ENOMEM;
2965 }
2966 memset(vc, 0, sizeof(struct vc_map));
2967
2968 vc->index = index;
2969 card->vcs[index] = vc;
2970
2971 flush_rx_pool(card, &vc->rcv.rx_pool);
2972
2973 rcte = SAR_RCTE_CONNECTOPEN |
2974 SAR_RCTE_RAWCELLINTEN |
2975 SAR_RCTE_RCQ |
2976 SAR_RCTE_FBP_1;
2977
2978 addr = card->rct_base + (vc->index << 2);
2979 write_sram(card, addr, rcte);
2980
2981 spin_lock_irqsave(&card->cmd_lock, flags);
2982 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2),
2983 SAR_REG_CMD);
2984 waitfor_idle(card);
2985 spin_unlock_irqrestore(&card->cmd_lock, flags);
2986 }
2987 }
2988
2989 return 0;
2990 }
2991
2992 static void
2993 close_card_oam(struct idt77252_dev *card)
2994 {
2995 unsigned long flags;
2996 unsigned long addr;
2997 struct vc_map *vc;
2998 int vpi, vci;
2999 int index;
3000
3001 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
3002 for (vci = 3; vci < 5; vci++) {
3003 index = VPCI2VC(card, vpi, vci);
3004 vc = card->vcs[index];
3005
3006 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
3007
3008 spin_lock_irqsave(&card->cmd_lock, flags);
3009 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2),
3010 SAR_REG_CMD);
3011 waitfor_idle(card);
3012 spin_unlock_irqrestore(&card->cmd_lock, flags);
3013
3014 if (vc->rcv.rx_pool.count) {
3015 DPRINTK("%s: closing a VC "
3016 "with pending rx buffers.\n",
3017 card->name);
3018
3019 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
3020 }
3021 }
3022 }
3023 }
3024
3025 static int
3026 open_card_ubr0(struct idt77252_dev *card)
3027 {
3028 struct vc_map *vc;
3029
3030 vc = kmalloc(sizeof(struct vc_map), GFP_KERNEL);
3031 if (!vc) {
3032 printk("%s: can't alloc vc\n", card->name);
3033 return -ENOMEM;
3034 }
3035 memset(vc, 0, sizeof(struct vc_map));
3036 card->vcs[0] = vc;
3037 vc->class = SCHED_UBR0;
3038
3039 vc->scq = alloc_scq(card, vc->class);
3040 if (!vc->scq) {
3041 printk("%s: can't get SCQ.\n", card->name);
3042 return -ENOMEM;
3043 }
3044
3045 card->scd2vc[0] = vc;
3046 vc->scd_index = 0;
3047 vc->scq->scd = card->scd_base;
3048
3049 fill_scd(card, vc->scq, vc->class);
3050
3051 write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base);
3052 write_sram(card, card->tct_base + 1, 0);
3053 write_sram(card, card->tct_base + 2, 0);
3054 write_sram(card, card->tct_base + 3, 0);
3055 write_sram(card, card->tct_base + 4, 0);
3056 write_sram(card, card->tct_base + 5, 0);
3057 write_sram(card, card->tct_base + 6, 0);
3058 write_sram(card, card->tct_base + 7, TCT_FLAG_UBR);
3059
3060 clear_bit(VCF_IDLE, &vc->flags);
3061 writel(TCMDQ_START | 0, SAR_REG_TCMDQ);
3062 return 0;
3063 }
3064
3065 static int
3066 idt77252_dev_open(struct idt77252_dev *card)
3067 {
3068 u32 conf;
3069
3070 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3071 printk("%s: SAR not yet initialized.\n", card->name);
3072 return -1;
3073 }
3074
3075 conf = SAR_CFG_RXPTH| /* enable receive path */
3076 SAR_RX_DELAY | /* interrupt on complete PDU */
3077 SAR_CFG_RAWIE | /* interrupt enable on raw cells */
3078 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
3079 SAR_CFG_TMOIE | /* interrupt on timer overflow */
3080 SAR_CFG_FBIE | /* interrupt on low free buffers */
3081 SAR_CFG_TXEN | /* transmit operation enable */
3082 SAR_CFG_TXINT | /* interrupt on transmit status */
3083 SAR_CFG_TXUIE | /* interrupt on transmit underrun */
3084 SAR_CFG_TXSFI | /* interrupt on TSQ almost full */
3085 SAR_CFG_PHYIE /* enable PHY interrupts */
3086 ;
3087
3088 #ifdef CONFIG_ATM_IDT77252_RCV_ALL
3089 /* Test RAW cell receive. */
3090 conf |= SAR_CFG_VPECA;
3091 #endif
3092
3093 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3094
3095 if (open_card_oam(card)) {
3096 printk("%s: Error initializing OAM.\n", card->name);
3097 return -1;
3098 }
3099
3100 if (open_card_ubr0(card)) {
3101 printk("%s: Error initializing UBR0.\n", card->name);
3102 return -1;
3103 }
3104
3105 IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name);
3106 return 0;
3107 }
3108
3109 void
3110 idt77252_dev_close(struct atm_dev *dev)
3111 {
3112 struct idt77252_dev *card = dev->dev_data;
3113 u32 conf;
3114
3115 close_card_oam(card);
3116
3117 conf = SAR_CFG_RXPTH | /* enable receive path */
3118 SAR_RX_DELAY | /* interrupt on complete PDU */
3119 SAR_CFG_RAWIE | /* interrupt enable on raw cells */
3120 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
3121 SAR_CFG_TMOIE | /* interrupt on timer overflow */
3122 SAR_CFG_FBIE | /* interrupt on low free buffers */
3123 SAR_CFG_TXEN | /* transmit operation enable */
3124 SAR_CFG_TXINT | /* interrupt on transmit status */
3125 SAR_CFG_TXUIE | /* interrupt on xmit underrun */
3126 SAR_CFG_TXSFI /* interrupt on TSQ almost full */
3127 ;
3128
3129 writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG);
3130
3131 DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name);
3132 }
3133
3134
3135 /*****************************************************************************/
3136 /* */
3137 /* Initialisation and Deinitialization of IDT77252 */
3138 /* */
3139 /*****************************************************************************/
3140
3141
3142 static void
3143 deinit_card(struct idt77252_dev *card)
3144 {
3145 struct sk_buff *skb;
3146 int i, j;
3147
3148 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3149 printk("%s: SAR not yet initialized.\n", card->name);
3150 return;
3151 }
3152 DIPRINTK("idt77252: deinitialize card %u\n", card->index);
3153
3154 writel(0, SAR_REG_CFG);
3155
3156 if (card->atmdev)
3157 atm_dev_deregister(card->atmdev);
3158
3159 for (i = 0; i < 4; i++) {
3160 for (j = 0; j < FBQ_SIZE; j++) {
3161 skb = card->sbpool[i].skb[j];
3162 if (skb) {
3163 pci_unmap_single(card->pcidev,
3164 IDT77252_PRV_PADDR(skb),
3165 skb->end - skb->data,
3166 PCI_DMA_FROMDEVICE);
3167 card->sbpool[i].skb[j] = NULL;
3168 dev_kfree_skb(skb);
3169 }
3170 }
3171 }
3172
3173 if (card->soft_tst)
3174 vfree(card->soft_tst);
3175
3176 if (card->scd2vc)
3177 vfree(card->scd2vc);
3178
3179 if (card->vcs)
3180 vfree(card->vcs);
3181
3182 if (card->raw_cell_hnd) {
3183 pci_free_consistent(card->pcidev, 2 * sizeof(u32),
3184 card->raw_cell_hnd, card->raw_cell_paddr);
3185 }
3186
3187 if (card->rsq.base) {
3188 DIPRINTK("%s: Release RSQ ...\n", card->name);
3189 deinit_rsq(card);
3190 }
3191
3192 if (card->tsq.base) {
3193 DIPRINTK("%s: Release TSQ ...\n", card->name);
3194 deinit_tsq(card);
3195 }
3196
3197 DIPRINTK("idt77252: Release IRQ.\n");
3198 free_irq(card->pcidev->irq, card);
3199
3200 for (i = 0; i < 4; i++) {
3201 if (card->fbq[i])
3202 iounmap((void *) card->fbq[i]);
3203 }
3204
3205 if (card->membase)
3206 iounmap((void *) card->membase);
3207
3208 clear_bit(IDT77252_BIT_INIT, &card->flags);
3209 DIPRINTK("%s: Card deinitialized.\n", card->name);
3210 }
3211
3212
3213 static int __devinit
3214 init_sram(struct idt77252_dev *card)
3215 {
3216 int i;
3217
3218 for (i = 0; i < card->sramsize; i += 4)
3219 write_sram(card, (i >> 2), 0);
3220
3221 /* set SRAM layout for THIS card */
3222 if (card->sramsize == (512 * 1024)) {
3223 card->tct_base = SAR_SRAM_TCT_128_BASE;
3224 card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1)
3225 / SAR_SRAM_TCT_SIZE;
3226 card->rct_base = SAR_SRAM_RCT_128_BASE;
3227 card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1)
3228 / SAR_SRAM_RCT_SIZE;
3229 card->rt_base = SAR_SRAM_RT_128_BASE;
3230 card->scd_base = SAR_SRAM_SCD_128_BASE;
3231 card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1)
3232 / SAR_SRAM_SCD_SIZE;
3233 card->tst[0] = SAR_SRAM_TST1_128_BASE;
3234 card->tst[1] = SAR_SRAM_TST2_128_BASE;
3235 card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1;
3236 card->abrst_base = SAR_SRAM_ABRSTD_128_BASE;
3237 card->abrst_size = SAR_ABRSTD_SIZE_8K;
3238 card->fifo_base = SAR_SRAM_FIFO_128_BASE;
3239 card->fifo_size = SAR_RXFD_SIZE_32K;
3240 } else {
3241 card->tct_base = SAR_SRAM_TCT_32_BASE;
3242 card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1)
3243 / SAR_SRAM_TCT_SIZE;
3244 card->rct_base = SAR_SRAM_RCT_32_BASE;
3245 card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1)
3246 / SAR_SRAM_RCT_SIZE;
3247 card->rt_base = SAR_SRAM_RT_32_BASE;
3248 card->scd_base = SAR_SRAM_SCD_32_BASE;
3249 card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1)
3250 / SAR_SRAM_SCD_SIZE;
3251 card->tst[0] = SAR_SRAM_TST1_32_BASE;
3252 card->tst[1] = SAR_SRAM_TST2_32_BASE;
3253 card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1);
3254 card->abrst_base = SAR_SRAM_ABRSTD_32_BASE;
3255 card->abrst_size = SAR_ABRSTD_SIZE_1K;
3256 card->fifo_base = SAR_SRAM_FIFO_32_BASE;
3257 card->fifo_size = SAR_RXFD_SIZE_4K;
3258 }
3259
3260 /* Initialize TCT */
3261 for (i = 0; i < card->tct_size; i++) {
3262 write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0);
3263 write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0);
3264 write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0);
3265 write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0);
3266 write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0);
3267 write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0);
3268 write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0);
3269 write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0);
3270 }
3271
3272 /* Initialize RCT */
3273 for (i = 0; i < card->rct_size; i++) {
3274 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE,
3275 (u32) SAR_RCTE_RAWCELLINTEN);
3276 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1,
3277 (u32) 0);
3278 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2,
3279 (u32) 0);
3280 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3,
3281 (u32) 0xffffffff);
3282 }
3283
3284 writel((SAR_FBQ0_LOW << 28) | 0x00000000 | 0x00000000 |
3285 (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0);
3286 writel((SAR_FBQ1_LOW << 28) | 0x00000000 | 0x00000000 |
3287 (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1);
3288 writel((SAR_FBQ2_LOW << 28) | 0x00000000 | 0x00000000 |
3289 (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2);
3290 writel((SAR_FBQ3_LOW << 28) | 0x00000000 | 0x00000000 |
3291 (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3);
3292
3293 /* Initialize rate table */
3294 for (i = 0; i < 256; i++) {
3295 write_sram(card, card->rt_base + i, log_to_rate[i]);
3296 }
3297
3298 for (i = 0; i < 128; i++) {
3299 unsigned int tmp;
3300
3301 tmp = rate_to_log[(i << 2) + 0] << 0;
3302 tmp |= rate_to_log[(i << 2) + 1] << 8;
3303 tmp |= rate_to_log[(i << 2) + 2] << 16;
3304 tmp |= rate_to_log[(i << 2) + 3] << 24;
3305 write_sram(card, card->rt_base + 256 + i, tmp);
3306 }
3307
3308 #if 0 /* Fill RDF and AIR tables. */
3309 for (i = 0; i < 128; i++) {
3310 unsigned int tmp;
3311
3312 tmp = RDF[0][(i << 1) + 0] << 16;
3313 tmp |= RDF[0][(i << 1) + 1] << 0;
3314 write_sram(card, card->rt_base + 512 + i, tmp);
3315 }
3316
3317 for (i = 0; i < 128; i++) {
3318 unsigned int tmp;
3319
3320 tmp = AIR[0][(i << 1) + 0] << 16;
3321 tmp |= AIR[0][(i << 1) + 1] << 0;
3322 write_sram(card, card->rt_base + 640 + i, tmp);
3323 }
3324 #endif
3325
3326 IPRINTK("%s: initialize rate table ...\n", card->name);
3327 writel(card->rt_base << 2, SAR_REG_RTBL);
3328
3329 /* Initialize TSTs */
3330 IPRINTK("%s: initialize TST ...\n", card->name);
3331 card->tst_free = card->tst_size - 2; /* last two are jumps */
3332
3333 for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++)
3334 write_sram(card, i, TSTE_OPC_VAR);
3335 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3336 idt77252_sram_write_errors = 1;
3337 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3338 idt77252_sram_write_errors = 0;
3339 for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++)
3340 write_sram(card, i, TSTE_OPC_VAR);
3341 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3342 idt77252_sram_write_errors = 1;
3343 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3344 idt77252_sram_write_errors = 0;
3345
3346 card->tst_index = 0;
3347 writel(card->tst[0] << 2, SAR_REG_TSTB);
3348
3349 /* Initialize ABRSTD and Receive FIFO */
3350 IPRINTK("%s: initialize ABRSTD ...\n", card->name);
3351 writel(card->abrst_size | (card->abrst_base << 2),
3352 SAR_REG_ABRSTD);
3353
3354 IPRINTK("%s: initialize receive fifo ...\n", card->name);
3355 writel(card->fifo_size | (card->fifo_base << 2),
3356 SAR_REG_RXFD);
3357
3358 IPRINTK("%s: SRAM initialization complete.\n", card->name);
3359 return 0;
3360 }
3361
3362 static int __devinit
3363 init_card(struct atm_dev *dev)
3364 {
3365 struct idt77252_dev *card = dev->dev_data;
3366 struct pci_dev *pcidev = card->pcidev;
3367 unsigned long tmpl, modl;
3368 unsigned int linkrate, rsvdcr;
3369 unsigned int tst_entries;
3370 struct net_device *tmp;
3371 char tname[10];
3372
3373 u32 size;
3374 u_char pci_byte;
3375 u32 conf;
3376 int i, k;
3377
3378 if (test_bit(IDT77252_BIT_INIT, &card->flags)) {
3379 printk("Error: SAR already initialized.\n");
3380 return -1;
3381 }
3382
3383 /*****************************************************************/
3384 /* P C I C O N F I G U R A T I O N */
3385 /*****************************************************************/
3386
3387 /* Set PCI Retry-Timeout and TRDY timeout */
3388 IPRINTK("%s: Checking PCI retries.\n", card->name);
3389 if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) {
3390 printk("%s: can't read PCI retry timeout.\n", card->name);
3391 deinit_card(card);
3392 return -1;
3393 }
3394 if (pci_byte != 0) {
3395 IPRINTK("%s: PCI retry timeout: %d, set to 0.\n",
3396 card->name, pci_byte);
3397 if (pci_write_config_byte(pcidev, 0x40, 0) != 0) {
3398 printk("%s: can't set PCI retry timeout.\n",
3399 card->name);
3400 deinit_card(card);
3401 return -1;
3402 }
3403 }
3404 IPRINTK("%s: Checking PCI TRDY.\n", card->name);
3405 if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) {
3406 printk("%s: can't read PCI TRDY timeout.\n", card->name);
3407 deinit_card(card);
3408 return -1;
3409 }
3410 if (pci_byte != 0) {
3411 IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n",
3412 card->name, pci_byte);
3413 if (pci_write_config_byte(pcidev, 0x41, 0) != 0) {
3414 printk("%s: can't set PCI TRDY timeout.\n", card->name);
3415 deinit_card(card);
3416 return -1;
3417 }
3418 }
3419 /* Reset Timer register */
3420 if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) {
3421 printk("%s: resetting timer overflow.\n", card->name);
3422 writel(SAR_STAT_TMROF, SAR_REG_STAT);
3423 }
3424 IPRINTK("%s: Request IRQ ... ", card->name);
3425 if (request_irq(pcidev->irq, idt77252_interrupt, SA_INTERRUPT|SA_SHIRQ,
3426 card->name, card) != 0) {
3427 printk("%s: can't allocate IRQ.\n", card->name);
3428 deinit_card(card);
3429 return -1;
3430 }
3431 IPRINTK("got %d.\n", pcidev->irq);
3432
3433 /*****************************************************************/
3434 /* C H E C K A N D I N I T S R A M */
3435 /*****************************************************************/
3436
3437 IPRINTK("%s: Initializing SRAM\n", card->name);
3438
3439 /* preset size of connecton table, so that init_sram() knows about it */
3440 conf = SAR_CFG_TX_FIFO_SIZE_9 | /* Use maximum fifo size */
3441 SAR_CFG_RXSTQ_SIZE_8k | /* Receive Status Queue is 8k */
3442 SAR_CFG_IDLE_CLP | /* Set CLP on idle cells */
3443 #ifndef CONFIG_ATM_IDT77252_SEND_IDLE
3444 SAR_CFG_NO_IDLE | /* Do not send idle cells */
3445 #endif
3446 0;
3447
3448 if (card->sramsize == (512 * 1024))
3449 conf |= SAR_CFG_CNTBL_1k;
3450 else
3451 conf |= SAR_CFG_CNTBL_512;
3452
3453 switch (vpibits) {
3454 case 0:
3455 conf |= SAR_CFG_VPVCS_0;
3456 break;
3457 default:
3458 case 1:
3459 conf |= SAR_CFG_VPVCS_1;
3460 break;
3461 case 2:
3462 conf |= SAR_CFG_VPVCS_2;
3463 break;
3464 case 8:
3465 conf |= SAR_CFG_VPVCS_8;
3466 break;
3467 }
3468
3469 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3470
3471 if (init_sram(card) < 0)
3472 return -1;
3473
3474 /********************************************************************/
3475 /* A L L O C R A M A N D S E T V A R I O U S T H I N G S */
3476 /********************************************************************/
3477 /* Initialize TSQ */
3478 if (0 != init_tsq(card)) {
3479 deinit_card(card);
3480 return -1;
3481 }
3482 /* Initialize RSQ */
3483 if (0 != init_rsq(card)) {
3484 deinit_card(card);
3485 return -1;
3486 }
3487
3488 card->vpibits = vpibits;
3489 if (card->sramsize == (512 * 1024)) {
3490 card->vcibits = 10 - card->vpibits;
3491 } else {
3492 card->vcibits = 9 - card->vpibits;
3493 }
3494
3495 card->vcimask = 0;
3496 for (k = 0, i = 1; k < card->vcibits; k++) {
3497 card->vcimask |= i;
3498 i <<= 1;
3499 }
3500
3501 IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name);
3502 writel(0, SAR_REG_VPM);
3503
3504 /* Little Endian Order */
3505 writel(0, SAR_REG_GP);
3506
3507 /* Initialize RAW Cell Handle Register */
3508 card->raw_cell_hnd = pci_alloc_consistent(card->pcidev, 2 * sizeof(u32),
3509 &card->raw_cell_paddr);
3510 if (!card->raw_cell_hnd) {
3511 printk("%s: memory allocation failure.\n", card->name);
3512 deinit_card(card);
3513 return -1;
3514 }
3515 memset(card->raw_cell_hnd, 0, 2 * sizeof(u32));
3516 writel(card->raw_cell_paddr, SAR_REG_RAWHND);
3517 IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name,
3518 card->raw_cell_hnd);
3519
3520 size = sizeof(struct vc_map *) * card->tct_size;
3521 IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size);
3522 if (NULL == (card->vcs = vmalloc(size))) {
3523 printk("%s: memory allocation failure.\n", card->name);
3524 deinit_card(card);
3525 return -1;
3526 }
3527 memset(card->vcs, 0, size);
3528
3529 size = sizeof(struct vc_map *) * card->scd_size;
3530 IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n",
3531 card->name, size);
3532 if (NULL == (card->scd2vc = vmalloc(size))) {
3533 printk("%s: memory allocation failure.\n", card->name);
3534 deinit_card(card);
3535 return -1;
3536 }
3537 memset(card->scd2vc, 0, size);
3538
3539 size = sizeof(struct tst_info) * (card->tst_size - 2);
3540 IPRINTK("%s: allocate %d byte for TST to VC mapping.\n",
3541 card->name, size);
3542 if (NULL == (card->soft_tst = vmalloc(size))) {
3543 printk("%s: memory allocation failure.\n", card->name);
3544 deinit_card(card);
3545 return -1;
3546 }
3547 for (i = 0; i < card->tst_size - 2; i++) {
3548 card->soft_tst[i].tste = TSTE_OPC_VAR;
3549 card->soft_tst[i].vc = NULL;
3550 }
3551
3552 if (dev->phy == NULL) {
3553 printk("%s: No LT device defined.\n", card->name);
3554 deinit_card(card);
3555 return -1;
3556 }
3557 if (dev->phy->ioctl == NULL) {
3558 printk("%s: LT had no IOCTL funtion defined.\n", card->name);
3559 deinit_card(card);
3560 return -1;
3561 }
3562
3563 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
3564 /*
3565 * this is a jhs hack to get around special functionality in the
3566 * phy driver for the atecom hardware; the functionality doesn't
3567 * exist in the linux atm suni driver
3568 *
3569 * it isn't the right way to do things, but as the guy from NIST
3570 * said, talking about their measurement of the fine structure
3571 * constant, "it's good enough for government work."
3572 */
3573 linkrate = 149760000;
3574 #endif
3575
3576 card->link_pcr = (linkrate / 8 / 53);
3577 printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n",
3578 card->name, linkrate, card->link_pcr);
3579
3580 #ifdef CONFIG_ATM_IDT77252_SEND_IDLE
3581 card->utopia_pcr = card->link_pcr;
3582 #else
3583 card->utopia_pcr = (160000000 / 8 / 54);
3584 #endif
3585
3586 rsvdcr = 0;
3587 if (card->utopia_pcr > card->link_pcr)
3588 rsvdcr = card->utopia_pcr - card->link_pcr;
3589
3590 tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2);
3591 modl = tmpl % (unsigned long)card->utopia_pcr;
3592 tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr);
3593 if (modl)
3594 tst_entries++;
3595 card->tst_free -= tst_entries;
3596 fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL);
3597
3598 #ifdef HAVE_EEPROM
3599 idt77252_eeprom_init(card);
3600 printk("%s: EEPROM: %02x:", card->name,
3601 idt77252_eeprom_read_status(card));
3602
3603 for (i = 0; i < 0x80; i++) {
3604 printk(" %02x",
3605 idt77252_eeprom_read_byte(card, i)
3606 );
3607 }
3608 printk("\n");
3609 #endif /* HAVE_EEPROM */
3610
3611 /*
3612 * XXX: <hack>
3613 */
3614 sprintf(tname, "eth%d", card->index);
3615 tmp = dev_get_by_name(tname); /* jhs: was "tmp = dev_get(tname);" */
3616 if (tmp) {
3617 memcpy(card->atmdev->esi, tmp->dev_addr, 6);
3618
3619 printk("%s: ESI %02x:%02x:%02x:%02x:%02x:%02x\n",
3620 card->name, card->atmdev->esi[0], card->atmdev->esi[1],
3621 card->atmdev->esi[2], card->atmdev->esi[3],
3622 card->atmdev->esi[4], card->atmdev->esi[5]);
3623 }
3624 /*
3625 * XXX: </hack>
3626 */
3627
3628 /* Set Maximum Deficit Count for now. */
3629 writel(0xffff, SAR_REG_MDFCT);
3630
3631 set_bit(IDT77252_BIT_INIT, &card->flags);
3632
3633 XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name);
3634 return 0;
3635 }
3636
3637
3638 /*****************************************************************************/
3639 /* */
3640 /* Probing of IDT77252 ABR SAR */
3641 /* */
3642 /*****************************************************************************/
3643
3644
3645 static int __devinit
3646 idt77252_preset(struct idt77252_dev *card)
3647 {
3648 u16 pci_command;
3649
3650 /*****************************************************************/
3651 /* P C I C O N F I G U R A T I O N */
3652 /*****************************************************************/
3653
3654 XPRINTK("%s: Enable PCI master and memory access for SAR.\n",
3655 card->name);
3656 if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) {
3657 printk("%s: can't read PCI_COMMAND.\n", card->name);
3658 deinit_card(card);
3659 return -1;
3660 }
3661 if (!(pci_command & PCI_COMMAND_IO)) {
3662 printk("%s: PCI_COMMAND: %04x (???)\n",
3663 card->name, pci_command);
3664 deinit_card(card);
3665 return (-1);
3666 }
3667 pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
3668 if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) {
3669 printk("%s: can't write PCI_COMMAND.\n", card->name);
3670 deinit_card(card);
3671 return -1;
3672 }
3673 /*****************************************************************/
3674 /* G E N E R I C R E S E T */
3675 /*****************************************************************/
3676
3677 /* Software reset */
3678 writel(SAR_CFG_SWRST, SAR_REG_CFG);
3679 mdelay(1);
3680 writel(0, SAR_REG_CFG);
3681
3682 IPRINTK("%s: Software resetted.\n", card->name);
3683 return 0;
3684 }
3685
3686
3687 static unsigned long __devinit
3688 probe_sram(struct idt77252_dev *card)
3689 {
3690 u32 data, addr;
3691
3692 writel(0, SAR_REG_DR0);
3693 writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD);
3694
3695 for (addr = 0x4000; addr < 0x80000; addr += 0x4000) {
3696 writel(0xdeadbeef, SAR_REG_DR0);
3697 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
3698
3699 writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD);
3700 data = readl(SAR_REG_DR0);
3701
3702 if (data != 0)
3703 break;
3704 }
3705
3706 return addr * sizeof(u32);
3707 }
3708
3709 static int __devinit
3710 idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id)
3711 {
3712 static struct idt77252_dev **last = &idt77252_chain;
3713 static int index = 0;
3714
3715 unsigned long membase, srambase;
3716 struct idt77252_dev *card;
3717 struct atm_dev *dev;
3718 ushort revision = 0;
3719 int i;
3720
3721
3722 if (pci_read_config_word(pcidev, PCI_REVISION_ID, &revision)) {
3723 printk("idt77252-%d: can't read PCI_REVISION_ID\n", index);
3724 return -ENODEV;
3725 }
3726
3727 card = kmalloc(sizeof(struct idt77252_dev), GFP_KERNEL);
3728 if (!card) {
3729 printk("idt77252-%d: can't allocate private data\n", index);
3730 return -ENOMEM;
3731 }
3732 memset(card, 0, sizeof(struct idt77252_dev));
3733
3734 card->revision = revision;
3735 card->index = index;
3736 card->pcidev = pcidev;
3737 sprintf(card->name, "idt77252-%d", card->index);
3738
3739 INIT_WORK(&card->tqueue, idt77252_softint, (void *)card);
3740
3741 membase = pci_resource_start(pcidev, 1);
3742 srambase = pci_resource_start(pcidev, 2);
3743
3744 init_MUTEX(&card->mutex);
3745 spin_lock_init(&card->cmd_lock);
3746 spin_lock_init(&card->tst_lock);
3747
3748 init_timer(&card->tst_timer);
3749 card->tst_timer.data = (unsigned long)card;
3750 card->tst_timer.function = tst_timer;
3751
3752 /* Do the I/O remapping... */
3753 card->membase = (unsigned long) ioremap(membase, 1024);
3754 if (!card->membase) {
3755 printk("%s: can't ioremap() membase\n", card->name);
3756 kfree(card);
3757 return -EIO;
3758 }
3759
3760 if (idt77252_preset(card)) {
3761 printk("%s: preset failed\n", card->name);
3762 iounmap((void *) card->membase);
3763 kfree(card);
3764 return -EIO;
3765 }
3766
3767 dev = atm_dev_register("idt77252", &idt77252_ops, -1, 0);
3768 if (!dev) {
3769 printk("%s: can't register atm device\n", card->name);
3770 iounmap((void *) card->membase);
3771 kfree(card);
3772 return -EIO;
3773 }
3774 dev->dev_data = card;
3775 card->atmdev = dev;
3776
3777 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
3778 suni_init(dev);
3779 if (!dev->phy) {
3780 printk("%s: can't init SUNI\n", card->name);
3781 deinit_card(card);
3782 kfree(card);
3783 return -EIO;
3784 }
3785 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
3786
3787 card->sramsize = probe_sram(card);
3788
3789 for (i = 0; i < 4; i++) {
3790 card->fbq[i] = (unsigned long)
3791 ioremap(srambase | 0x200000 | (i << 18), 4);
3792 if (!card->fbq[i]) {
3793 printk("%s: can't ioremap() FBQ%d\n", card->name, i);
3794 deinit_card(card);
3795 kfree(card);
3796 return -EIO;
3797 }
3798 }
3799
3800 printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n",
3801 card->name, ((revision > 1) && (revision < 25)) ?
3802 'A' + revision - 1 : '?', membase, srambase,
3803 card->sramsize / 1024);
3804
3805 if (init_card(dev)) {
3806 printk("%s: init_card failed\n", card->name);
3807 deinit_card(card);
3808 kfree(card);
3809 return -EIO;
3810 }
3811
3812 dev->ci_range.vpi_bits = card->vpibits;
3813 dev->ci_range.vci_bits = card->vcibits;
3814 dev->link_rate = card->link_pcr;
3815
3816 if (dev->phy->start)
3817 dev->phy->start(dev);
3818
3819 if (idt77252_dev_open(card)) {
3820 printk("%s: dev_open failed\n", card->name);
3821
3822 if (dev->phy->stop)
3823 dev->phy->stop(dev);
3824 deinit_card(card);
3825 kfree(card);
3826 return -EIO;
3827 }
3828
3829 *last = card;
3830 last = &card->next;
3831 index++;
3832
3833 return 0;
3834 }
3835
3836 static struct pci_device_id idt77252_pci_tbl[] __devinitdata =
3837 {
3838 { PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_IDT_IDT77252,
3839 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
3840 { 0, }
3841 };
3842
3843 static struct pci_driver idt77252_driver = {
3844 .name = "idt77252",
3845 .id_table = idt77252_pci_tbl,
3846 .probe = idt77252_init_one,
3847 };
3848
3849 static int __init idt77252_init(void)
3850 {
3851 struct sk_buff *skb;
3852
3853 printk("%s: at %p\n", __FUNCTION__, idt77252_init);
3854
3855 if (sizeof(skb->cb) < sizeof(struct atm_skb_data) +
3856 sizeof(struct idt77252_skb_prv)) {
3857 printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n",
3858 __FUNCTION__, (unsigned long) sizeof(skb->cb),
3859 (unsigned long) sizeof(struct atm_skb_data) +
3860 sizeof(struct idt77252_skb_prv));
3861 return -EIO;
3862 }
3863
3864 if (pci_register_driver(&idt77252_driver) > 0)
3865 return 0;
3866
3867 pci_unregister_driver(&idt77252_driver);
3868 return -ENODEV;
3869 }
3870
3871 static void __exit idt77252_exit(void)
3872 {
3873 struct idt77252_dev *card;
3874 struct atm_dev *dev;
3875
3876 pci_unregister_driver(&idt77252_driver);
3877
3878 while (idt77252_chain) {
3879 card = idt77252_chain;
3880 dev = card->atmdev;
3881 idt77252_chain = card->next;
3882
3883 if (dev->phy->stop)
3884 dev->phy->stop(dev);
3885 deinit_card(card);
3886 kfree(card);
3887 }
3888
3889 DIPRINTK("idt77252: finished cleanup-module().\n");
3890 }
3891
3892 module_init(idt77252_init);
3893 module_exit(idt77252_exit);
3894
3895 MODULE_LICENSE("GPL");
3896
3897 MODULE_PARM(vpibits, "i");
3898 MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)");
3899 #ifdef CONFIG_ATM_IDT77252_DEBUG
3900 MODULE_PARM(debug, "i");
3901 MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h");
3902 #endif
3903
3904 MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>");
3905 MODULE_DESCRIPTION("IDT77252 ABR SAR Driver");
Mirror of the linux-mips.org kernel tree