[PATCH] i386: __devinit should be __cpuinit
[linux-2.6/linux-mips.git] / arch / i386 / kernel / cpu / common.c
blobf63dcfb16dad479f1d1a7d1745adc5efd4b14dd1
1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
4 #include <linux/smp.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/bootmem.h>
8 #include <asm/semaphore.h>
9 #include <asm/processor.h>
10 #include <asm/i387.h>
11 #include <asm/msr.h>
12 #include <asm/io.h>
13 #include <asm/mmu_context.h>
14 #ifdef CONFIG_X86_LOCAL_APIC
15 #include <asm/mpspec.h>
16 #include <asm/apic.h>
17 #include <mach_apic.h>
18 #endif
20 #include "cpu.h"
22 DEFINE_PER_CPU(struct Xgt_desc_struct, cpu_gdt_descr);
23 EXPORT_PER_CPU_SYMBOL(cpu_gdt_descr);
25 DEFINE_PER_CPU(unsigned char, cpu_16bit_stack[CPU_16BIT_STACK_SIZE]);
26 EXPORT_PER_CPU_SYMBOL(cpu_16bit_stack);
28 static int cachesize_override __cpuinitdata = -1;
29 static int disable_x86_fxsr __cpuinitdata = 0;
30 static int disable_x86_serial_nr __cpuinitdata = 1;
32 struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {};
34 extern int disable_pse;
36 static void default_init(struct cpuinfo_x86 * c)
38 /* Not much we can do here... */
39 /* Check if at least it has cpuid */
40 if (c->cpuid_level == -1) {
41 /* No cpuid. It must be an ancient CPU */
42 if (c->x86 == 4)
43 strcpy(c->x86_model_id, "486");
44 else if (c->x86 == 3)
45 strcpy(c->x86_model_id, "386");
49 static struct cpu_dev default_cpu = {
50 .c_init = default_init,
51 .c_vendor = "Unknown",
53 static struct cpu_dev * this_cpu = &default_cpu;
55 static int __init cachesize_setup(char *str)
57 get_option (&str, &cachesize_override);
58 return 1;
60 __setup("cachesize=", cachesize_setup);
62 int __cpuinit get_model_name(struct cpuinfo_x86 *c)
64 unsigned int *v;
65 char *p, *q;
67 if (cpuid_eax(0x80000000) < 0x80000004)
68 return 0;
70 v = (unsigned int *) c->x86_model_id;
71 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
72 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
73 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
74 c->x86_model_id[48] = 0;
76 /* Intel chips right-justify this string for some dumb reason;
77 undo that brain damage */
78 p = q = &c->x86_model_id[0];
79 while ( *p == ' ' )
80 p++;
81 if ( p != q ) {
82 while ( *p )
83 *q++ = *p++;
84 while ( q <= &c->x86_model_id[48] )
85 *q++ = '\0'; /* Zero-pad the rest */
88 return 1;
92 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
94 unsigned int n, dummy, ecx, edx, l2size;
96 n = cpuid_eax(0x80000000);
98 if (n >= 0x80000005) {
99 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
100 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
101 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
102 c->x86_cache_size=(ecx>>24)+(edx>>24);
105 if (n < 0x80000006) /* Some chips just has a large L1. */
106 return;
108 ecx = cpuid_ecx(0x80000006);
109 l2size = ecx >> 16;
111 /* do processor-specific cache resizing */
112 if (this_cpu->c_size_cache)
113 l2size = this_cpu->c_size_cache(c,l2size);
115 /* Allow user to override all this if necessary. */
116 if (cachesize_override != -1)
117 l2size = cachesize_override;
119 if ( l2size == 0 )
120 return; /* Again, no L2 cache is possible */
122 c->x86_cache_size = l2size;
124 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
125 l2size, ecx & 0xFF);
128 /* Naming convention should be: <Name> [(<Codename>)] */
129 /* This table only is used unless init_<vendor>() below doesn't set it; */
130 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
132 /* Look up CPU names by table lookup. */
133 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
135 struct cpu_model_info *info;
137 if ( c->x86_model >= 16 )
138 return NULL; /* Range check */
140 if (!this_cpu)
141 return NULL;
143 info = this_cpu->c_models;
145 while (info && info->family) {
146 if (info->family == c->x86)
147 return info->model_names[c->x86_model];
148 info++;
150 return NULL; /* Not found */
154 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early)
156 char *v = c->x86_vendor_id;
157 int i;
158 static int printed;
160 for (i = 0; i < X86_VENDOR_NUM; i++) {
161 if (cpu_devs[i]) {
162 if (!strcmp(v,cpu_devs[i]->c_ident[0]) ||
163 (cpu_devs[i]->c_ident[1] &&
164 !strcmp(v,cpu_devs[i]->c_ident[1]))) {
165 c->x86_vendor = i;
166 if (!early)
167 this_cpu = cpu_devs[i];
168 return;
172 if (!printed) {
173 printed++;
174 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
175 printk(KERN_ERR "CPU: Your system may be unstable.\n");
177 c->x86_vendor = X86_VENDOR_UNKNOWN;
178 this_cpu = &default_cpu;
182 static int __init x86_fxsr_setup(char * s)
184 disable_x86_fxsr = 1;
185 return 1;
187 __setup("nofxsr", x86_fxsr_setup);
190 /* Standard macro to see if a specific flag is changeable */
191 static inline int flag_is_changeable_p(u32 flag)
193 u32 f1, f2;
195 asm("pushfl\n\t"
196 "pushfl\n\t"
197 "popl %0\n\t"
198 "movl %0,%1\n\t"
199 "xorl %2,%0\n\t"
200 "pushl %0\n\t"
201 "popfl\n\t"
202 "pushfl\n\t"
203 "popl %0\n\t"
204 "popfl\n\t"
205 : "=&r" (f1), "=&r" (f2)
206 : "ir" (flag));
208 return ((f1^f2) & flag) != 0;
212 /* Probe for the CPUID instruction */
213 static int __cpuinit have_cpuid_p(void)
215 return flag_is_changeable_p(X86_EFLAGS_ID);
218 /* Do minimum CPU detection early.
219 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
220 The others are not touched to avoid unwanted side effects.
222 WARNING: this function is only called on the BP. Don't add code here
223 that is supposed to run on all CPUs. */
224 static void __init early_cpu_detect(void)
226 struct cpuinfo_x86 *c = &boot_cpu_data;
228 c->x86_cache_alignment = 32;
230 if (!have_cpuid_p())
231 return;
233 /* Get vendor name */
234 cpuid(0x00000000, &c->cpuid_level,
235 (int *)&c->x86_vendor_id[0],
236 (int *)&c->x86_vendor_id[8],
237 (int *)&c->x86_vendor_id[4]);
239 get_cpu_vendor(c, 1);
241 c->x86 = 4;
242 if (c->cpuid_level >= 0x00000001) {
243 u32 junk, tfms, cap0, misc;
244 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
245 c->x86 = (tfms >> 8) & 15;
246 c->x86_model = (tfms >> 4) & 15;
247 if (c->x86 == 0xf)
248 c->x86 += (tfms >> 20) & 0xff;
249 if (c->x86 >= 0x6)
250 c->x86_model += ((tfms >> 16) & 0xF) << 4;
251 c->x86_mask = tfms & 15;
252 if (cap0 & (1<<19))
253 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
257 void __cpuinit generic_identify(struct cpuinfo_x86 * c)
259 u32 tfms, xlvl;
260 int junk;
262 if (have_cpuid_p()) {
263 /* Get vendor name */
264 cpuid(0x00000000, &c->cpuid_level,
265 (int *)&c->x86_vendor_id[0],
266 (int *)&c->x86_vendor_id[8],
267 (int *)&c->x86_vendor_id[4]);
269 get_cpu_vendor(c, 0);
270 /* Initialize the standard set of capabilities */
271 /* Note that the vendor-specific code below might override */
273 /* Intel-defined flags: level 0x00000001 */
274 if ( c->cpuid_level >= 0x00000001 ) {
275 u32 capability, excap;
276 cpuid(0x00000001, &tfms, &junk, &excap, &capability);
277 c->x86_capability[0] = capability;
278 c->x86_capability[4] = excap;
279 c->x86 = (tfms >> 8) & 15;
280 c->x86_model = (tfms >> 4) & 15;
281 if (c->x86 == 0xf)
282 c->x86 += (tfms >> 20) & 0xff;
283 if (c->x86 >= 0x6)
284 c->x86_model += ((tfms >> 16) & 0xF) << 4;
285 c->x86_mask = tfms & 15;
286 } else {
287 /* Have CPUID level 0 only - unheard of */
288 c->x86 = 4;
291 /* AMD-defined flags: level 0x80000001 */
292 xlvl = cpuid_eax(0x80000000);
293 if ( (xlvl & 0xffff0000) == 0x80000000 ) {
294 if ( xlvl >= 0x80000001 ) {
295 c->x86_capability[1] = cpuid_edx(0x80000001);
296 c->x86_capability[6] = cpuid_ecx(0x80000001);
298 if ( xlvl >= 0x80000004 )
299 get_model_name(c); /* Default name */
303 early_intel_workaround(c);
305 #ifdef CONFIG_X86_HT
306 phys_proc_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff;
307 #endif
310 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
312 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
313 /* Disable processor serial number */
314 unsigned long lo,hi;
315 rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
316 lo |= 0x200000;
317 wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
318 printk(KERN_NOTICE "CPU serial number disabled.\n");
319 clear_bit(X86_FEATURE_PN, c->x86_capability);
321 /* Disabling the serial number may affect the cpuid level */
322 c->cpuid_level = cpuid_eax(0);
326 static int __init x86_serial_nr_setup(char *s)
328 disable_x86_serial_nr = 0;
329 return 1;
331 __setup("serialnumber", x86_serial_nr_setup);
336 * This does the hard work of actually picking apart the CPU stuff...
338 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
340 int i;
342 c->loops_per_jiffy = loops_per_jiffy;
343 c->x86_cache_size = -1;
344 c->x86_vendor = X86_VENDOR_UNKNOWN;
345 c->cpuid_level = -1; /* CPUID not detected */
346 c->x86_model = c->x86_mask = 0; /* So far unknown... */
347 c->x86_vendor_id[0] = '\0'; /* Unset */
348 c->x86_model_id[0] = '\0'; /* Unset */
349 c->x86_max_cores = 1;
350 memset(&c->x86_capability, 0, sizeof c->x86_capability);
352 if (!have_cpuid_p()) {
353 /* First of all, decide if this is a 486 or higher */
354 /* It's a 486 if we can modify the AC flag */
355 if ( flag_is_changeable_p(X86_EFLAGS_AC) )
356 c->x86 = 4;
357 else
358 c->x86 = 3;
361 generic_identify(c);
363 printk(KERN_DEBUG "CPU: After generic identify, caps:");
364 for (i = 0; i < NCAPINTS; i++)
365 printk(" %08lx", c->x86_capability[i]);
366 printk("\n");
368 if (this_cpu->c_identify) {
369 this_cpu->c_identify(c);
371 printk(KERN_DEBUG "CPU: After vendor identify, caps:");
372 for (i = 0; i < NCAPINTS; i++)
373 printk(" %08lx", c->x86_capability[i]);
374 printk("\n");
378 * Vendor-specific initialization. In this section we
379 * canonicalize the feature flags, meaning if there are
380 * features a certain CPU supports which CPUID doesn't
381 * tell us, CPUID claiming incorrect flags, or other bugs,
382 * we handle them here.
384 * At the end of this section, c->x86_capability better
385 * indicate the features this CPU genuinely supports!
387 if (this_cpu->c_init)
388 this_cpu->c_init(c);
390 /* Disable the PN if appropriate */
391 squash_the_stupid_serial_number(c);
394 * The vendor-specific functions might have changed features. Now
395 * we do "generic changes."
398 /* TSC disabled? */
399 if ( tsc_disable )
400 clear_bit(X86_FEATURE_TSC, c->x86_capability);
402 /* FXSR disabled? */
403 if (disable_x86_fxsr) {
404 clear_bit(X86_FEATURE_FXSR, c->x86_capability);
405 clear_bit(X86_FEATURE_XMM, c->x86_capability);
408 if (disable_pse)
409 clear_bit(X86_FEATURE_PSE, c->x86_capability);
411 /* If the model name is still unset, do table lookup. */
412 if ( !c->x86_model_id[0] ) {
413 char *p;
414 p = table_lookup_model(c);
415 if ( p )
416 strcpy(c->x86_model_id, p);
417 else
418 /* Last resort... */
419 sprintf(c->x86_model_id, "%02x/%02x",
420 c->x86_vendor, c->x86_model);
423 /* Now the feature flags better reflect actual CPU features! */
425 printk(KERN_DEBUG "CPU: After all inits, caps:");
426 for (i = 0; i < NCAPINTS; i++)
427 printk(" %08lx", c->x86_capability[i]);
428 printk("\n");
431 * On SMP, boot_cpu_data holds the common feature set between
432 * all CPUs; so make sure that we indicate which features are
433 * common between the CPUs. The first time this routine gets
434 * executed, c == &boot_cpu_data.
436 if ( c != &boot_cpu_data ) {
437 /* AND the already accumulated flags with these */
438 for ( i = 0 ; i < NCAPINTS ; i++ )
439 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
442 /* Init Machine Check Exception if available. */
443 mcheck_init(c);
445 if (c == &boot_cpu_data)
446 sysenter_setup();
447 enable_sep_cpu();
449 if (c == &boot_cpu_data)
450 mtrr_bp_init();
451 else
452 mtrr_ap_init();
455 #ifdef CONFIG_X86_HT
456 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
458 u32 eax, ebx, ecx, edx;
459 int index_msb, core_bits;
460 int cpu = smp_processor_id();
462 cpuid(1, &eax, &ebx, &ecx, &edx);
464 c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0);
466 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
467 return;
469 smp_num_siblings = (ebx & 0xff0000) >> 16;
471 if (smp_num_siblings == 1) {
472 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
473 } else if (smp_num_siblings > 1 ) {
475 if (smp_num_siblings > NR_CPUS) {
476 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
477 smp_num_siblings = 1;
478 return;
481 index_msb = get_count_order(smp_num_siblings);
482 phys_proc_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
484 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
485 phys_proc_id[cpu]);
487 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
489 index_msb = get_count_order(smp_num_siblings) ;
491 core_bits = get_count_order(c->x86_max_cores);
493 cpu_core_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) &
494 ((1 << core_bits) - 1);
496 if (c->x86_max_cores > 1)
497 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
498 cpu_core_id[cpu]);
501 #endif
503 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
505 char *vendor = NULL;
507 if (c->x86_vendor < X86_VENDOR_NUM)
508 vendor = this_cpu->c_vendor;
509 else if (c->cpuid_level >= 0)
510 vendor = c->x86_vendor_id;
512 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
513 printk("%s ", vendor);
515 if (!c->x86_model_id[0])
516 printk("%d86", c->x86);
517 else
518 printk("%s", c->x86_model_id);
520 if (c->x86_mask || c->cpuid_level >= 0)
521 printk(" stepping %02x\n", c->x86_mask);
522 else
523 printk("\n");
526 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
528 /* This is hacky. :)
529 * We're emulating future behavior.
530 * In the future, the cpu-specific init functions will be called implicitly
531 * via the magic of initcalls.
532 * They will insert themselves into the cpu_devs structure.
533 * Then, when cpu_init() is called, we can just iterate over that array.
536 extern int intel_cpu_init(void);
537 extern int cyrix_init_cpu(void);
538 extern int nsc_init_cpu(void);
539 extern int amd_init_cpu(void);
540 extern int centaur_init_cpu(void);
541 extern int transmeta_init_cpu(void);
542 extern int rise_init_cpu(void);
543 extern int nexgen_init_cpu(void);
544 extern int umc_init_cpu(void);
546 void __init early_cpu_init(void)
548 intel_cpu_init();
549 cyrix_init_cpu();
550 nsc_init_cpu();
551 amd_init_cpu();
552 centaur_init_cpu();
553 transmeta_init_cpu();
554 rise_init_cpu();
555 nexgen_init_cpu();
556 umc_init_cpu();
557 early_cpu_detect();
559 #ifdef CONFIG_DEBUG_PAGEALLOC
560 /* pse is not compatible with on-the-fly unmapping,
561 * disable it even if the cpus claim to support it.
563 clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
564 disable_pse = 1;
565 #endif
568 * cpu_init() initializes state that is per-CPU. Some data is already
569 * initialized (naturally) in the bootstrap process, such as the GDT
570 * and IDT. We reload them nevertheless, this function acts as a
571 * 'CPU state barrier', nothing should get across.
573 void __cpuinit cpu_init(void)
575 int cpu = smp_processor_id();
576 struct tss_struct * t = &per_cpu(init_tss, cpu);
577 struct thread_struct *thread = &current->thread;
578 struct desc_struct *gdt;
579 __u32 stk16_off = (__u32)&per_cpu(cpu_16bit_stack, cpu);
580 struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu);
582 if (cpu_test_and_set(cpu, cpu_initialized)) {
583 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
584 for (;;) local_irq_enable();
586 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
588 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
589 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
590 if (tsc_disable && cpu_has_tsc) {
591 printk(KERN_NOTICE "Disabling TSC...\n");
592 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
593 clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability);
594 set_in_cr4(X86_CR4_TSD);
598 * This is a horrible hack to allocate the GDT. The problem
599 * is that cpu_init() is called really early for the boot CPU
600 * (and hence needs bootmem) but much later for the secondary
601 * CPUs, when bootmem will have gone away
603 if (NODE_DATA(0)->bdata->node_bootmem_map) {
604 gdt = (struct desc_struct *)alloc_bootmem_pages(PAGE_SIZE);
605 /* alloc_bootmem_pages panics on failure, so no check */
606 memset(gdt, 0, PAGE_SIZE);
607 } else {
608 gdt = (struct desc_struct *)get_zeroed_page(GFP_KERNEL);
609 if (unlikely(!gdt)) {
610 printk(KERN_CRIT "CPU%d failed to allocate GDT\n", cpu);
611 for (;;)
612 local_irq_enable();
617 * Initialize the per-CPU GDT with the boot GDT,
618 * and set up the GDT descriptor:
620 memcpy(gdt, cpu_gdt_table, GDT_SIZE);
622 /* Set up GDT entry for 16bit stack */
623 *(__u64 *)(&gdt[GDT_ENTRY_ESPFIX_SS]) |=
624 ((((__u64)stk16_off) << 16) & 0x000000ffffff0000ULL) |
625 ((((__u64)stk16_off) << 32) & 0xff00000000000000ULL) |
626 (CPU_16BIT_STACK_SIZE - 1);
628 cpu_gdt_descr->size = GDT_SIZE - 1;
629 cpu_gdt_descr->address = (unsigned long)gdt;
631 load_gdt(cpu_gdt_descr);
632 load_idt(&idt_descr);
635 * Set up and load the per-CPU TSS and LDT
637 atomic_inc(&init_mm.mm_count);
638 current->active_mm = &init_mm;
639 if (current->mm)
640 BUG();
641 enter_lazy_tlb(&init_mm, current);
643 load_esp0(t, thread);
644 set_tss_desc(cpu,t);
645 load_TR_desc();
646 load_LDT(&init_mm.context);
648 #ifdef CONFIG_DOUBLEFAULT
649 /* Set up doublefault TSS pointer in the GDT */
650 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
651 #endif
653 /* Clear %fs and %gs. */
654 asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs");
656 /* Clear all 6 debug registers: */
657 set_debugreg(0, 0);
658 set_debugreg(0, 1);
659 set_debugreg(0, 2);
660 set_debugreg(0, 3);
661 set_debugreg(0, 6);
662 set_debugreg(0, 7);
665 * Force FPU initialization:
667 current_thread_info()->status = 0;
668 clear_used_math();
669 mxcsr_feature_mask_init();
672 #ifdef CONFIG_HOTPLUG_CPU
673 void __cpuinit cpu_uninit(void)
675 int cpu = raw_smp_processor_id();
676 cpu_clear(cpu, cpu_initialized);
678 /* lazy TLB state */
679 per_cpu(cpu_tlbstate, cpu).state = 0;
680 per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;
682 #endif