include/asm-x86_64/io_apic.h

   1 #ifndef __ASM_IO_APIC_H
   2 #define __ASM_IO_APIC_H
   3
   4 #include <linux/config.h>
   5 #include <asm/types.h>
   6 #include <asm/mpspec.h>
   7
   8 /*
   9  * Intel IO-APIC support for SMP and UP systems.
  10  *
  11  * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
  12  */
  13
  14 #ifdef CONFIG_X86_IO_APIC
  15
  16 #define APIC_MISMATCH_DEBUG
  17
  18 #define IO_APIC_BASE(idx) \
  19                 ((volatile int *)(__fix_to_virt(FIX_IO_APIC_BASE_0 + idx) \
  20                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK)))
  21
  22 /*
  23  * The structure of the IO-APIC:
  24  */
  25 union IO_APIC_reg_00 {
  26         u32     raw;
  27         struct {
  28                 u32     __reserved_2    : 14,
  29                         LTS             :  1,
  30                         delivery_type   :  1,
  31                         __reserved_1    :  8,
  32                         ID              :  8;
  33         } __attribute__ ((packed)) bits;
  34 };
  35
  36 union IO_APIC_reg_01 {
  37         u32     raw;
  38         struct {
  39                 u32     version         :  8,
  40                 __reserved_2    :  7,
  41                 PRQ             :  1,
  42                 entries         :  8,
  43                 __reserved_1    :  8;
  44         } __attribute__ ((packed)) bits;
  45 };
  46
  47 union IO_APIC_reg_02 {
  48         u32     raw;
  49         struct {
  50                 u32     __reserved_2    : 24,
  51                 arbitration     :  4,
  52                 __reserved_1    :  4;
  53         } __attribute__ ((packed)) bits;
  54 };
  55
  56 union IO_APIC_reg_03 {
  57         u32     raw;
  58         struct {
  59                 u32     boot_DT         :  1,
  60                         __reserved_1    : 31;
  61         } __attribute__ ((packed)) bits;
  62 };
  63
  64 /*
  65  * # of IO-APICs and # of IRQ routing registers
  66  */
  67 extern int nr_ioapics;
  68 extern int nr_ioapic_registers[MAX_IO_APICS];
  69
  70 enum ioapic_irq_destination_types {
  71         dest_Fixed = 0,
  72         dest_LowestPrio = 1,
  73         dest_SMI = 2,
  74         dest__reserved_1 = 3,
  75         dest_NMI = 4,
  76         dest_INIT = 5,
  77         dest__reserved_2 = 6,
  78         dest_ExtINT = 7
  79 };
  80
  81 struct IO_APIC_route_entry {
  82         __u32   vector          :  8,
  83                 delivery_mode   :  3,   /* 000: FIXED
  84                                          * 001: lowest prio
  85                                          * 111: ExtINT
  86                                          */
  87                 dest_mode       :  1,   /* 0: physical, 1: logical */
  88                 delivery_status :  1,
  89                 polarity        :  1,
  90                 irr             :  1,
  91                 trigger         :  1,   /* 0: edge, 1: level */
  92                 mask            :  1,   /* 0: enabled, 1: disabled */
  93                 __reserved_2    : 15;
  94
  95         union {         struct { __u32
  96                                         __reserved_1    : 24,
  97                                         physical_dest   :  4,
  98                                         __reserved_2    :  4;
  99                         } physical;
 100
 101                         struct { __u32
 102                                         __reserved_1    : 24,
 103                                         logical_dest    :  8;
 104                         } logical;
 105         } dest;
 106
 107 } __attribute__ ((packed));
 108
 109 /*
 110  * MP-BIOS irq configuration table structures:
 111  */
 112
 113 /* I/O APIC entries */
 114 extern struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
 115
 116 /* # of MP IRQ source entries */
 117 extern int mp_irq_entries;
 118
 119 /* MP IRQ source entries */
 120 extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
 121
 122 /* non-0 if default (table-less) MP configuration */
 123 extern int mpc_default_type;
 124
 125 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 126 {
 127         *IO_APIC_BASE(apic) = reg;
 128         return *(IO_APIC_BASE(apic)+4);
 129 }
 130
 131 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 132 {
 133         *IO_APIC_BASE(apic) = reg;
 134         *(IO_APIC_BASE(apic)+4) = value;
 135 }
 136
 137 /*
 138  * Re-write a value: to be used for read-modify-write
 139  * cycles where the read already set up the index register.
 140  */
 141 static inline void io_apic_modify(unsigned int apic, unsigned int value)
 142 {
 143         *(IO_APIC_BASE(apic)+4) = value;
 144 }
 145
 146 /*
 147  * Synchronize the IO-APIC and the CPU by doing
 148  * a dummy read from the IO-APIC
 149  */
 150 static inline void io_apic_sync(unsigned int apic)
 151 {
 152         (void) *(IO_APIC_BASE(apic)+4);
 153 }
 154
 155 /* 1 if "noapic" boot option passed */
 156 extern int skip_ioapic_setup;
 157
 158 /*
 159  * If we use the IO-APIC for IRQ routing, disable automatic
 160  * assignment of PCI IRQ's.
 161  */
 162 #define io_apic_assign_pci_irqs (mp_irq_entries && !skip_ioapic_setup)
 163
 164 #ifdef CONFIG_ACPI_BOOT
 165 extern int io_apic_get_unique_id (int ioapic, int apic_id);
 166 extern int io_apic_get_version (int ioapic);
 167 extern int io_apic_get_redir_entries (int ioapic);
 168 extern int io_apic_set_pci_routing (int ioapic, int pin, int irq);
 169 #endif
 170
 171 #ifdef CONFIG_ACPI_BOOT
 172 extern int io_apic_get_unique_id (int ioapic, int apic_id);
 173 extern int io_apic_get_version (int ioapic);
 174 extern int io_apic_get_redir_entries (int ioapic);
 175 extern int io_apic_set_pci_routing (int ioapic, int pin, int irq);
 176 #endif
 177
 178 extern int sis_apic_bug; /* dummy */
 179
 180
 181 #else  /* !CONFIG_X86_IO_APIC */
 182 #define io_apic_assign_pci_irqs 0
 183 #endif
 184
 185 void enable_NMI_through_LVT0 (void * dummy);
 186
 187 #endif