include/asm-v850/sim85e2c.h

   1 /*
   2  * include/asm-v850/sim85e2c.h -- Machine-dependent defs for
   3  *      V850E2 RTL simulator
   4  *
   5  *  Copyright (C) 2002  NEC Corporation
   6  *  Copyright (C) 2002  Miles Bader <miles@gnu.org>
   7  *
   8  * This file is subject to the terms and conditions of the GNU General
   9  * Public License.  See the file COPYING in the main directory of this
  10  * archive for more details.
  11  *
  12  * Written by Miles Bader <miles@gnu.org>
  13  */
  14
  15 #ifndef __V850_SIM85E2C_H__
  16 #define __V850_SIM85E2C_H__
  17
  18
  19 #define CPU_ARCH        "v850e2"
  20 #define CPU_MODEL       "v850e2"
  21 #define CPU_MODEL_LONG  "NEC V850E2"
  22 #define PLATFORM        "sim85e2c"
  23 #define PLATFORM_LONG   "SIM85E2C V850E2 simulator"
  24
  25
  26 /* Various memory areas supported by the simulator.
  27    These should match the corresponding definitions in the linker script.  */
  28
  29 /* `instruction RAM'; instruction fetches are much faster from IRAM than
  30    from DRAM.  */
  31 #define IRAM_ADDR               0
  32 #define IRAM_SIZE               0x00100000 /* 1MB */
  33 /* `data RAM', below and contiguous with the I/O space.
  34    Data fetches are much faster from DRAM than from IRAM.  */
  35 #define DRAM_ADDR               0xfff00000
  36 #define DRAM_SIZE               0x000ff000 /* 1020KB */
  37 /* `external ram'.  Unlike the above RAM areas, this memory is cached,
  38    so both instruction and data fetches should be (mostly) fast --
  39    however, currently only write-through caching is supported, so writes
  40    to ERAM will be slow.  */
  41 #define ERAM_ADDR               0x00100000
  42 #define ERAM_SIZE               0x07f00000 /* 127MB (max) */
  43
  44
  45 /* CPU core control registers; these should be expanded and moved into
  46    separate header files when we support some other processors based on
  47    the same E2 core.  */
  48 /* Bus Transaction Control Register */
  49 #define NA85E2C_CACHE_BTSC_ADDR 0xfffff070
  50 #define NA85E2C_CACHE_BTSC      (*(volatile unsigned short *)NA85E2C_CACHE_BTSC_ADDR)
  51 #define NA85E2C_CACHE_BTSC_ICM  0x1 /* icache enable */
  52 #define NA85E2C_CACHE_BTSC_DCM0 0x4 /* dcache enable, bit 0 */
  53 #define NA85E2C_CACHE_BTSC_DCM1 0x8 /* dcache enable, bit 1 */
  54 /* Cache Configuration Register */
  55 #define NA85E2C_BUSM_BHC_ADDR   0xfffff06a
  56 #define NA85E2C_BUSM_BHC        (*(volatile unsigned short *)NA85E2C_BUSM_BHC_ADDR)
  57
  58 /* Simulator specific control registers.  */
  59 /* NOTHAL controls whether the simulator will stop at a `halt' insn.  */
  60 #define NOTHAL_ADDR             0xffffff22
  61 #define NOTHAL                  (*(volatile unsigned char *)NOTHAL_ADDR)
  62 /* The simulator will stop N cycles after N is written to SIMFIN.  */
  63 #define SIMFIN_ADDR             0xffffff24
  64 #define SIMFIN                  (*(volatile unsigned short *)SIMFIN_ADDR)
  65
  66
  67 /* The simulator has an nb85e-style interrupt system.  */
  68 #include <asm/nb85e_intc.h>
  69
  70 /* For <asm/irq.h> */
  71 #define NUM_CPU_IRQS            64
  72
  73
  74 /* For <asm/page.h> */
  75 #define PAGE_OFFSET             DRAM_ADDR
  76
  77
  78 /* For <asm/entry.h> */
  79 /* `R0 RAM', used for a few miscellaneous variables that must be accessible
  80    using a load instruction relative to R0.  The sim85e2c simulator
  81    actually puts 1020K of RAM from FFF00000 to FFFFF000, so we arbitarily
  82    choose a small portion at the end of that.  */
  83 #define R0_RAM_ADDR             0xFFFFE000
  84
  85
  86 /* For <asm/param.h> */
  87 #ifndef HZ
  88 #define HZ                      24      /* Minimum supported frequency.  */
  89 #endif
  90
  91
  92 #endif /* __V850_SIM85E2C_H__ */