arch/mips/pci/pci-vr41xx.h

   1 /*
   2  * FILE NAME
   3  *      arch/mips/vr41xx/common/pciu.h
   4  *
   5  * BRIEF MODULE DESCRIPTION
   6  *      Include file for PCI Control Unit of the NEC VR4100 series.
   7  *
   8  * Author: Yoichi Yuasa
   9  *         yyuasa@mvista.com or source@mvista.com
  10  *
  11  * Copyright 2002 MontaVista Software Inc.
  12  *
  13  *  This program is free software; you can redistribute it and/or modify it
  14  *  under the terms of the GNU General Public License as published by the
  15  *  Free Software Foundation; either version 2 of the License, or (at your
  16  *  option) any later version.
  17  *
  18  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  19  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  20  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  23  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  24  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  25  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  26  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  27  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  *  You should have received a copy of the GNU General Public License along
  30  *  with this program; if not, write to the Free Software Foundation, Inc.,
  31  *  675 Mass Ave, Cambridge, MA 02139, USA.
  32  */
  33 /*
  34  * Changes:
  35  *  MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
  36  *  - New creation, NEC VR4122 and VR4131 are supported.
  37  */
  38 #ifndef __VR41XX_PCIU_H
  39 #define __VR41XX_PCIU_H
  40
  41 #include <linux/config.h>
  42 #include <asm/addrspace.h>
  43
  44 #define BIT(x)  (1 << (x))
  45
  46 #define PCIMMAW1REG                     KSEG1ADDR(0x0f000c00)
  47 #define PCIMMAW2REG                     KSEG1ADDR(0x0f000c04)
  48 #define PCITAW1REG                      KSEG1ADDR(0x0f000c08)
  49 #define PCITAW2REG                      KSEG1ADDR(0x0f000c0c)
  50 #define PCIMIOAWREG                     KSEG1ADDR(0x0f000c10)
  51 #define INTERNAL_BUS_BASE_ADDRESS       0xff000000
  52 #define ADDRESS_MASK                    0x000fe000
  53 #define PCI_ACCESS_ENABLE               BIT(12)
  54 #define PCI_ADDRESS_SETTING             0x000000ff
  55
  56 #define PCICONFDREG                     KSEG1ADDR(0x0f000c14)
  57 #define PCICONFAREG                     KSEG1ADDR(0x0f000c18)
  58 #define PCIMAILREG                      KSEG1ADDR(0x0f000c1c)
  59
  60 #define BUSERRADREG                     KSEG1ADDR(0x0f000c24)
  61 #define ERROR_ADDRESS                   0xfffffffc
  62
  63 #define INTCNTSTAREG                    KSEG1ADDR(0x0f000c28)
  64 #define MABTCLR                         BIT(31)
  65 #define TRDYCLR                         BIT(30)
  66 #define PARCLR                          BIT(29)
  67 #define MBCLR                           BIT(28)
  68 #define SERRCLR                         BIT(27)
  69
  70 #define PCIEXACCREG                     KSEG1ADDR(0x0f000c2c)
  71 #define UNLOCK                          BIT(1)
  72 #define EAREQ                           BIT(0)
  73
  74 #define PCIRECONTREG                    KSEG1ADDR(0x0f000c30)
  75 #define RTRYCNT                         0x000000ff
  76
  77 #define PCIENREG                        KSEG1ADDR(0x0f000c34)
  78 #define CONFIG_DONE                     BIT(2)
  79
  80 #define PCICLKSELREG                    KSEG1ADDR(0x0f000c38)
  81 #define EQUAL_VTCLOCK                   0x00000002
  82 #define HALF_VTCLOCK                    0x00000000
  83 #define QUARTER_VTCLOCK                 0x00000001
  84
  85 #define PCITRDYVREG                     KSEG1ADDR(0x0f000c3c)
  86
  87 #define PCICLKRUNREG                    KSEG1ADDR(0x0f000c60)
  88
  89 #define PCIU_CONFIGREGS_BASE            KSEG1ADDR(0x0f000d00)
  90 #define VENDORIDREG                     KSEG1ADDR(0x0f000d00)
  91 #define DEVICEIDREG                     KSEG1ADDR(0x0f000d00)
  92 #define COMMANDREG                      KSEG1ADDR(0x0f000d04)
  93 #define STATUSREG                       KSEG1ADDR(0x0f000d04)
  94 #define REVIDREG                        KSEG1ADDR(0x0f000d08)
  95 #define CLASSREG                        KSEG1ADDR(0x0f000d08)
  96 #define CACHELSREG                      KSEG1ADDR(0x0f000d0c)
  97 #define LATTIMEREG                      KSEG1ADDR(0x0f000d0c)
  98 #define MAILBAREG                       KSEG1ADDR(0x0f000d10)
  99 #define PCIMBA1REG                      KSEG1ADDR(0x0f000d14)
 100 #define PCIMBA2REG                      KSEG1ADDR(0x0f000d18)
 101 #define INTLINEREG                      KSEG1ADDR(0x0f000d3c)
 102 #define INTPINREG                       KSEG1ADDR(0x0f000d3c)
 103 #define RETVALREG                       KSEG1ADDR(0x0f000d40)
 104 #define PCIAPCNTREG                     KSEG1ADDR(0x0f000d40)
 105
 106 #define MPCIINTREG                      KSEG1ADDR(0x0f0000b2)
 107
 108 #define MAX_PCI_CLOCK                   33333333
 109
 110 #define PCIU_CLOCK                      0x0080
 111 #define PCI_CLOCK                       0x2000
 112
 113 static inline int pciu_read_config_byte(int where, u8 * val)
 114 {
 115         u32 data;
 116
 117         data = readl(PCIU_CONFIGREGS_BASE + where);
 118         *val = (u8) (data >> ((where & 3) << 3));
 119
 120         return PCIBIOS_SUCCESSFUL;
 121 }
 122
 123 static inline int pciu_read_config_word(int where, u16 * val)
 124 {
 125         u32 data;
 126
 127         if (where & 1)
 128                 return PCIBIOS_BAD_REGISTER_NUMBER;
 129
 130         data = readl(PCIU_CONFIGREGS_BASE + where);
 131         *val = (u16) (data >> ((where & 2) << 3));
 132
 133         return PCIBIOS_SUCCESSFUL;
 134 }
 135
 136 static inline int pciu_read_config_dword(int where, u32 * val)
 137 {
 138         if (where & 3)
 139                 return PCIBIOS_BAD_REGISTER_NUMBER;
 140
 141         *val = readl(PCIU_CONFIGREGS_BASE + where);
 142
 143         return PCIBIOS_SUCCESSFUL;
 144 }
 145
 146 static inline int pciu_write_config_byte(int where, u8 val)
 147 {
 148         writel(val, PCIU_CONFIGREGS_BASE + where);
 149
 150         return 0;
 151 }
 152
 153 static inline int pciu_write_config_word(int where, u16 val)
 154 {
 155         writel(val, PCIU_CONFIGREGS_BASE + where);
 156
 157         return 0;
 158 }
 159
 160 static inline int pciu_write_config_dword(int where, u32 val)
 161 {
 162         writel(val, PCIU_CONFIGREGS_BASE + where);
 163
 164         return 0;
 165 }
 166
 167 #endif                          /* __VR41XX_PCIU_H */