arch/mips/pci/pci-vr41xx.c

   1 /*
   2  * FILE NAME
   3  *      arch/mips/vr41xx/common/pciu.c
   4  *
   5  * BRIEF MODULE DESCRIPTION
   6  *      PCI Control Unit routines for the NEC VR4100 series.
   7  *
   8  * Author: Yoichi Yuasa
   9  *         yyuasa@mvista.com or source@mvista.com
  10  *
  11  * Copyright 2001,2002 MontaVista Software Inc.
  12  *
  13  *  This program is free software; you can redistribute it and/or modify it
  14  *  under the terms of the GNU General Public License as published by the
  15  *  Free Software Foundation; either version 2 of the License, or (at your
  16  *  option) any later version.
  17  *
  18  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  19  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  20  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  23  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  24  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  25  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  26  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  27  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  *  You should have received a copy of the GNU General Public License along
  30  *  with this program; if not, write to the Free Software Foundation, Inc.,
  31  *  675 Mass Ave, Cambridge, MA 02139, USA.
  32  */
  33 /*
  34  * Changes:
  35  *  Paul Mundt <lethal@chaoticdreams.org>
  36  *  - Fix deadlock-causing PCIU access race for VR4131.
  37  *
  38  *  MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
  39  *  - New creation, NEC VR4122 and VR4131 are supported.
  40  */
  41 #include <linux/config.h>
  42 #include <linux/init.h>
  43 #include <linux/pci.h>
  44 #include <linux/types.h>
  45 #include <linux/delay.h>
  46
  47 #include <asm/cpu.h>
  48 #include <asm/io.h>
  49 #include <asm/pci_channel.h>
  50 #include <asm/vr41xx/vr41xx.h>
  51
  52 #include "pciu.h"
  53
  54 extern unsigned long vr41xx_vtclock;
  55
  56 static inline int vr41xx_pci_config_access(unsigned char bus,
  57                                            unsigned int devfn, int where)
  58 {
  59         if (bus == 0) {
  60                 /*
  61                  * Type 0 configuration
  62                  */
  63                 if (PCI_SLOT(devfn) < 11 || where > 255)
  64                         return -1;
  65
  66                 writel((1UL << PCI_SLOT(devfn)) |
  67                        (PCI_FUNC(devfn) << 8) |
  68                        (where & 0xfc), PCICONFAREG);
  69         } else {
  70                 /*
  71                  * Type 1 configuration
  72                  */
  73                 if (where > 255)
  74                         return -1;
  75
  76                 writel((bus << 16) |
  77                        (devfn << 8) | (where & 0xfc) | 1UL, PCICONFAREG);
  78         }
  79
  80         return 0;
  81 }
  82
  83 static int vr41xx_pci_config_read(struct pci_bus *bus, unsigned int devfn,
  84                                   int where, int size, u32 * val)
  85 {
  86         u32 data;
  87
  88         *val = 0xffffffffUL;
  89         if (vr41xx_pci_config_access(bus->number, devfn, where) < 0)
  90                 return PCIBIOS_DEVICE_NOT_FOUND;
  91
  92         data = readl(PCICONFDREG);
  93
  94         switch (size) {
  95         case 1:
  96                 *val = (data >> ((where & 3) << 3)) & 0xffUL;
  97                 break;
  98         case 2:
  99                 *val = (data >> ((where & 2) << 3)) & 0xffffUL;
 100                 break;
 101         case 4:
 102                 *val = data;
 103                 break;
 104         default:
 105                 return PCIBIOS_FUNC_NOT_SUPPORTED;
 106         }
 107
 108         return PCIBIOS_SUCCESSFUL;
 109 }
 110
 111 static int vr41xx_pci_config_write(struct pci_bus *bus, unsigned int devfn,
 112                                    int where, int size, u32 val)
 113 {
 114         u32 data;
 115         int shift;
 116
 117         if (vr41xx_pci_config_access(bus->number, devfn, where) < 0)
 118                 return PCIBIOS_DEVICE_NOT_FOUND;
 119
 120         data = readl(PCICONFDREG);
 121
 122         switch (size) {
 123         case 1:
 124                 shift = (where & 3) << 3;
 125                 data &= ~(0xff << shift);
 126                 data |= ((val & 0xff) << shift);
 127                 break;
 128         case 2:
 129                 shift = (where & 2) << 3;
 130                 data &= ~(0xffff << shift);
 131                 data |= ((val & 0xffff) << shift);
 132                 break;
 133         case 4:
 134                 data = val;
 135                 break;
 136         default:
 137                 return PCIBIOS_FUNC_NOT_SUPPORTED;
 138         }
 139
 140         writel(data, PCICONFDREG);
 141
 142         return PCIBIOS_SUCCESSFUL;
 143 }
 144
 145 struct pci_ops vr41xx_pci_ops = {
 146         .read = vr41xx_pci_config_read,
 147         .write = vr41xx_pci_config_write,
 148 };
 149
 150 void __init vr41xx_pciu_init(struct vr41xx_pci_address_map *map)
 151 {
 152         struct vr41xx_pci_address_space *s;
 153         u32 config;
 154         int n;
 155
 156         if (!map)
 157                 return;
 158
 159         /* Disable PCI interrupt */
 160         writew(0, MPCIINTREG);
 161
 162         /* Supply VTClock to PCIU */
 163         vr41xx_clock_supply(PCIU_CLOCK);
 164
 165         /*
 166          * Sleep for 1us after setting MSKPPCIU bit in CMUCLKMSK
 167          * before doing any PCIU access to avoid deadlock on VR4131.
 168          */
 169         udelay(1);
 170
 171         /* Select PCI clock */
 172         if (vr41xx_vtclock < MAX_PCI_CLOCK)
 173                 writel(EQUAL_VTCLOCK, PCICLKSELREG);
 174         else if ((vr41xx_vtclock / 2) < MAX_PCI_CLOCK)
 175                 writel(HALF_VTCLOCK, PCICLKSELREG);
 176         else if ((vr41xx_vtclock / 4) < MAX_PCI_CLOCK)
 177                 writel(QUARTER_VTCLOCK, PCICLKSELREG);
 178         else
 179                 printk(KERN_INFO "Warning: PCI Clock is over 33MHz.\n");
 180
 181         /* Supply PCI clock by PCI bus */
 182         vr41xx_clock_supply(PCI_CLOCK);
 183
 184         /*
 185          * Set PCI memory & I/O space address conversion registers
 186          * for master transaction.
 187          */
 188         if (map->mem1 != NULL) {
 189                 s = map->mem1;
 190                 config = (s->internal_base & 0xff000000) |
 191                     ((s->address_mask & 0x7f000000) >> 11) | (1UL << 12) |
 192                     ((s->pci_base & 0xff000000) >> 24);
 193                 writel(config, PCIMMAW1REG);
 194         }
 195         if (map->mem2 != NULL) {
 196                 s = map->mem2;
 197                 config = (s->internal_base & 0xff000000) |
 198                     ((s->address_mask & 0x7f000000) >> 11) | (1UL << 12) |
 199                     ((s->pci_base & 0xff000000) >> 24);
 200                 writel(config, PCIMMAW2REG);
 201         }
 202         if (map->io != NULL) {
 203                 s = map->io;
 204                 config = (s->internal_base & 0xff000000) |
 205                     ((s->address_mask & 0x7f000000) >> 11) | (1UL << 12) |
 206                     ((s->pci_base & 0xff000000) >> 24);
 207                 writel(config, PCIMIOAWREG);
 208         }
 209
 210         /* Set target memory windows */
 211         writel(0x00081000, PCITAW1REG);
 212         writel(0UL, PCITAW2REG);
 213         pciu_write_config_dword(PCI_BASE_ADDRESS_0, 0UL);
 214         pciu_write_config_dword(PCI_BASE_ADDRESS_1, 0UL);
 215
 216         /* Clear bus error */
 217         n = readl(BUSERRADREG);
 218
 219         if (current_cpu_data.cputype == CPU_VR4122) {
 220                 writel(0UL, PCITRDYVREG);
 221                 pciu_write_config_dword(PCI_CACHE_LINE_SIZE, 0x0000f804);
 222         } else {
 223                 writel(100UL, PCITRDYVREG);
 224                 pciu_write_config_dword(PCI_CACHE_LINE_SIZE, 0x00008004);
 225         }
 226
 227         writel(CONFIG_DONE, PCIENREG);
 228         pciu_write_config_dword(PCI_COMMAND,
 229                                 PCI_COMMAND_IO |
 230                                 PCI_COMMAND_MEMORY |
 231                                 PCI_COMMAND_MASTER |
 232                                 PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
 233 }