arch/mips/pci/pci-sb1250.c

   1 /*
   2  * Copyright (C) 2001,2002 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18
  19 /*
  20  * BCM1250-specific PCI support
  21  *
  22  * This module provides the glue between Linux's PCI subsystem
  23  * and the hardware.  We basically provide glue for accessing
  24  * configuration space, and set up the translation for I/O
  25  * space accesses.
  26  *
  27  * To access configuration space, we use ioremap.  In the 32-bit
  28  * kernel, this consumes either 4 or 8 page table pages, and 16MB of
  29  * kernel mapped memory.  Hopefully neither of these should be a huge
  30  * problem.
  31  */
  32 #include <linux/config.h>
  33 #include <linux/types.h>
  34 #include <linux/pci.h>
  35 #include <linux/kernel.h>
  36 #include <linux/init.h>
  37 #include <linux/mm.h>
  38 #include <linux/console.h>
  39
  40 #include <asm/sibyte/sb1250_defs.h>
  41 #include <asm/sibyte/sb1250_regs.h>
  42 #include <asm/sibyte/sb1250_scd.h>
  43 #include <asm/io.h>
  44
  45 /*
  46  * Macros for calculating offsets into config space given a device
  47  * structure or dev/fun/reg
  48  */
  49 #define CFGOFFSET(bus,devfn,where) (((bus)<<16) + ((devfn)<<8) + (where))
  50 #define CFGADDR(bus,devfn,where)   CFGOFFSET((bus)->number,(devfn),where)
  51
  52 static void *cfg_space;
  53
  54 #define PCI_BUS_ENABLED 1
  55 #define LDT_BUS_ENABLED 2
  56 #define PCI_DEVICE_MODE 4
  57
  58 static int sb1250_bus_status = 0;
  59
  60 #define PCI_BRIDGE_DEVICE  0
  61 #define LDT_BRIDGE_DEVICE  1
  62
  63 #ifdef CONFIG_SIBYTE_HAS_LDT
  64 /*
  65  * HT's level-sensitive interrupts require EOI, which is generated
  66  * through a 4MB memory-mapped region
  67  */
  68 unsigned long ldt_eoi_space;
  69 #endif
  70
  71 /*
  72  * Read/write 32-bit values in config space.
  73  */
  74 static inline u32 READCFG32(u32 addr)
  75 {
  76         return *(u32 *) (cfg_space + (addr & ~3));
  77 }
  78
  79 static inline void WRITECFG32(u32 addr, u32 data)
  80 {
  81         *(u32 *) (cfg_space + (addr & ~3)) = data;
  82 }
  83
  84 /*
  85  * Some checks before doing config cycles:
  86  * In PCI Device Mode, hide everything on bus 0 except the LDT host
  87  * bridge.  Otherwise, access is controlled by bridge MasterEn bits.
  88  */
  89 static int sb1250_pci_can_access(struct pci_bus *bus, int devfn)
  90 {
  91         u32 devno;
  92
  93         if (!(sb1250_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))
  94                 return 0;
  95
  96         if (bus->number == 0) {
  97                 devno = PCI_SLOT(devfn);
  98                 if (devno == LDT_BRIDGE_DEVICE)
  99                         return (sb1250_bus_status & LDT_BUS_ENABLED) != 0;
 100                 else if (sb1250_bus_status & PCI_DEVICE_MODE)
 101                         return 0;
 102                 else
 103                         return 1;
 104         } else
 105                 return 1;
 106 }
 107
 108 /*
 109  * Read/write access functions for various sizes of values
 110  * in config space.  Return all 1's for disallowed accesses
 111  * for a kludgy but adequate simulation of master aborts.
 112  */
 113
 114 static int sb1250_pcibios_read(struct pci_bus *bus, unsigned int devfn,
 115                                int where, int size, u32 * val)
 116 {
 117         u32 data = 0;
 118
 119         if ((size == 2) && (where & 1))
 120                 return PCIBIOS_BAD_REGISTER_NUMBER;
 121         else if ((size == 4) && (where & 3))
 122                 return PCIBIOS_BAD_REGISTER_NUMBER;
 123
 124         if (sb1250_pci_can_access(bus, devfn))
 125                 data = READCFG32(CFGADDR(bus, devfn, where));
 126         else
 127                 data = 0xFFFFFFFF;
 128
 129         if (size == 1)
 130                 *val = (data >> ((where & 3) << 3)) & 0xff;
 131         else if (size == 2)
 132                 *val = (data >> ((where & 3) << 3)) & 0xffff;
 133         else
 134                 *val = data;
 135
 136         return PCIBIOS_SUCCESSFUL;
 137 }
 138
 139 static int sb1250_pcibios_write(struct pci_bus *bus, unsigned int devfn,
 140                                 int where, int size, u32 val)
 141 {
 142         u32 cfgaddr = CFGADDR(bus, devfn, where);
 143         u32 data = 0;
 144
 145         if ((size == 2) && (where & 1))
 146                 return PCIBIOS_BAD_REGISTER_NUMBER;
 147         else if ((size == 4) && (where & 3))
 148                 return PCIBIOS_BAD_REGISTER_NUMBER;
 149
 150         if (!sb1250_pci_can_access(bus, devfn))
 151                 return PCIBIOS_BAD_REGISTER_NUMBER;
 152
 153         data = READCFG32(cfgaddr);
 154
 155         if (size == 1)
 156                 data = (data & ~(0xff << ((where & 3) << 3))) |
 157                     (val << ((where & 3) << 3));
 158         else if (size == 2)
 159                 data = (data & ~(0xffff << ((where & 3) << 3))) |
 160                     (val << ((where & 3) << 3));
 161
 162         WRITECFG32(cfgaddr, data);
 163
 164         return PCIBIOS_SUCCESSFUL;
 165 }
 166
 167 struct pci_ops sb1250_pci_ops = {
 168         .read = sb1250_pcibios_read,
 169         .write = sb1250_pcibios_write
 170 };
 171
 172
 173 void __init pcibios_init(void)
 174 {
 175         uint32_t cmdreg;
 176         uint64_t reg;
 177
 178         cfg_space =
 179             ioremap(A_PHYS_LDTPCI_CFG_MATCH_BITS, 16 * 1024 * 1024);
 180
 181         /*
 182          * See if the PCI bus has been configured by the firmware.
 183          */
 184         reg = *((volatile uint64_t *) KSEG1ADDR(A_SCD_SYSTEM_CFG));
 185         if (!(reg & M_SYS_PCI_HOST)) {
 186                 sb1250_bus_status |= PCI_DEVICE_MODE;
 187         } else {
 188                 cmdreg =
 189                     READCFG32(CFGOFFSET
 190                               (0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
 191                                PCI_COMMAND));
 192                 if (!(cmdreg & PCI_COMMAND_MASTER)) {
 193                         printk
 194                             ("PCI: Skipping PCI probe.  Bus is not initialized.\n");
 195                         iounmap(cfg_space);
 196                         return;
 197                 }
 198                 sb1250_bus_status |= PCI_BUS_ENABLED;
 199         }
 200
 201         /*
 202          * Establish mappings in KSEG2 (kernel virtual) to PCI I/O
 203          * space.  Use "match bytes" policy to make everything look
 204          * little-endian.  So, you need to also set
 205          * CONFIG_SWAP_IO_SPACE, but this is the combination that
 206          * works correctly with most of Linux's drivers.
 207          * XXX ehs: Should this happen in PCI Device mode?
 208          */
 209
 210         set_io_port_base((unsigned long)
 211                          ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 65536));
 212         isa_slot_offset = (unsigned long)
 213             ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES_32, 1024 * 1024);
 214
 215 #ifdef CONFIG_SIBYTE_HAS_LDT
 216         /*
 217          * Also check the LDT bridge's enable, just in case we didn't
 218          * initialize that one.
 219          */
 220
 221         cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(LDT_BRIDGE_DEVICE, 0),
 222                                      PCI_COMMAND));
 223         if (cmdreg & PCI_COMMAND_MASTER) {
 224                 sb1250_bus_status |= LDT_BUS_ENABLED;
 225
 226                 /*
 227                  * Need bits 23:16 to convey vector number.  Note that
 228                  * this consumes 4MB of kernel-mapped memory
 229                  * (Kseg2/Kseg3) for 32-bit kernel.
 230                  */
 231                 ldt_eoi_space = (unsigned long)
 232                     ioremap(A_PHYS_LDT_SPECIAL_MATCH_BYTES,
 233                             4 * 1024 * 1024);
 234         }
 235 #endif
 236
 237         /* Probe for PCI hardware */
 238
 239         printk("PCI: Probing PCI hardware on host bus 0.\n");
 240         pci_scan_bus(0, &sb1250_pci_ops, NULL);
 241
 242 #ifdef CONFIG_VGA_CONSOLE
 243         take_over_console(&vga_con, 0, MAX_NR_CONSOLES - 1, 1);
 244 #endif
 245 }
 246
 247 int pcibios_enable_device(struct pci_dev *dev, int mask)
 248 {
 249         /* Not needed, since we enable all devices at startup.  */
 250         return 0;
 251 }
 252
 253 void pcibios_align_resource(void *data, struct resource *res,
 254                             unsigned long size, unsigned long align)
 255 {
 256 }
 257
 258 char *__init pcibios_setup(char *str)
 259 {
 260         /* Nothing to do for now.  */
 261
 262         return str;
 263 }
 264
 265 struct pci_fixup pcibios_fixups[] = {
 266         {0}
 267 };
 268
 269 /*
 270  *  Called after each bus is probed, but before its children
 271  *  are examined.
 272  */
 273 void __devinit pcibios_fixup_bus(struct pci_bus *b)
 274 {
 275         pci_read_bridge_bases(b);
 276 }
 277
 278 unsigned int pcibios_assign_all_busses(void)
 279 {
 280         return 1;
 281 }