arch/mips/pci/pci-mips.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 1999, 2000 MIPS Technologies, Inc.  All rights reserved.
   4  *
   5  *  This program is free software; you can distribute it and/or modify it
   6  *  under the terms of the GNU General Public License (Version 2) as
   7  *  published by the Free Software Foundation.
   8  *
   9  *  This program is distributed in the hope it will be useful, but WITHOUT
  10  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  *  for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License along
  15  *  with this program; if not, write to the Free Software Foundation, Inc.,
  16  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17  *
  18  * MIPS boards specific PCI support.
  19  *
  20  */
  21 #include <linux/config.h>
  22 #include <linux/types.h>
  23 #include <linux/pci.h>
  24 #include <linux/kernel.h>
  25 #include <linux/init.h>
  26
  27 #include <asm/mips-boards/generic.h>
  28 #include <asm/gt64120.h>
  29 #include <asm/mips-boards/bonito64.h>
  30 #ifdef CONFIG_MIPS_MALTA
  31 #include <asm/mips-boards/malta.h>
  32 #endif
  33 #include <asm/mips-boards/msc01_pci.h>
  34
  35 #define PCI_ACCESS_READ  0
  36 #define PCI_ACCESS_WRITE 1
  37
  38 /*
  39  *  PCI configuration cycle AD bus definition
  40  */
  41 /* Type 0 */
  42 #define PCI_CFG_TYPE0_REG_SHF           0
  43 #define PCI_CFG_TYPE0_FUNC_SHF          8
  44
  45 /* Type 1 */
  46 #define PCI_CFG_TYPE1_REG_SHF           0
  47 #define PCI_CFG_TYPE1_FUNC_SHF          8
  48 #define PCI_CFG_TYPE1_DEV_SHF           11
  49 #define PCI_CFG_TYPE1_BUS_SHF           16
  50
  51 static int mips_pcibios_config_access(unsigned char access_type,
  52                                       struct pci_bus *bus,
  53                                       unsigned int devfn, int where,
  54                                       u32 * data)
  55 {
  56         unsigned char busnum = bus->number;
  57         unsigned char type;
  58         u32 intr, dummy;
  59         u64 pci_addr;
  60
  61         switch (mips_revision_corid) {
  62         case MIPS_REVISION_CORID_QED_RM5261:
  63         case MIPS_REVISION_CORID_CORE_LV:
  64         case MIPS_REVISION_CORID_CORE_FPGA:
  65                 /* Galileo GT64120 system controller. */
  66
  67                 if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0)))
  68                         return -1;      /* Because of a bug in the galileo (for slot 31). */
  69
  70                 /* Clear cause register bits */
  71                 GT_READ(GT_INTRCAUSE_OFS, intr);
  72                 GT_WRITE(GT_INTRCAUSE_OFS, intr &
  73                          ~(GT_INTRCAUSE_MASABORT0_BIT |
  74                            GT_INTRCAUSE_TARABORT0_BIT));
  75
  76                 /* Setup address */
  77                 GT_WRITE(GT_PCI0_CFGADDR_OFS,
  78                          (busnum << GT_PCI0_CFGADDR_BUSNUM_SHF) |
  79                          (devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
  80                          ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
  81                          GT_PCI0_CFGADDR_CONFIGEN_BIT);
  82
  83                 if (access_type == PCI_ACCESS_WRITE) {
  84                         if (busnum == 0 && devfn == 0) {
  85                                 /*
  86                                  * The Galileo system controller is acting
  87                                  * differently than other devices.
  88                                  */
  89                                 GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
  90                         } else {
  91                                 GT_PCI_WRITE(GT_PCI0_CFGDATA_OFS, *data);
  92                         }
  93                 } else {
  94                         if (busnum == 0 && devfn == 0) {
  95                                 /*
  96                                  * The Galileo system controller is acting
  97                                  * differently than other devices.
  98                                  */
  99                                 GT_READ(GT_PCI0_CFGDATA_OFS, *data);
 100                         } else {
 101                                 GT_PCI_READ(GT_PCI0_CFGDATA_OFS, *data);
 102                         }
 103                 }
 104
 105                 /* Check for master or target abort */
 106                 GT_READ(GT_INTRCAUSE_OFS, intr);
 107
 108                 if (intr & (GT_INTRCAUSE_MASABORT0_BIT |
 109                             GT_INTRCAUSE_TARABORT0_BIT)) {
 110                         /* Error occurred */
 111
 112                         /* Clear bits */
 113                         GT_READ(GT_INTRCAUSE_OFS, intr);
 114                         GT_WRITE(GT_INTRCAUSE_OFS, intr &
 115                                  ~(GT_INTRCAUSE_MASABORT0_BIT |
 116                                    GT_INTRCAUSE_TARABORT0_BIT));
 117
 118                         return -1;
 119                 }
 120
 121                 break;
 122
 123         case MIPS_REVISION_CORID_BONITO64:
 124         case MIPS_REVISION_CORID_CORE_20K:
 125                 /* Algorithmics Bonito64 system controller. */
 126
 127                 if ((busnum == 0) && (PCI_SLOT(devfn) == 0)) {
 128                         return -1;
 129                 }
 130
 131                 /* Clear cause register bits */
 132                 BONITO_PCICMD |= (BONITO_PCICMD_MABORT_CLR |
 133                                   BONITO_PCICMD_MTABORT_CLR);
 134
 135                 /*
 136                  * Setup pattern to be used as PCI "address" for
 137                  * Type 0 cycle
 138                  */
 139                 if (busnum == 0) {
 140                         /* IDSEL */
 141                         pci_addr = (u64) 1 << (PCI_SLOT(devfn) + 10);
 142                 } else {
 143                         /* Bus number */
 144                         pci_addr = busnum << PCI_CFG_TYPE1_BUS_SHF;
 145
 146                         /* Device number */
 147                         pci_addr |=
 148                             PCI_SLOT(devfn) << PCI_CFG_TYPE1_DEV_SHF;
 149                 }
 150
 151                 /* Function (same for Type 0/1) */
 152                 pci_addr |= PCI_FUNC(devfn) << PCI_CFG_TYPE0_FUNC_SHF;
 153
 154                 /* Register number (same for Type 0/1) */
 155                 pci_addr |= (where & ~0x3) << PCI_CFG_TYPE0_REG_SHF;
 156
 157                 if (busnum == 0) {
 158                         /* Type 0 */
 159                         BONITO_PCIMAP_CFG = pci_addr >> 16;
 160                 } else {
 161                         /* Type 1 */
 162                         BONITO_PCIMAP_CFG = (pci_addr >> 16) | 0x10000;
 163                 }
 164
 165                 /* Flush Bonito register block */
 166                 dummy = BONITO_PCIMAP_CFG;
 167                 iob();          /* sync */
 168
 169                 /* Perform access */
 170                 if (access_type == PCI_ACCESS_WRITE) {
 171                         *(volatile u32 *) (KSEG1ADDR(BONITO_PCICFG_BASE +
 172                                                      (pci_addr & 0xffff)))
 173                             = *(u32 *) data;
 174
 175                         /* Wait till done */
 176                         while (BONITO_PCIMSTAT & 0xF);
 177                 } else {
 178                         *(u32 *) data =
 179                             *(volatile u32
 180                               *) (KSEG1ADDR(BONITO_PCICFG_BASE +
 181                                             (pci_addr & 0xffff)));
 182                 }
 183
 184                 /* Detect Master/Target abort */
 185                 if (BONITO_PCICMD & (BONITO_PCICMD_MABORT_CLR |
 186                                      BONITO_PCICMD_MTABORT_CLR)) {
 187                         /* Error occurred */
 188
 189                         /* Clear bits */
 190                         BONITO_PCICMD |= (BONITO_PCICMD_MABORT_CLR |
 191                                           BONITO_PCICMD_MTABORT_CLR);
 192
 193                         return -1;
 194                 }
 195                 break;
 196
 197         case MIPS_REVISION_CORID_CORE_MSC:
 198                 /* MIPS system controller. */
 199
 200                 if ((busnum == 0) && (PCI_SLOT(devfn) == 0)) {
 201                         return -1;
 202                 }
 203
 204                 /* Clear status register bits. */
 205                 MSC_WRITE(MSC01_PCI_INTSTAT,
 206                           (MSC01_PCI_INTCFG_MA_BIT |
 207                            MSC01_PCI_INTCFG_TA_BIT));
 208
 209                 /* Setup address */
 210                 if (busnum == 0)
 211                         type = 0;       /* Type 0 */
 212                 else
 213                         type = 1;       /* Type 1 */
 214
 215                 MSC_WRITE(MSC01_PCI_CFGADDR,
 216                           ((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) |
 217                            (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF)
 218                            | (PCI_FUNC(devfn) <<
 219                               MSC01_PCI_CFGADDR_FNUM_SHF) | ((where /
 220                                                               4) <<
 221                                                              MSC01_PCI_CFGADDR_RNUM_SHF)
 222                            | (type)));
 223
 224                 /* Perform access */
 225                 if (access_type == PCI_ACCESS_WRITE) {
 226                         MSC_WRITE(MSC01_PCI_CFGDATA, *data);
 227                 } else {
 228                         MSC_READ(MSC01_PCI_CFGDATA, *data);
 229                 }
 230
 231                 /* Detect Master/Target abort */
 232                 MSC_READ(MSC01_PCI_INTSTAT, intr);
 233                 if (intr & (MSC01_PCI_INTCFG_MA_BIT |
 234                             MSC01_PCI_INTCFG_TA_BIT)) {
 235                         /* Error occurred */
 236
 237                         /* Clear bits */
 238                         MSC_READ(MSC01_PCI_INTSTAT, intr);
 239                         MSC_WRITE(MSC01_PCI_INTSTAT,
 240                                   (MSC01_PCI_INTCFG_MA_BIT |
 241                                    MSC01_PCI_INTCFG_TA_BIT));
 242
 243                         return -1;
 244                 }
 245                 break;
 246         default:
 247                 printk
 248                     ("Unknown Core card, don't know the system controller.\n");
 249                 return -1;
 250         }
 251
 252         return 0;
 253 }
 254
 255
 256 /*
 257  * We can't address 8 and 16 bit words directly.  Instead we have to
 258  * read/write a 32bit word and mask/modify the data we actually want.
 259  */
 260 static int mips_pcibios_read(struct pci_bus *bus, unsigned int devfn,
 261                              int where, int size, u32 * val)
 262 {
 263         u32 data = 0;
 264
 265         if ((size == 2) && (where & 1))
 266                 return PCIBIOS_BAD_REGISTER_NUMBER;
 267         else if ((size == 4) && (where & 3))
 268                 return PCIBIOS_BAD_REGISTER_NUMBER;
 269
 270         if (mips_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
 271                                        &data))
 272                 return -1;
 273
 274         if (size == 1)
 275                 *val = (data >> ((where & 3) << 3)) & 0xff;
 276         else if (size == 2)
 277                 *val = (data >> ((where & 3) << 3)) & 0xffff;
 278         else
 279                 *val = data;
 280
 281         return PCIBIOS_SUCCESSFUL;
 282 }
 283
 284 static int mips_pcibios_write(struct pci_bus *bus, unsigned int devfn,
 285                               int where, int size, u32 val)
 286 {
 287         u32 data = 0;
 288
 289         if ((size == 2) && (where & 1))
 290                 return PCIBIOS_BAD_REGISTER_NUMBER;
 291         else if ((size == 4) && (where & 3))
 292                 return PCIBIOS_BAD_REGISTER_NUMBER;
 293
 294         if (mips_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
 295                                        &data))
 296                 return -1;
 297
 298         if (size == 1)
 299                 data = (data & ~(0xff << ((where & 3) << 3))) |
 300                     (val << ((where & 3) << 3));
 301         else if (size == 2)
 302                 data = (data & ~(0xffff << ((where & 3) << 3))) |
 303                     (val << ((where & 3) << 3));
 304
 305         if (mips_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where,
 306                                        &data))
 307                 return -1;
 308
 309         return PCIBIOS_SUCCESSFUL;
 310 }
 311
 312 struct pci_ops mips_pci_ops = {
 313         .read = mips_pcibios_read,
 314         .write = mips_pcibios_write
 315 };
 316
 317 int mips_pcibios_iack(void)
 318 {
 319         int irq;
 320         u32 dummy;
 321
 322         /*
 323          * Determine highest priority pending interrupt by performing
 324          * a PCI Interrupt Acknowledge cycle.
 325          */
 326         switch (mips_revision_corid) {
 327         case MIPS_REVISION_CORID_QED_RM5261:
 328         case MIPS_REVISION_CORID_CORE_LV:
 329         case MIPS_REVISION_CORID_CORE_FPGA:
 330         case MIPS_REVISION_CORID_CORE_MSC:
 331                 if (mips_revision_corid == MIPS_REVISION_CORID_CORE_MSC)
 332                         MSC_READ(MSC01_PCI_IACK, irq);
 333                 else
 334                         GT_READ(GT_PCI0_IACK_OFS, irq);
 335                 irq &= 0xff;
 336                 break;
 337         case MIPS_REVISION_CORID_BONITO64:
 338         case MIPS_REVISION_CORID_CORE_20K:
 339                 /* The following will generate a PCI IACK cycle on the
 340                  * Bonito controller. It's a little bit kludgy, but it
 341                  * was the easiest way to implement it in hardware at
 342                  * the given time.
 343                  */
 344                 BONITO_PCIMAP_CFG = 0x20000;
 345
 346                 /* Flush Bonito register block */
 347                 dummy = BONITO_PCIMAP_CFG;
 348                 iob();          /* sync */
 349
 350                 irq = *(volatile u32 *) (KSEG1ADDR(BONITO_PCICFG_BASE));
 351                 iob();          /* sync */
 352                 irq &= 0xff;
 353                 BONITO_PCIMAP_CFG = 0;
 354                 break;
 355         default:
 356                 printk
 357                     ("Unknown Core card, don't know the system controller.\n");
 358                 return -1;
 359         }
 360         return irq;
 361 }
 362
 363 static int __init pcibios_init(void)
 364 {
 365 #ifdef CONFIG_MIPS_MALTA
 366         struct pci_dev *pdev;
 367         unsigned char reg_val;
 368 #endif
 369
 370         printk("PCI: Probing PCI hardware on host bus 0.\n");
 371         pci_scan_bus(0, &mips_pci_ops, NULL);
 372
 373         switch (mips_revision_corid) {
 374         case MIPS_REVISION_CORID_QED_RM5261:
 375         case MIPS_REVISION_CORID_CORE_LV:
 376         case MIPS_REVISION_CORID_CORE_FPGA:
 377                 /*
 378                  * Due to a bug in the Galileo system controller, we need
 379                  * to setup the PCI BAR for the Galileo internal registers.
 380                  * This should be done in the bios/bootprom and will be
 381                  * fixed in a later revision of YAMON (the MIPS boards
 382                  * boot prom).
 383                  */
 384                 GT_WRITE(GT_PCI0_CFGADDR_OFS, (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |       /* Local bus */
 385                          (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) |    /* GT64120 dev */
 386                          (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |  /* Function 0 */
 387                          ((0x20 / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |   /* BAR 4 */
 388                          GT_PCI0_CFGADDR_CONFIGEN_BIT);
 389
 390                 /* Perform the write */
 391                 GT_WRITE(GT_PCI0_CFGDATA_OFS, PHYSADDR(MIPS_GT_BASE));
 392                 break;
 393         }
 394
 395 #ifdef CONFIG_MIPS_MALTA
 396         pci_for_each_dev(pdev) {
 397                 if ((pdev->vendor == PCI_VENDOR_ID_INTEL)
 398                     && (pdev->device == PCI_DEVICE_ID_INTEL_82371AB)
 399                     && (PCI_SLOT(pdev->devfn) == 0x0a)) {
 400                         /*
 401                          * IDE Decode enable.
 402                          */
 403                         pci_read_config_byte(pdev, 0x41, &reg_val);
 404                         pci_write_config_byte(pdev, 0x41, reg_val | 0x80);
 405                         pci_read_config_byte(pdev, 0x43, &reg_val);
 406                         pci_write_config_byte(pdev, 0x43, reg_val | 0x80);
 407                 }
 408
 409                 if ((pdev->vendor == PCI_VENDOR_ID_INTEL)
 410                     && (pdev->device == PCI_DEVICE_ID_INTEL_82371AB_0)
 411                     && (PCI_SLOT(pdev->devfn) == 0x0a)) {
 412                         /*
 413                          * Set top of main memory accessible by ISA or DMA
 414                          * devices to 16 Mb.
 415                          */
 416                         pci_read_config_byte(pdev, 0x69, &reg_val);
 417                         pci_write_config_byte(pdev, 0x69, reg_val | 0xf0);
 418                 }
 419         }
 420
 421         /*
 422          * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
 423          * Controller.
 424          * This should be done in the bios/bootprom and will be fixed in
 425          * a later revision of YAMON (the MIPS boards boot prom).
 426          */
 427         /* Entering config state. */
 428         SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
 429
 430         /* Activate floppy controller. */
 431         SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
 432         SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
 433         SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
 434         SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
 435
 436         /* Exit config state. */
 437         SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
 438 #endif
 439
 440         return 0;
 441 }
 442
 443 subsys_initcall(pcibios_init);
 444
 445 int pcibios_enable_device(struct pci_dev *dev, int mask)
 446 {
 447         /* Not needed, since we enable all devices at startup.  */
 448         return 0;
 449 }
 450
 451 void pcibios_align_resource(void *data, struct resource *res,
 452                             unsigned long size, unsigned long align)
 453 {
 454 }
 455
 456 char *__init pcibios_setup(char *str)
 457 {
 458         /* Nothing to do for now.  */
 459
 460         return str;
 461 }
 462
 463 struct pci_fixup pcibios_fixups[] = {
 464         {0}
 465 };
 466
 467 /*
 468  *  Called after each bus is probed, but before its children
 469  *  are examined.
 470  */
 471 void __devinit pcibios_fixup_bus(struct pci_bus *b)
 472 {
 473         pci_read_bridge_bases(b);
 474 }
 475
 476 unsigned int pcibios_assign_all_busses(void)
 477 {
 478         return 1;
 479 }