arch/mips/pci/pci-lasat.c

   1 #include <linux/kernel.h>
   2 #include <linux/init.h>
   3 #include <linux/pci.h>
   4 #include <asm/bootinfo.h>
   5
   6 #include <asm/lasat/lasat.h>
   7 #include <asm/gt64120.h>
   8 #include <asm/nile4.h>
   9
  10 #define PCI_ACCESS_READ  0
  11 #define PCI_ACCESS_WRITE 1
  12
  13 #undef DEBUG_PCI
  14 #ifdef DEBUG_PCI
  15 #define Dprintk(fmt...) printk(fmt)
  16 #else
  17 #define Dprintk(fmt...)
  18 #endif
  19
  20 static int (*lasat_pcibios_config_access) (unsigned char access_type,
  21                                            struct pci_bus * bus,
  22                                            unsigned int devfn, int where,
  23                                            u32 * val);
  24
  25 /*
  26  * Because of an error/peculiarity in the Galileo chip, we need to swap the
  27  * bytes when running bigendian.
  28  */
  29 #define GT_WRITE(ofs, data)  \
  30              *(volatile u32 *)(LASAT_GT_BASE+ofs) = cpu_to_le32(data)
  31 #define GT_READ(ofs, data)   \
  32              data = le32_to_cpu(*(volatile u32 *)(LASAT_GT_BASE+ofs))
  33
  34
  35 static int lasat_pcibios_config_access_100(unsigned char access_type,
  36                                            struct pci_bus *bus,
  37                                            unsigned int devfn, int where,
  38                                            u32 * val)
  39 {
  40         unsigned char busnum = bus->number;
  41         u32 intr;
  42
  43         if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0)))
  44                 return -1;      /* Because of a bug in the Galileo (for slot 31). */
  45
  46         /* Clear cause register bits */
  47         GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
  48                                      GT_INTRCAUSE_TARABORT0_BIT));
  49
  50         /* Setup address */
  51         GT_WRITE(GT_PCI0_CFGADDR_OFS,
  52                  (busnum << GT_PCI0_CFGADDR_BUSNUM_SHF) |
  53                  (devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
  54                  ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
  55                  GT_PCI0_CFGADDR_CONFIGEN_BIT);
  56
  57         if (access_type == PCI_ACCESS_WRITE) {
  58                 GT_WRITE(GT_PCI0_CFGDATA_OFS, *val);
  59         } else {
  60                 GT_READ(GT_PCI0_CFGDATA_OFS, *val);
  61         }
  62
  63         /* Check for master or target abort */
  64         GT_READ(GT_INTRCAUSE_OFS, intr);
  65
  66         if (intr &
  67             (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) {
  68                 /* Error occurred */
  69
  70                 /* Clear bits */
  71                 GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
  72                                              GT_INTRCAUSE_TARABORT0_BIT));
  73
  74                 return -1;
  75         }
  76
  77         return 0;
  78 }
  79
  80 #define LO(reg) (reg / 4)
  81 #define HI(reg) (reg / 4 + 1)
  82
  83 volatile unsigned long *const vrc_pciregs = (void *) Vrc5074_BASE;
  84
  85 static int lasat_pcibios_config_access_200(unsigned char access_type,
  86                                            struct pci_bus *bus,
  87                                            unsigned int devfn, int where,
  88                                            u32 * val)
  89 {
  90         unsigned char busnum = bus->number;
  91         u32 adr, mask, err;
  92
  93         if ((busnum == 0) && (PCI_SLOT(devfn) > 8))
  94                 /* The addressing scheme chosen leaves room for just
  95                  * 8 devices on the first busnum (besides the PCI
  96                  * controller itself) */
  97                 return -1;
  98
  99         if ((busnum == 0) && (devfn == PCI_DEVFN(0, 0))) {
 100                 /* Access controller registers directly */
 101                 if (access_type == PCI_ACCESS_WRITE) {
 102                         vrc_pciregs[(0x200 + where) >> 2] = *val;
 103                 } else {
 104                         *val = vrc_pciregs[(0x200 + where) >> 2];
 105                 }
 106                 return 0;
 107         }
 108
 109         /* Temporarily map PCI Window 1 to config space */
 110         mask = vrc_pciregs[LO(NILE4_PCIINIT1)];
 111         vrc_pciregs[LO(NILE4_PCIINIT1)] =
 112             0x0000001a | (busnum ? 0x200 : 0);
 113
 114         /* Clear PCI Error register. This also clears the Error Type
 115          * bits in the Control register */
 116         vrc_pciregs[LO(NILE4_PCIERR)] = 0;
 117         vrc_pciregs[HI(NILE4_PCIERR)] = 0;
 118
 119         /* Setup address */
 120         if (busnum == 0)
 121                 adr =
 122                     KSEG1ADDR(PCI_WINDOW1) +
 123                     ((1 << (PCI_SLOT(devfn) + 15)) | (PCI_FUNC(devfn) << 8)
 124                      | (where & ~3));
 125         else
 126                 adr =
 127                     KSEG1ADDR(PCI_WINDOW1) | (busnum << 16) | (devfn << 8)
 128                     | (where & ~3);
 129
 130 #ifdef DEBUG_PCI
 131         printk("PCI config %s: adr %x",
 132                access_type == PCI_ACCESS_WRITE ? "write" : "read", adr);
 133 #endif
 134
 135         if (access_type == PCI_ACCESS_WRITE) {
 136                 *(u32 *) adr = *val;
 137         } else {
 138                 *val = *(u32 *) adr;
 139         }
 140
 141 #ifdef DEBUG_PCI
 142         printk(" value = %x\n", *val);
 143 #endif
 144
 145         /* Check for master or target abort */
 146         err = (vrc_pciregs[HI(NILE4_PCICTRL)] >> 5) & 0x7;
 147
 148         /* Restore PCI Window 1 */
 149         vrc_pciregs[LO(NILE4_PCIINIT1)] = mask;
 150
 151         if (err) {
 152                 /* Error occured */
 153 #ifdef DEBUG_PCI
 154                 printk("\terror %x at adr %x\n", err,
 155                        vrc_pciregs[LO(PCIERR)]);
 156 #endif
 157                 return -1;
 158         }
 159
 160         return 0;
 161 }
 162
 163 static int lasat_pcibios_read(struct pci_bus *bus, unsigned int devfn,
 164                               int where, int size, u32 * val)
 165 {
 166         u32 data = 0;
 167
 168         if ((size == 2) && (where & 1))
 169                 return PCIBIOS_BAD_REGISTER_NUMBER;
 170         else if ((size == 4) && (where & 3))
 171                 return PCIBIOS_BAD_REGISTER_NUMBER;
 172
 173         if (lasat_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
 174                                         &data))
 175                 return -1;
 176
 177         if (size == 1)
 178                 *val = (data >> ((where & 3) << 3)) & 0xff;
 179         else if (size == 2)
 180                 *val = (data >> ((where & 3) << 3)) & 0xffff;
 181         else
 182                 *val = data;
 183
 184         return PCIBIOS_SUCCESSFUL;
 185 }
 186
 187 static int lasat_pcibios_write(struct pci_bus *bus, unsigned int devfn,
 188                                int where, int size, u32 val)
 189 {
 190         u32 data = 0;
 191
 192         if ((size == 2) && (where & 1))
 193                 return PCIBIOS_BAD_REGISTER_NUMBER;
 194         else if ((size == 4) && (where & 3))
 195                 return PCIBIOS_BAD_REGISTER_NUMBER;
 196
 197         if (lasat_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
 198                                         &data))
 199                 return -1;
 200
 201         if (size == 1)
 202                 data = (data & ~(0xff << ((where & 3) << 3))) |
 203                     (val << ((where & 3) << 3));
 204         else if (size == 2)
 205                 data = (data & ~(0xffff << ((where & 3) << 3))) |
 206                     (val << ((where & 3) << 3));
 207
 208         if (lasat_pcibios_config_access
 209             (PCI_ACCESS_WRITE, bus, devfn, where, &data))
 210                 return -1;
 211
 212         return PCIBIOS_SUCCESSFUL;
 213 }
 214
 215 struct pci_ops lasat_pci_ops = {
 216         .read = lasat_pcibios_read,
 217         .write = lasat_pcibios_write,
 218 };
 219
 220 char *__init pcibios_setup(char *str)
 221 {
 222         return str;
 223 }
 224
 225 static int __init pcibios_init(void)
 226 {
 227         switch (mips_machtype) {
 228         case MACH_LASAT_100:
 229                 lasat_pcibios_config_access =
 230                     &lasat_pcibios_config_access_100;
 231                 break;
 232         case MACH_LASAT_200:
 233                 lasat_pcibios_config_access =
 234                     &lasat_pcibios_config_access_200;
 235                 break;
 236         default:
 237                 panic("pcibios_init: mips_machtype incorrect");
 238         }
 239
 240         Dprintk("pcibios_init()\n");
 241         pci_scan_bus(0, &lasat_pci_ops, NULL);
 242         return 0;
 243 }
 244
 245 subsys_initcall(pcibios_init);
 246
 247 void __init pcibios_fixup_bus(struct pci_bus *b)
 248 {
 249         Dprintk("pcibios_fixup_bus()\n");
 250 }
 251
 252 int __init pcibios_enable_device(struct pci_dev *dev, int mask)
 253 {
 254         /* Not needed, since we enable all devices at startup.  */
 255         return 0;
 256 }
 257
 258 void __init pcibios_align_resource(void *data, struct resource *res,
 259                                    unsigned long size, unsigned long align)
 260 {
 261 }
 262
 263 unsigned __init int pcibios_assign_all_busses(void)
 264 {
 265         return 1;
 266 }
 267
 268 struct pci_fixup pcibios_fixups[] = {
 269         {0}
 270 };