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Feed the mess through indent.
[linux-2.6/linux-mips.git] / arch / mips / pci / pci-ip32.c
blobe85c3ea4bc057c3c137f77a02248777c379380bb
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000, 2001 Keith M Wesolowski
7 */
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/types.h>
12 #include <asm/pci.h>
13 #include <asm/ip32/mace.h>
14 #include <asm/ip32/crime.h>
15 #include <asm/ip32/ip32_ints.h>
16 #include <linux/delay.h>
17
18 #undef DEBUG_MACE_PCI
19
20 /*
21 * O2 has up to 5 PCI devices connected into the MACE bridge. The device
22 * map looks like this:
23 *
24 * 0 aic7xxx 0
25 * 1 aic7xxx 1
26 * 2 expansion slot
27 * 3 N/C
28 * 4 N/C
29 */
30
31 #define chkslot(_bus,_devfn) \
32 do { \
33 if ((_bus)->number > 0 || PCI_SLOT (_devfn) < 1 \
34 || PCI_SLOT (_devfn) > 3) \
35 return PCIBIOS_DEVICE_NOT_FOUND; \
36 } while (0)
37
38 #define mkaddr(_devfn, where) \
39 ((((_devfn) & 0xffUL) << 8) | ((where) & 0xfcUL))
40
41 void macepci_error(int irq, void *dev, struct pt_regs *regs);
42
43 static int macepci_read_config(struct pci_bus *bus, unsigned int devfn,
44 int where, int size, u32 * val)
45 {
46 switch (size) {
47 case 1:
48 *val = 0xff;
49 chkslot(bus, devfn);
50 mace_write_32(MACEPCI_CONFIG_ADDR, mkaddr(devfn, where));
51 *val =
52 mace_read_8(MACEPCI_CONFIG_DATA +
53 ((where & 3UL) ^ 3UL));
54
55 return PCIBIOS_SUCCESSFUL;
56
57 case 2:
58 *val = 0xffff;
59 chkslot(bus, devfn);
60 if (where & 1)
61 return PCIBIOS_BAD_REGISTER_NUMBER;
62 mace_write_32(MACEPCI_CONFIG_ADDR, mkaddr(devfn, where));
63 *val =
64 mace_read_16(MACEPCI_CONFIG_DATA +
65 ((where & 2UL) ^ 2UL));
66
67 return PCIBIOS_SUCCESSFUL;
68
69 case 4:
70 *val = 0xffffffff;
71 chkslot(bus, devfn);
72 if (where & 3)
73 return PCIBIOS_BAD_REGISTER_NUMBER;
74 mace_write_32(MACEPCI_CONFIG_ADDR, mkaddr(devfn, where));
75 *val = mace_read_32(MACEPCI_CONFIG_DATA);
76
77 return PCIBIOS_SUCCESSFUL;
78 }
79 }
80
81 static int macepci_write_config(struct pci_bus *bus, unsigned int devfn,
82 int where, int size, u32 val)
83 {
84 switch (size) {
85 case 1:
86 chkslot(bus, devfn);
87 mace_write_32(MACEPCI_CONFIG_ADDR, mkaddr(devfn, where));
88 mace_write_8(MACEPCI_CONFIG_DATA + ((where & 3UL) ^ 3UL),
89 val);
90
91 return PCIBIOS_SUCCESSFUL;
92
93 case 2:
94 chkslot(bus, devfn);
95 if (where & 1)
96 return PCIBIOS_BAD_REGISTER_NUMBER;
97 mace_write_32(MACEPCI_CONFIG_ADDR, mkaddr(devfn, where));
98 mace_write_16(MACEPCI_CONFIG_DATA + ((where & 2UL) ^ 2UL),
99 val);
100
101 return PCIBIOS_SUCCESSFUL;
102
103 case 4:
104 chkslot(bus, devfn);
105 if (where & 3)
106 return PCIBIOS_BAD_REGISTER_NUMBER;
107 mace_write_32(MACEPCI_CONFIG_ADDR, mkaddr(devfn, where));
108 mace_write_32(MACEPCI_CONFIG_DATA, val);
109
110 return PCIBIOS_SUCCESSFUL;
111 }
112 }
113
114 static struct pci_ops macepci_ops = {
115 .read = macepci_read_config,
116 .write = macepci_write_config,
117 };
118
119 struct pci_fixup pcibios_fixups[] = { {0} };
120
121 static int __init pcibios_init(void)
122 {
123 struct pci_dev *dev;
124 u32 start, size;
125 u16 cmd;
126 u32 base_io = 0x3000; /* The first i/o address to assign after SCSI */
127 u32 base_mem = 0x80100000; /* Likewise */
128 u32 rev = mace_read_32(MACEPCI_REV);
129 int i;
130
131 printk("MACE: PCI rev %d detected at %016lx\n", rev,
132 (u64) MACE_BASE + MACE_PCI);
133
134 /* These are *bus* addresses */
135 ioport_resource.start = 0;
136 ioport_resource.end = 0xffffffffUL;
137 iomem_resource.start = 0x80000000UL;
138 iomem_resource.end = 0xffffffffUL;
139
140 /* Clear any outstanding errors and enable interrupts */
141 mace_write_32(MACEPCI_ERROR_ADDR, 0);
142 mace_write_32(MACEPCI_ERROR_FLAGS, 0);
143 mace_write_32(MACEPCI_CONTROL, 0xff008500);
144 crime_write_64(CRIME_HARD_INT, 0UL);
145 crime_write_64(CRIME_SOFT_INT, 0UL);
146 crime_write_64(CRIME_INT_STAT, 0x000000000000ff00UL);
147
148 if (request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0,
149 "MACE PCI error", NULL))
150 panic("PCI bridge can't get interrupt; can't happen.");
151
152 pci_scan_bus(0, &macepci_ops, NULL);
153
154 #ifdef DEBUG_MACE_PCI
155 pci_for_each_dev(dev) {
156 printk("Device: %d/%d/%d ARCS-assigned bus resource map\n",
157 dev->bus->number, PCI_SLOT(dev->devfn),
158 PCI_FUNC(dev->devfn));
159 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
160 if (dev->resource[i].start == 0)
161 continue;
162 printk("%d: %016lx - %016lx (flags %04lx)\n",
163 i, dev->resource[i].start,
164 dev->resource[i].end,
165 dev->resource[i].flags);
166 }
167 }
168 #endif
169 /*
170 * Assign sane resources to and enable all devices. The requirement
171 * for the SCSI controllers is well-known: a 256-byte I/O region
172 * which we must assign, and a 1-page memory region which is
173 * assigned by the system firmware.
174 */
175 pci_for_each_dev(dev) {
176 switch (PCI_SLOT(dev->devfn)) {
177 case 1: /* SCSI bus 0 */
178 dev->resource[0].start = 0x1000UL;
179 dev->resource[0].end = 0x10ffUL;
180 break;
181 case 2: /* SCSI bus 1 */
182 dev->resource[0].start = 0x2000UL;
183 dev->resource[0].end = 0x20ffUL;
184 break;
185 default: /* Slots - I guess we have only 1 */
186 for (i = 0; i < 6; i++) {
187 size = dev->resource[i].end
188 - dev->resource[i].start;
189 if (!size
190 || !(dev->resource[i].flags
191 & (IORESOURCE_IO |
192 IORESOURCE_MEM))) {
193 dev->resource[i].start =
194 dev->resource[i].end = 0UL;
195 continue;
196 }
197 if (dev->resource[i].flags & IORESOURCE_IO) {
198 dev->resource[i].start = base_io;
199 base_io += PAGE_ALIGN(size);
200 } else {
201 dev->resource[i].start = base_mem;
202 base_mem += 0x100000UL;
203 }
204 dev->resource[i].end =
205 dev->resource[i].start + size;
206 }
207 break;
208 }
209 for (i = 0; i < 6; i++) {
210 if (dev->resource[i].start == 0)
211 continue;
212 start = dev->resource[i].start;
213 if (dev->resource[i].flags & IORESOURCE_IO)
214 start |= 1;
215 pci_write_config_dword(dev,
216 PCI_BASE_ADDRESS_0 +
217 (i << 2), (u32) start);
218 }
219 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x20);
220 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x30);
221 pci_read_config_word(dev, PCI_COMMAND, &cmd);
222 cmd |=
223 (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
224 PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
225 PCI_COMMAND_PARITY);
226 pci_write_config_word(dev, PCI_COMMAND, cmd);
227 pci_set_master(dev);
228 }
229 /*
230 * Fixup O2 PCI slot. Bad hack.
231 */
232 /* devtag = pci_make_tag(0, 0, 3, 0);
233
234 slot = macepci_conf_read(0, devtag, PCI_COMMAND_STATUS_REG);
235 slot |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE;
236 macepci_conf_write(0, devtag, PCI_COMMAND_STATUS_REG, slot);
237
238 slot = macepci_conf_read(0, devtag, PCI_MAPREG_START);
239 if (slot == 0xffffffe1)
240 macepci_conf_write(0, devtag, PCI_MAPREG_START, 0x00001000);
241
242 slot = macepci_conf_read(0, devtag, PCI_MAPREG_START + (2 << 2));
243 if ((slot & 0xffff0000) == 0) {
244 slot += 0x00010000;
245 macepci_conf_write(0, devtag, PCI_MAPREG_START + (2 << 2),
246 0x00000000);
247 }
248 */
249 #ifdef DEBUG_MACE_PCI
250 printk("Triggering PCI bridge interrupt...\n");
251 mace_write_32(MACEPCI_ERROR_FLAGS, MACEPCI_ERROR_INTERRUPT_TEST);
252
253 pci_for_each_dev(dev) {
254 printk("Device: %d/%d/%d final bus resource map\n",
255 dev->bus->number, PCI_SLOT(dev->devfn),
256 PCI_FUNC(dev->devfn));
257 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
258 if (dev->resource[i].start == 0)
259 continue;
260 printk("%d: %016lx - %016lx (flags %04lx)\n",
261 i, dev->resource[i].start,
262 dev->resource[i].end,
263 dev->resource[i].flags);
264 }
265 }
266 #endif
267
268 return 0;
269 }
270
271 subsys_initcall(pcibios_init);
272
273 /*
274 * Given a PCI slot number (a la PCI_SLOT(...)) and the interrupt pin of
275 * the device (1-4 => A-D), tell what irq to use. Note that we don't
276 * in theory have slots 4 and 5, and we never normally use the shared
277 * irqs. I suppose a device without a pin A will thank us for doing it
278 * right if there exists such a broken piece of crap.
279 */
280 static int __devinit macepci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
281 {
282 chkslot(dev->bus, dev->devfn);
283 if (pin == 0)
284 pin = 1;
285 switch (slot) {
286 case 1:
287 return MACEPCI_SCSI0_IRQ;
288 case 2:
289 return MACEPCI_SCSI1_IRQ;
290 case 3:
291 switch (pin) {
292 case 2:
293 return MACEPCI_SHARED0_IRQ;
294 case 3:
295 return MACEPCI_SHARED1_IRQ;
296 case 4:
297 return MACEPCI_SHARED2_IRQ;
298 case 1:
299 default:
300 return MACEPCI_SLOT0_IRQ;
301 }
302 case 4:
303 switch (pin) {
304 case 2:
305 return MACEPCI_SHARED2_IRQ;
306 case 3:
307 return MACEPCI_SHARED0_IRQ;
308 case 4:
309 return MACEPCI_SHARED1_IRQ;
310 case 1:
311 default:
312 return MACEPCI_SLOT1_IRQ;
313 }
314 return MACEPCI_SLOT1_IRQ;
315 case 5:
316 switch (pin) {
317 case 2:
318 return MACEPCI_SHARED1_IRQ;
319 case 3:
320 return MACEPCI_SHARED2_IRQ;
321 case 4:
322 return MACEPCI_SHARED0_IRQ;
323 case 1:
324 default:
325 return MACEPCI_SLOT2_IRQ;
326 }
327 default:
328 return 0;
329 }
330 }
331
332 /*
333 * It's not entirely clear what this does in a system with no bridges.
334 * In any case, bridges are not supported by Linux in O2.
335 */
336 static u8 __init macepci_swizzle(struct pci_dev *dev, u8 * pinp)
337 {
338 if (PCI_SLOT(dev->devfn) == 2)
339 *pinp = 2;
340 else
341 *pinp = 1;
342 return PCI_SLOT(dev->devfn);
343 }
344
345 /* All devices are enabled during initialization. */
346 int pcibios_enable_device(struct pci_dev *dev, int mask)
347 {
348 return PCIBIOS_SUCCESSFUL;
349 }
350
351 char *__init pcibios_setup(char *str)
352 {
353 return str;
354 }
355
356 void pcibios_align_resource(void *data, struct resource *res,
357 unsigned long size, unsigned long align)
358 {
359 }
360
361 void __init pcibios_update_irq(struct pci_dev *dev, int irq)
362 {
363 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
364 }
365
366 void __devinit pcibios_fixup_bus(struct pci_bus *b)
367 {
368 pci_fixup_irqs(macepci_swizzle, macepci_map_irq);
369 }
370
371 /*
372 * Handle errors from the bridge. This includes master and target aborts,
373 * various command and address errors, and the interrupt test. This gets
374 * registered on the bridge error irq. It's conceivable that some of these
375 * conditions warrant a panic. Anybody care to say which ones?
376 */
377 void macepci_error(int irq, void *dev, struct pt_regs *regs)
378 {
379 u32 flags, error_addr;
380 char space;
381
382 flags = mace_read_32(MACEPCI_ERROR_FLAGS);
383 error_addr = mace_read_32(MACEPCI_ERROR_ADDR);
384
385 if (flags & MACEPCI_ERROR_MEMORY_ADDR)
386 space = 'M';
387 else if (flags & MACEPCI_ERROR_CONFIG_ADDR)
388 space = 'C';
389 else
390 space = 'X';
391
392 if (flags & MACEPCI_ERROR_MASTER_ABORT) {
393 printk("MACEPCI: Master abort at 0x%08x (%c)\n",
394 error_addr, space);
395 mace_write_32(MACEPCI_ERROR_FLAGS,
396 flags & ~MACEPCI_ERROR_MASTER_ABORT);
397 }
398 if (flags & MACEPCI_ERROR_TARGET_ABORT) {
399 printk("MACEPCI: Target abort at 0x%08x (%c)\n",
400 error_addr, space);
401 mace_write_32(MACEPCI_ERROR_FLAGS,
402 flags & ~MACEPCI_ERROR_TARGET_ABORT);
403 }
404 if (flags & MACEPCI_ERROR_DATA_PARITY_ERR) {
405 printk("MACEPCI: Data parity error at 0x%08x (%c)\n",
406 error_addr, space);
407 mace_write_32(MACEPCI_ERROR_FLAGS, flags
408 & ~MACEPCI_ERROR_DATA_PARITY_ERR);
409 }
410 if (flags & MACEPCI_ERROR_RETRY_ERR) {
411 printk("MACEPCI: Retry error at 0x%08x (%c)\n", error_addr,
412 space);
413 mace_write_32(MACEPCI_ERROR_FLAGS, flags
414 & ~MACEPCI_ERROR_RETRY_ERR);
415 }
416 if (flags & MACEPCI_ERROR_ILLEGAL_CMD) {
417 printk("MACEPCI: Illegal command at 0x%08x (%c)\n",
418 error_addr, space);
419 mace_write_32(MACEPCI_ERROR_FLAGS,
420 flags & ~MACEPCI_ERROR_ILLEGAL_CMD);
421 }
422 if (flags & MACEPCI_ERROR_SYSTEM_ERR) {
423 printk("MACEPCI: System error at 0x%08x (%c)\n",
424 error_addr, space);
425 mace_write_32(MACEPCI_ERROR_FLAGS, flags
426 & ~MACEPCI_ERROR_SYSTEM_ERR);
427 }
428 if (flags & MACEPCI_ERROR_PARITY_ERR) {
429 printk("MACEPCI: Parity error at 0x%08x (%c)\n",
430 error_addr, space);
431 mace_write_32(MACEPCI_ERROR_FLAGS,
432 flags & ~MACEPCI_ERROR_PARITY_ERR);
433 }
434 if (flags & MACEPCI_ERROR_OVERRUN) {
435 printk("MACEPCI: Overrun error at 0x%08x (%c)\n",
436 error_addr, space);
437 mace_write_32(MACEPCI_ERROR_FLAGS, flags
438 & ~MACEPCI_ERROR_OVERRUN);
439 }
440 if (flags & MACEPCI_ERROR_SIG_TABORT) {
441 printk("MACEPCI: Signaled target abort (clearing)\n");
442 mace_write_32(MACEPCI_ERROR_FLAGS, flags
443 & ~MACEPCI_ERROR_SIG_TABORT);
444 }
445 if (flags & MACEPCI_ERROR_INTERRUPT_TEST) {
446 printk("MACEPCI: Interrupt test triggered (clearing)\n");
447 mace_write_32(MACEPCI_ERROR_FLAGS, flags
448 & ~MACEPCI_ERROR_INTERRUPT_TEST);
449 }
450 }
451
452 unsigned int pcibios_assign_all_busses(void)
453 {
454 return 0;
455 }
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