arch/mips/pci/pci-ddb5476.c

   1 #include <linux/config.h>
   2 #include <linux/kernel.h>
   3 #include <linux/init.h>
   4 #include <linux/types.h>
   5 #include <linux/pci.h>
   6
   7 #include <asm/pci_channel.h>
   8 #include <asm/debug.h>
   9
  10 #include <asm/ddb5xxx/ddb5xxx.h>
  11
  12 static struct resource extpci_io_resource = {
  13         "pci IO space",
  14         0x1000,                 /* leave some room for ISA bus */
  15         DDB_PCI_IO_SIZE - 1,
  16         IORESOURCE_IO
  17 };
  18
  19 static struct resource extpci_mem_resource = {
  20         "pci memory space",
  21         DDB_PCI_MEM_BASE + 0x00100000,  /* leave 1 MB for RTC */
  22         DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1,
  23         IORESOURCE_MEM
  24 };
  25
  26 extern struct pci_ops ddb5476_ext_pci_ops;
  27
  28 struct pci_channel mips_pci_channels[] = {
  29         {&ddb5476_ext_pci_ops, &extpci_io_resource, &extpci_mem_resource},
  30         {NULL, NULL, NULL}
  31 };
  32
  33
  34 /*
  35  * we fix up irqs based on the slot number.
  36  * The first entry is at AD:11.
  37  *
  38  * This does not work for devices on sub-buses yet.
  39  */
  40
  41 /*
  42  * temporary
  43  */
  44
  45 #define         PCI_EXT_INTA            8
  46 #define         PCI_EXT_INTB            9
  47 #define         PCI_EXT_INTC            10
  48 #define         PCI_EXT_INTD            11
  49 #define         PCI_EXT_INTE            12
  50
  51 /*
  52  * based on ddb5477 manual page 11
  53  */
  54 #define         MAX_SLOT_NUM            21
  55 static unsigned char irq_map[MAX_SLOT_NUM] = {
  56         /* SLOT:  0, AD:11 */ 0xff,
  57         /* SLOT:  1, AD:12 */ 0xff,
  58                                         /* SLOT:  2, AD:13 */ 9,
  59                                         /* USB */
  60                                         /* SLOT:  3, AD:14 */ 10,
  61                                         /* PMU */
  62         /* SLOT:  4, AD:15 */ 0xff,
  63                                         /* SLOT:  5, AD:16 */ 0x0,
  64                                         /* P2P bridge */
  65         /* SLOT:  6, AD:17 */ nile4_to_irq(PCI_EXT_INTB),
  66         /* SLOT:  7, AD:18 */ nile4_to_irq(PCI_EXT_INTC),
  67         /* SLOT:  8, AD:19 */ nile4_to_irq(PCI_EXT_INTD),
  68         /* SLOT:  9, AD:20 */ nile4_to_irq(PCI_EXT_INTA),
  69         /* SLOT: 10, AD:21 */ 0xff,
  70         /* SLOT: 11, AD:22 */ 0xff,
  71         /* SLOT: 12, AD:23 */ 0xff,
  72                                         /* SLOT: 13, AD:24 */ 14,
  73                                         /* HD controller, M5229 */
  74         /* SLOT: 14, AD:25 */ 0xff,
  75         /* SLOT: 15, AD:26 */ 0xff,
  76         /* SLOT: 16, AD:27 */ 0xff,
  77         /* SLOT: 17, AD:28 */ 0xff,
  78         /* SLOT: 18, AD:29 */ 0xff,
  79         /* SLOT: 19, AD:30 */ 0xff,
  80         /* SLOT: 20, AD:31 */ 0xff
  81 };
  82
  83 extern int vrc5477_irq_to_irq(int irq);
  84 void __init pcibios_fixup_irqs(void)
  85 {
  86         struct pci_dev *dev;
  87         int slot_num;
  88
  89         pci_for_each_dev(dev) {
  90                 slot_num = PCI_SLOT(dev->devfn);
  91
  92                 /* we don't do IRQ fixup for sub-bus yet */
  93                 if (dev->bus->parent != NULL) {
  94                         db_run(printk
  95                                ("Don't know how to fixup irq for PCI device %d on sub-bus %d\n",
  96                                 slot_num, dev->bus->number));
  97                         continue;
  98                 }
  99
 100                 db_assert(slot_num < MAX_SLOT_NUM);
 101                 db_assert(irq_map[slot_num] != 0xff);
 102
 103                 pci_write_config_byte(dev,
 104                                       PCI_INTERRUPT_LINE,
 105                                       irq_map[slot_num]);
 106                 dev->irq = irq_map[slot_num];
 107         }
 108 }
 109
 110 #if defined(CONFIG_RUNTIME_DEBUG)
 111 extern void jsun_scan_pci_bus(void);
 112 #endif
 113
 114 void __init ddb_pci_reset_bus(void)
 115 {
 116         u32 temp;
 117
 118         /*
 119          * I am not sure about the "official" procedure, the following
 120          * steps work as far as I know:
 121          * We first set PCI cold reset bit (bit 31) in PCICTRL-H.
 122          * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
 123          * The same is true for both PCI channels.
 124          */
 125         temp = ddb_in32(DDB_PCICTRL + 4);
 126         temp |= 0x80000000;
 127         ddb_out32(DDB_PCICTRL + 4, temp);
 128         temp &= ~0xc0000000;
 129         ddb_out32(DDB_PCICTRL + 4, temp);
 130
 131 }
 132
 133 unsigned __init int pcibios_assign_all_busses(void)
 134 {
 135         /* we hope pci_auto has assigned the bus numbers to all buses */
 136         return 1;
 137 }
 138
 139 void __init pcibios_fixup_resources(struct pci_dev *dev)
 140 {
 141 }
 142
 143 void __init pcibios_fixup(void)
 144 {
 145 }