arch/mips/pci/pci-ddb5074.c

   1 #include <linux/kernel.h>
   2 #include <linux/init.h>
   3 #include <linux/types.h>
   4 #include <linux/pci.h>
   5
   6 #include <asm/pci_channel.h>
   7 #include <asm/debug.h>
   8
   9 #include <asm/ddb5xxx/ddb5xxx.h>
  10
  11 static struct resource extpci_io_resource = {
  12         "pci IO space",
  13         0x1000,                 /* leave some room for ISA bus */
  14         DDB_PCI_IO_SIZE - 1,
  15         IORESOURCE_IO
  16 };
  17
  18 static struct resource extpci_mem_resource = {
  19         "pci memory space",
  20         DDB_PCI_MEM_BASE + 0x00100000,  /* leave 1 MB for RTC */
  21         DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1,
  22         IORESOURCE_MEM
  23 };
  24
  25 extern struct pci_ops ddb5476_ext_pci_ops;
  26
  27 struct pci_channel mips_pci_channels[] = {
  28         {&ddb5476_ext_pci_ops, &extpci_io_resource, &extpci_mem_resource},
  29         {NULL, NULL, NULL}
  30 };
  31
  32 #define     PCI_EXT_INTA        8
  33 #define     PCI_EXT_INTB        9
  34 #define     PCI_EXT_INTC        10
  35 #define     PCI_EXT_INTD        11
  36 #define     PCI_EXT_INTE        12
  37
  38 #define     MAX_SLOT_NUM        14
  39
  40 static unsigned char irq_map[MAX_SLOT_NUM] = {
  41         /* SLOT:  0 */ nile4_to_irq(PCI_EXT_INTE),
  42         /* SLOT:  1 */ nile4_to_irq(PCI_EXT_INTA),
  43         /* SLOT:  2 */ nile4_to_irq(PCI_EXT_INTA),
  44         /* SLOT:  3 */ nile4_to_irq(PCI_EXT_INTB),
  45         /* SLOT:  4 */ nile4_to_irq(PCI_EXT_INTC),
  46         /* SLOT:  5 */ nile4_to_irq(NILE4_INT_UART),
  47         /* SLOT:  6 */ 0xff,
  48         /* SLOT:  7 */ 0xff,
  49         /* SLOT:  8 */ 0xff,
  50         /* SLOT:  9 */ 0xff,
  51         /* SLOT:  10 */ nile4_to_irq(PCI_EXT_INTE),
  52         /* SLOT:  11 */ 0xff,
  53         /* SLOT:  12 */ 0xff,
  54         /* SLOT:  13 */ nile4_to_irq(PCI_EXT_INTE),
  55 };
  56
  57 void __init pcibios_fixup_irqs(void)
  58 {
  59
  60         struct pci_dev *dev;
  61         int slot_num;
  62
  63         pci_for_each_dev(dev) {
  64                 slot_num = PCI_SLOT(dev->devfn);
  65                 db_assert(slot_num < MAX_SLOT_NUM);
  66                 printk("irq_map[%d]: %02x\n", slot_num, irq_map[slot_num]);
  67                 db_assert(irq_map[slot_num] != 0xff);
  68
  69                 pci_write_config_byte(dev,
  70                                       PCI_INTERRUPT_LINE,
  71                                       irq_map[slot_num]);
  72
  73                 dev->irq = irq_map[slot_num];
  74         }
  75 }
  76
  77 void __init ddb_pci_reset_bus(void)
  78 {
  79         u32 temp;
  80
  81         /*
  82          * I am not sure about the "official" procedure, the following
  83          * steps work as far as I know:
  84          * We first set PCI cold reset bit (bit 31) in PCICTRL-H.
  85          * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
  86          * The same is true for both PCI channels.
  87          */
  88         temp = ddb_in32(DDB_PCICTRL + 4);
  89         temp |= 0x80000000;
  90         ddb_out32(DDB_PCICTRL + 4, temp);
  91         temp &= ~0xc0000000;
  92         ddb_out32(DDB_PCICTRL + 4, temp);
  93
  94 }
  95
  96 unsigned __init int pcibios_assign_all_busses(void)
  97 {
  98         /* we hope pci_auto has assigned the bus numbers to all buses */
  99         return 1;
 100 }
 101
 102 void __init pcibios_fixup_resources(struct pci_dev *dev)
 103 {
 104 }
 105
 106 void __init pcibios_fixup(void)
 107 {
 108         struct pci_dev *dev;
 109
 110         pci_for_each_dev(dev) {
 111                 if (dev->vendor == PCI_VENDOR_ID_AL &&
 112                     dev->device == PCI_DEVICE_ID_AL_M7101) {
 113                         /*
 114                          * It's nice to have the LEDs on the GPIO pins
 115                          * available for debugging
 116                          */
 117                         extern struct pci_dev *pci_pmu;
 118                         u8 t8;
 119
 120                         pci_pmu = dev;  /* for LEDs D2 and D3 */
 121                         /* Program the lines for LEDs D2 and D3 to output */
 122                         pci_read_config_byte(dev, 0x7d, &t8);
 123                         t8 |= 0xc0;
 124                         pci_write_config_byte(dev, 0x7d, t8);
 125                         /* Turn LEDs D2 and D3 off */
 126                         pci_read_config_byte(dev, 0x7e, &t8);
 127                         t8 |= 0xc0;
 128                         pci_write_config_byte(dev, 0x7e, t8);
 129
 130                 }
 131         }
 132 }