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Feed the mess through indent.
[linux-2.6/linux-mips.git] / arch / mips / pci / pci-auto.c
blob1d25569b1fc8867c4d05dca9315e00e374345087
1 /*
2 * PCI autoconfiguration library
3 *
4 * Author: Matt Porter <mporter@mvista.com>
5 *
6 * Copyright 2000, 2001, 2002, 2003 MontaVista Software Inc.
7 * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15 /*
16 * Modified for MIPS by Jun Sun, jsun@mvista.com
17 *
18 * . Simplify the interface between pci_auto and the rest: a single function.
19 * . Assign resources from low address to upper address.
20 * . change most int to u32.
21 *
22 * Further modified to include it as mips generic code, ppopov@mvista.com.
23 *
24 * 2001-10-26 Bradley D. LaRonde <brad@ltc.com>
25 * - Add a top_bus argument to the "early config" functions so that
26 * they can set a fake parent bus pointer to convince the underlying
27 * pci ops to use type 1 configuration for sub busses.
28 * - Set bridge base and limit registers correctly.
29 * - Align io and memory base properly before and after bridge setup.
30 * - Don't fall through to pci_setup_bars for bridge.
31 * - Reformat the debug output to look more like lspci's output.
32 *
33 * 2003-04-09 Yoichi Yuasa, Alice Hennessy, Jun Sun
34 * - Add cardbus bridge support, mostly copied from PPC
35 */
36
37 #include <linux/kernel.h>
38 #include <linux/init.h>
39 #include <linux/types.h>
40 #include <linux/pci.h>
41
42 #include <asm/pci_channel.h>
43
44 #define DEBUG
45 #ifdef DEBUG
46 #define DBG(x...) printk(x)
47 #else
48 #define DBG(x...)
49 #endif
50
51 /*
52 * These functions are used early on before PCI scanning is done
53 * and all of the pci_dev and pci_bus structures have been created.
54 */
55 static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
56 int top_bus, int busnr, int devfn)
57 {
58 static struct pci_dev dev;
59 static struct pci_bus bus;
60
61 dev.bus = &bus;
62 dev.sysdata = hose;
63 dev.devfn = devfn;
64 bus.number = busnr;
65 bus.ops = hose->pci_ops;
66
67 if (busnr != top_bus)
68 /* Fake a parent bus structure. */
69 bus.parent = &bus;
70 else
71 bus.parent = NULL;
72
73 return &dev;
74 }
75
76 #define EARLY_PCI_OP(rw, size, type) \
77 int early_##rw##_config_##size(struct pci_channel *hose, \
78 int top_bus, int bus, int devfn, int offset, type value) \
79 { \
80 return pci_##rw##_config_##size( \
81 fake_pci_dev(hose, top_bus, bus, devfn), \
82 offset, value); \
83 }
84
85 EARLY_PCI_OP(read, byte, u8 *)
86 EARLY_PCI_OP(read, word, u16 *)
87 EARLY_PCI_OP(read, dword, u32 *)
88 EARLY_PCI_OP(write, byte, u8)
89 EARLY_PCI_OP(write, word, u16)
90 EARLY_PCI_OP(write, dword, u32)
91
92 static struct resource *io_resource_inuse;
93 static struct resource *mem_resource_inuse;
94
95 static u32 pciauto_lower_iospc;
96 static u32 pciauto_upper_iospc;
97
98 static u32 pciauto_lower_memspc;
99 static u32 pciauto_upper_memspc;
100
101 void __init
102 pciauto_setup_bars(struct pci_channel *hose,
103 int top_bus,
104 int current_bus, int pci_devfn, int bar_limit)
105 {
106 u32 bar_response, bar_size, bar_value;
107 u32 bar, addr_mask, bar_nr = 0;
108 u32 *upper_limit;
109 u32 *lower_limit;
110 int found_mem64 = 0;
111
112 for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar += 4) {
113 /* Tickle the BAR and get the response */
114 early_write_config_dword(hose, top_bus,
115 current_bus,
116 pci_devfn, bar, 0xffffffff);
117 early_read_config_dword(hose, top_bus,
118 current_bus,
119 pci_devfn, bar, &bar_response);
120
121 /* If BAR is not implemented go to the next BAR */
122 if (!bar_response)
123 continue;
124
125 /*
126 * Workaround for a BAR that doesn't use its upper word,
127 * like the ALi 1535D+ PCI DC-97 Controller Modem (M5457).
128 * bdl <brad@ltc.com>
129 */
130 if (!(bar_response & 0xffff0000))
131 bar_response |= 0xffff0000;
132
133 retry:
134 /* Check the BAR type and set our address mask */
135 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
136 addr_mask = PCI_BASE_ADDRESS_IO_MASK;
137 upper_limit = &pciauto_upper_iospc;
138 lower_limit = &pciauto_lower_iospc;
139 DBG(" I/O");
140 } else {
141 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
142 == PCI_BASE_ADDRESS_MEM_TYPE_64)
143 found_mem64 = 1;
144
145 addr_mask = PCI_BASE_ADDRESS_MEM_MASK;
146 upper_limit = &pciauto_upper_memspc;
147 lower_limit = &pciauto_lower_memspc;
148 DBG(" Mem");
149 }
150
151
152 /* Calculate requested size */
153 bar_size = ~(bar_response & addr_mask) + 1;
154
155 /* Allocate a base address */
156 bar_value =
157 ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size;
158
159 if ((bar_value + bar_size) > *upper_limit) {
160 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
161 if (io_resource_inuse->child) {
162 io_resource_inuse =
163 io_resource_inuse->child;
164 pciauto_lower_iospc =
165 io_resource_inuse->start;
166 pciauto_upper_iospc =
167 io_resource_inuse->end + 1;
168 goto retry;
169 }
170
171 } else {
172 if (mem_resource_inuse->child) {
173 mem_resource_inuse =
174 mem_resource_inuse->child;
175 pciauto_lower_memspc =
176 mem_resource_inuse->start;
177 pciauto_upper_memspc =
178 mem_resource_inuse->end + 1;
179 goto retry;
180 }
181 }
182 DBG(" unavailable -- skipping\n");
183 continue;
184 }
185
186 /* Write it out and update our limit */
187 early_write_config_dword(hose, top_bus, current_bus,
188 pci_devfn, bar, bar_value);
189
190 *lower_limit = bar_value + bar_size;
191
192 /*
193 * If we are a 64-bit decoder then increment to the
194 * upper 32 bits of the bar and force it to locate
195 * in the lower 4GB of memory.
196 */
197 if (found_mem64) {
198 bar += 4;
199 early_write_config_dword(hose, top_bus,
200 current_bus,
201 pci_devfn,
202 bar, 0x00000000);
203 }
204
205 DBG(" at 0x%.8x [size=0x%x]\n", bar_value, bar_size);
206
207 bar_nr++;
208 }
209
210 }
211
212 void __init
213 pciauto_prescan_setup_bridge(struct pci_channel *hose,
214 int top_bus,
215 int current_bus, int pci_devfn, int sub_bus)
216 {
217 /* Configure bus number registers */
218 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
219 PCI_PRIMARY_BUS, current_bus);
220 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
221 PCI_SECONDARY_BUS, sub_bus + 1);
222 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
223 PCI_SUBORDINATE_BUS, 0xff);
224
225 /* Align memory and I/O to 1MB and 4KB boundaries. */
226 pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
227 & ~(0x100000 - 1);
228 pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
229 & ~(0x1000 - 1);
230
231 /* Set base (lower limit) of address range behind bridge. */
232 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
233 PCI_MEMORY_BASE,
234 pciauto_lower_memspc >> 16);
235 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
236 PCI_IO_BASE,
237 (pciauto_lower_iospc & 0x0000f000) >> 8);
238 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
239 PCI_IO_BASE_UPPER16,
240 pciauto_lower_iospc >> 16);
241
242 /* We don't support prefetchable memory for now, so disable */
243 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
244 PCI_PREF_MEMORY_BASE, 0);
245 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
246 PCI_PREF_MEMORY_LIMIT, 0);
247 }
248
249 void __init
250 pciauto_postscan_setup_bridge(struct pci_channel *hose,
251 int top_bus,
252 int current_bus, int pci_devfn, int sub_bus)
253 {
254 u32 temp;
255
256 /*
257 * [jsun] we always bump up baselines a little, so that if there
258 * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
259 * spaces.
260 */
261 pciauto_lower_memspc += 1;
262 pciauto_lower_iospc += 1;
263
264 /* Configure bus number registers */
265 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
266 PCI_SUBORDINATE_BUS, sub_bus);
267
268 /* Set upper limit of address range behind bridge. */
269 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
270 PCI_MEMORY_LIMIT,
271 pciauto_lower_memspc >> 16);
272 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
273 PCI_IO_LIMIT,
274 (pciauto_lower_iospc & 0x0000f000) >> 8);
275 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
276 PCI_IO_LIMIT_UPPER16,
277 pciauto_lower_iospc >> 16);
278
279 /* Align memory and I/O to 1MB and 4KB boundaries. */
280 pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
281 & ~(0x100000 - 1);
282 pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
283 & ~(0x1000 - 1);
284
285 /* Enable memory and I/O accesses, enable bus master */
286 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
287 PCI_COMMAND, &temp);
288 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
289 PCI_COMMAND,
290 temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY
291 | PCI_COMMAND_MASTER);
292 }
293
294 void __init
295 pciauto_prescan_setup_cardbus_bridge(struct pci_channel *hose,
296 int top_bus,
297 int current_bus,
298 int pci_devfn, int sub_bus)
299 {
300 /* Configure bus number registers */
301 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
302 PCI_PRIMARY_BUS, current_bus);
303 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
304 PCI_SECONDARY_BUS, sub_bus + 1);
305 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
306 PCI_SUBORDINATE_BUS, 0xff);
307
308 /* Align memory and I/O to 4KB and 4 byte boundaries. */
309 pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
310 & ~(0x1000 - 1);
311 pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
312 & ~(0x4 - 1);
313
314 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
315 PCI_CB_MEMORY_BASE_0,
316 pciauto_lower_memspc);
317 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
318 PCI_CB_IO_BASE_0, pciauto_lower_iospc);
319 }
320
321 void __init
322 pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose,
323 int top_bus,
324 int current_bus,
325 int pci_devfn, int sub_bus)
326 {
327 u32 temp;
328
329 /*
330 * Configure subordinate bus number. The PCI subsystem
331 * bus scan will renumber buses (reserving three additional
332 * for this PCI<->CardBus bridge for the case where a CardBus
333 * adapter contains a P2P or CB2CB bridge.
334 */
335
336 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
337 PCI_SUBORDINATE_BUS, sub_bus);
338
339 /*
340 * Reserve an additional 4MB for mem space and 16KB for
341 * I/O space. This should cover any additional space
342 * requirement of unusual CardBus devices with
343 * additional bridges that can consume more address space.
344 *
345 * Although pcmcia-cs currently will reprogram bridge
346 * windows, the goal is to add an option to leave them
347 * alone and use the bridge window ranges as the regions
348 * that are searched for free resources upon hot-insertion
349 * of a device. This will allow a PCI<->CardBus bridge
350 * configured by this routine to happily live behind a
351 * P2P bridge in a system.
352 */
353 pciauto_lower_memspc += 0x00400000;
354 pciauto_lower_iospc += 0x00004000;
355
356 /* Align memory and I/O to 4KB and 4 byte boundaries. */
357 pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
358 & ~(0x1000 - 1);
359 pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
360 & ~(0x4 - 1);
361 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
362 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
363 PCI_CB_MEMORY_LIMIT_0,
364 pciauto_lower_memspc - 1);
365 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
366 PCI_CB_IO_LIMIT_0,
367 pciauto_lower_iospc - 1);
368
369 /* Enable memory and I/O accesses, enable bus master */
370 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
371 PCI_COMMAND, &temp);
372 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
373 PCI_COMMAND,
374 temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY
375 | PCI_COMMAND_MASTER);
376 }
377
378 #define PCIAUTO_IDE_MODE_MASK 0x05
379
380 int __init
381 pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
382 {
383 int sub_bus;
384 u32 pci_devfn, pci_class, cmdstat, found_multi = 0;
385 unsigned short vid, did;
386 unsigned char header_type;
387 int devfn_start = 0;
388 int devfn_stop = 0xff;
389
390 sub_bus = current_bus;
391
392 if (hose->first_devfn)
393 devfn_start = hose->first_devfn;
394 if (hose->last_devfn)
395 devfn_stop = hose->last_devfn;
396
397 for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) {
398
399 if (PCI_FUNC(pci_devfn) && !found_multi)
400 continue;
401
402 early_read_config_word(hose, top_bus, current_bus,
403 pci_devfn, PCI_VENDOR_ID, &vid);
404
405 if (vid == 0xffff)
406 continue;
407
408 early_read_config_byte(hose, top_bus, current_bus,
409 pci_devfn, PCI_HEADER_TYPE,
410 &header_type);
411
412 if (!PCI_FUNC(pci_devfn))
413 found_multi = header_type & 0x80;
414
415 early_read_config_word(hose, top_bus, current_bus,
416 pci_devfn, PCI_DEVICE_ID, &did);
417
418 early_read_config_dword(hose, top_bus, current_bus,
419 pci_devfn, PCI_CLASS_REVISION,
420 &pci_class);
421
422 DBG("%.2x:%.2x.%x Class %.4x: %.4x:%.4x",
423 current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn),
424 pci_class >> 16, vid, did);
425 if (pci_class & 0xff)
426 DBG(" (rev %.2x)", pci_class & 0xff);
427 DBG("\n");
428
429 if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
430 DBG(" Bridge: primary=%.2x, secondary=%.2x\n", current_bus, sub_bus + 1);
431 pciauto_setup_bars(hose, top_bus, current_bus,
432 pci_devfn, PCI_BASE_ADDRESS_1);
433 pciauto_prescan_setup_bridge(hose, top_bus,
434 current_bus,
435 pci_devfn, sub_bus);
436 DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n", sub_bus + 1, pciauto_lower_iospc, pciauto_lower_memspc);
437 sub_bus =
438 pciauto_bus_scan(hose, top_bus, sub_bus + 1);
439 DBG("Back to bus %.2x\n", current_bus);
440 pciauto_postscan_setup_bridge(hose, top_bus,
441 current_bus,
442 pci_devfn, sub_bus);
443 continue;
444 } else if ((pci_class >> 16) == PCI_CLASS_BRIDGE_CARDBUS) {
445 DBG(" CARDBUS Bridge: primary=%.2x, secondary=%.2x\n", current_bus, sub_bus + 1);
446 DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn));
447 /* Place CardBus Socket/ExCA registers */
448 pciauto_setup_bars(hose, top_bus, current_bus,
449 pci_devfn, PCI_BASE_ADDRESS_0);
450
451 pciauto_prescan_setup_cardbus_bridge(hose, top_bus,
452 current_bus,
453 pci_devfn,
454 sub_bus);
455
456 DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n", sub_bus + 1, pciauto_lower_iospc, pciauto_lower_memspc);
457 sub_bus =
458 pciauto_bus_scan(hose, top_bus, sub_bus + 1);
459 DBG("Back to bus %.2x, sub_bus is %x\n",
460 current_bus, sub_bus);
461 pciauto_postscan_setup_cardbus_bridge(hose,
462 top_bus,
463 current_bus,
464 pci_devfn,
465 sub_bus);
466 continue;
467 } else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
468
469 unsigned char prg_iface;
470
471 early_read_config_byte(hose, top_bus, current_bus,
472 pci_devfn, PCI_CLASS_PROG,
473 &prg_iface);
474 if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
475 DBG("Skipping legacy mode IDE controller\n");
476 continue;
477 }
478 }
479
480 /*
481 * Found a peripheral, enable some standard
482 * settings
483 */
484 early_read_config_dword(hose, top_bus, current_bus,
485 pci_devfn, PCI_COMMAND, &cmdstat);
486 early_write_config_dword(hose, top_bus, current_bus,
487 pci_devfn, PCI_COMMAND,
488 cmdstat | PCI_COMMAND_IO |
489 PCI_COMMAND_MEMORY |
490 PCI_COMMAND_MASTER);
491 early_write_config_byte(hose, top_bus, current_bus,
492 pci_devfn, PCI_LATENCY_TIMER,
493 0x80);
494
495 /* Allocate PCI I/O and/or memory space */
496 pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn,
497 PCI_BASE_ADDRESS_5);
498 }
499 return sub_bus;
500 }
501
502 int __init pciauto_assign_resources(int busno, struct pci_channel *hose)
503 {
504 /* setup resource limits */
505 io_resource_inuse = hose->io_resource;
506 mem_resource_inuse = hose->mem_resource;
507
508 pciauto_lower_iospc = io_resource_inuse->start;
509 pciauto_upper_iospc = io_resource_inuse->end + 1;
510 pciauto_lower_memspc = mem_resource_inuse->start;
511 pciauto_upper_memspc = mem_resource_inuse->end + 1;
512 DBG("Autoconfig PCI channel 0x%p\n", hose);
513 DBG("Scanning bus %.2x, I/O 0x%.8x:0x%.8x, Mem 0x%.8x:0x%.8x\n",
514 busno, pciauto_lower_iospc, pciauto_upper_iospc,
515 pciauto_lower_memspc, pciauto_upper_memspc);
516
517 return pciauto_bus_scan(hose, busno, busno);
518 }
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