arch/mips/pci/ops-vrc4173.c

   1 /*
   2  * FILE NAME
   3  *      arch/mips/vr41xx/nec-eagle/vrc4173.c
   4  *
   5  * BRIEF MODULE DESCRIPTION
   6  *      Pre-setup for NEC VRC4173.
   7  *
   8  * Author: Yoichi Yuasa
   9  *         yyuasa@mvista.com or source@mvista.com
  10  *
  11  * Copyright 2001,2002 MontaVista Software Inc.
  12  *
  13  *  This program is free software; you can redistribute it and/or modify it
  14  *  under the terms of the GNU General Public License as published by the
  15  *  Free Software Foundation; either version 2 of the License, or (at your
  16  *  option) any later version.
  17  *
  18  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  19  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  20  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  23  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  24  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  25  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  26  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  27  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  *  You should have received a copy of the GNU General Public License along
  30  *  with this program; if not, write to the Free Software Foundation, Inc.,
  31  *  675 Mass Ave, Cambridge, MA 02139, USA.
  32  */
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35 #include <linux/module.h>
  36
  37 #include <asm/io.h>
  38 #include <asm/vr41xx/eagle.h>
  39 #include <asm/vr41xx/vrc4173.h>
  40
  41 #define PCI_CONFIG_ADDR KSEG1ADDR(0x0f000c18)
  42 #define PCI_CONFIG_DATA KSEG1ADDR(0x0f000c14)
  43
  44 static inline void config_writeb(u8 reg, u8 val)
  45 {
  46         u32 data;
  47         int shift;
  48
  49         writel((1UL << 0x1e) | (reg & 0xfc), PCI_CONFIG_ADDR);
  50         data = readl(PCI_CONFIG_DATA);
  51
  52         shift = (reg & 3) << 3;
  53         data &= ~(0xff << shift);
  54         data |= (((u32) val) << shift);
  55
  56         writel(data, PCI_CONFIG_DATA);
  57 }
  58
  59 static inline u16 config_readw(u8 reg)
  60 {
  61         u32 data;
  62
  63         writel(((1UL << 30) | (reg & 0xfc)), PCI_CONFIG_ADDR);
  64         data = readl(PCI_CONFIG_DATA);
  65
  66         return (u16) (data >> ((reg & 2) << 3));
  67 }
  68
  69 static inline u32 config_readl(u8 reg)
  70 {
  71         writel(((1UL << 30) | (reg & 0xfc)), PCI_CONFIG_ADDR);
  72
  73         return readl(PCI_CONFIG_DATA);
  74 }
  75
  76 static inline void config_writel(u8 reg, u32 val)
  77 {
  78         writel((1UL << 0x1e) | (reg & 0xfc), PCI_CONFIG_ADDR);
  79         writel(val, PCI_CONFIG_DATA);
  80 }
  81
  82 void __init vrc4173_preinit(void)
  83 {
  84         u32 cmdsts, base;
  85         u16 cmu_mask;
  86
  87
  88         if ((config_readw(PCI_VENDOR_ID) == PCI_VENDOR_ID_NEC) &&
  89             (config_readw(PCI_DEVICE_ID) == PCI_DEVICE_ID_NEC_VRC4173)) {
  90                 /*
  91                  * Initialized NEC VRC4173 Bus Control Unit
  92                  */
  93                 cmdsts = config_readl(PCI_COMMAND);
  94                 config_writel(PCI_COMMAND,
  95                               cmdsts |
  96                               PCI_COMMAND_IO |
  97                               PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  98
  99                 config_writeb(PCI_LATENCY_TIMER, 0x80);
 100
 101                 config_writel(PCI_BASE_ADDRESS_0, VR41XX_PCI_IO_START);
 102                 base = config_readl(PCI_BASE_ADDRESS_0);
 103                 base &= PCI_BASE_ADDRESS_IO_MASK;
 104                 config_writeb(0x40, 0x01);
 105
 106                 /* CARDU1 IDSEL = AD12, CARDU2 IDSEL = AD13 */
 107                 config_writeb(0x41, 0);
 108
 109                 cmu_mask = 0x1000;
 110                 outw(cmu_mask, base + 0x040);
 111                 cmu_mask |= 0x0800;
 112                 outw(cmu_mask, base + 0x040);
 113
 114                 outw(0x000f, base + 0x042);     /* Soft reset of CMU */
 115                 cmu_mask |= 0x05e0;
 116                 outw(cmu_mask, base + 0x040);
 117                 cmu_mask = inw(base + 0x040);   /* dummy read */
 118                 outw(0x0000, base + 0x042);
 119         }
 120 }