arch/mips/pci/ops-ocelot.c

   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  * Galileo Evaluation Boards PCI support.
   4  *
   5  * The general-purpose functions to read/write and configure the GT64120A's
   6  * PCI registers (function names start with pci0 or pci1) are either direct
   7  * copies of functions written by Galileo Technology, or are modifications
   8  * of their functions to work with Linux 2.4 vs Linux 2.2.  These functions
   9  * are Copyright - Galileo Technology.
  10  *
  11  * Other functions are derived from other MIPS PCI implementations, or were
  12  * written by RidgeRun, Inc,  Copyright (C) 2000 RidgeRun, Inc.
  13  *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
  14  *
  15  * Copyright 2001 MontaVista Software Inc.
  16  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
  17  *
  18  *  This program is free software; you can redistribute  it and/or modify it
  19  *  under  the terms of  the GNU General  Public License as published by the
  20  *  Free Software Foundation;  either version 2 of the  License, or (at your
  21  *  option) any later version.
  22  *
  23  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  24  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  25  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  26  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  27  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  28  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  29  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  30  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  31  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  32  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  *
  34  *  You should have received a copy of the  GNU General Public License along
  35  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  36  *  675 Mass Ave, Cambridge, MA 02139, USA.
  37  */
  38 #include <linux/types.h>
  39 #include <linux/pci.h>
  40 #include <linux/kernel.h>
  41 #include <linux/slab.h>
  42 #include <linux/version.h>
  43 #include <linux/cache.h>
  44 #include <asm/pci.h>
  45 #include <asm/io.h>
  46 #include <asm/gt64120/gt64120.h>
  47
  48 #include <linux/init.h>
  49
  50 #define SELF 0
  51
  52 /*
  53  * These functions and structures provide the BIOS scan and mapping of the PCI
  54  * devices.
  55  */
  56
  57 #define MAX_PCI_DEVS 10
  58
  59 struct pci_device {
  60         u32 slot;
  61         u32 BARtype[6];
  62         u32 BARsize[6];
  63 };
  64
  65 static void __init scan_and_initialize_pci(void);
  66 static u32 __init scan_pci_bus(struct pci_device *pci_devices);
  67 static void __init allocate_pci_space(struct pci_device *pci_devices);
  68
  69 /*
  70  * The functions that actually read and write to the controller.
  71  *
  72  *  Copied from or modified from Galileo Technology code.
  73  */
  74 static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device);
  75 static void pci0WriteConfigReg(unsigned int offset,
  76                                struct pci_dev *device, unsigned int data);
  77 static unsigned int pci1ReadConfigReg(int offset, struct pci_dev *device);
  78 static void pci1WriteConfigReg(unsigned int offset,
  79                                struct pci_dev *device, unsigned int data);
  80
  81 static void pci0MapIOspace(unsigned int pci0IoBase,
  82                            unsigned int pci0IoLength);
  83 static void pci1MapIOspace(unsigned int pci1IoBase,
  84                            unsigned int pci1IoLength);
  85 static void pci0MapMemory0space(unsigned int pci0Mem0Base,
  86                                 unsigned int pci0Mem0Length);
  87 static void pci1MapMemory0space(unsigned int pci1Mem0Base,
  88                                 unsigned int pci1Mem0Length);
  89 static void pci0MapMemory1space(unsigned int pci0Mem1Base,
  90                                 unsigned int pci0Mem1Length);
  91 static void pci1MapMemory1space(unsigned int pci1Mem1Base,
  92                                 unsigned int pci1Mem1Length);
  93 static unsigned int pci0GetIOspaceBase(void);
  94 static unsigned int pci0GetIOspaceSize(void);
  95 static unsigned int pci0GetMemory0Base(void);
  96 static unsigned int pci0GetMemory0Size(void);
  97 static unsigned int pci0GetMemory1Base(void);
  98 static unsigned int pci0GetMemory1Size(void);
  99 static unsigned int pci1GetIOspaceBase(void);
 100 static unsigned int pci1GetIOspaceSize(void);
 101 static unsigned int pci1GetMemory0Base(void);
 102 static unsigned int pci1GetMemory0Size(void);
 103 static unsigned int pci1GetMemory1Base(void);
 104 static unsigned int pci1GetMemory1Size(void);
 105
 106
 107 /*  Functions to implement "pci ops"  */
 108 static int galileo_pcibios_read(struct pci_bus *bus, unsigned int devfn,
 109                                 int offset, int size, u32 * val);
 110 static int galileo_pcibios_write(struct pci_bus *bus, unsigned int devfn,
 111                                  int offset, int size, u32 val);
 112 static void galileo_pcibios_set_master(struct pci_dev *dev);
 113
 114 /*
 115  *  General-purpose PCI functions.
 116  */
 117
 118 /*
 119  * pci0MapIOspace - Maps PCI0 IO space for the master.
 120  * Inputs: base and length of pci0Io
 121  */
 122
 123 static void pci0MapIOspace(unsigned int pci0IoBase,
 124                            unsigned int pci0IoLength)
 125 {
 126         unsigned int pci0IoTop =
 127             (unsigned int) (pci0IoBase + pci0IoLength);
 128
 129         if (pci0IoLength == 0)
 130                 pci0IoTop++;
 131
 132         pci0IoBase = (unsigned int) (pci0IoBase >> 21);
 133         pci0IoTop = (unsigned int) (((pci0IoTop - 1) & 0x0fffffff) >> 21);
 134         GT_WRITE(GT_PCI0IOLD_OFS, pci0IoBase);
 135         GT_WRITE(GT_PCI0IOHD_OFS, pci0IoTop);
 136 }
 137
 138 /*
 139  * pci1MapIOspace - Maps PCI1 IO space for the master.
 140  * Inputs: base and length of pci1Io
 141  */
 142
 143 static void pci1MapIOspace(unsigned int pci1IoBase,
 144                            unsigned int pci1IoLength)
 145 {
 146         unsigned int pci1IoTop =
 147             (unsigned int) (pci1IoBase + pci1IoLength);
 148
 149         if (pci1IoLength == 0)
 150                 pci1IoTop++;
 151
 152         pci1IoBase = (unsigned int) (pci1IoBase >> 21);
 153         pci1IoTop = (unsigned int) (((pci1IoTop - 1) & 0x0fffffff) >> 21);
 154         GT_WRITE(GT_PCI1IOLD_OFS, pci1IoBase);
 155         GT_WRITE(GT_PCI1IOHD_OFS, pci1IoTop);
 156 }
 157
 158 /*
 159  * pci0MapMemory0space - Maps PCI0 memory0 space for the master.
 160  * Inputs: base and length of pci0Mem0
 161  */
 162
 163 static void pci0MapMemory0space(unsigned int pci0Mem0Base,
 164                                 unsigned int pci0Mem0Length)
 165 {
 166         unsigned int pci0Mem0Top = pci0Mem0Base + pci0Mem0Length;
 167
 168         if (pci0Mem0Length == 0)
 169                 pci0Mem0Top++;
 170
 171         pci0Mem0Base = pci0Mem0Base >> 21;
 172         pci0Mem0Top = ((pci0Mem0Top - 1) & 0x0fffffff) >> 21;
 173         GT_WRITE(GT_PCI0M0LD_OFS, pci0Mem0Base);
 174         GT_WRITE(GT_PCI0M0HD_OFS, pci0Mem0Top);
 175 }
 176
 177 /*
 178  * pci1MapMemory0space - Maps PCI1 memory0 space for the master.
 179  * Inputs: base and length of pci1Mem0
 180  */
 181
 182 static void pci1MapMemory0space(unsigned int pci1Mem0Base,
 183                                 unsigned int pci1Mem0Length)
 184 {
 185         unsigned int pci1Mem0Top = pci1Mem0Base + pci1Mem0Length;
 186
 187         if (pci1Mem0Length == 0)
 188                 pci1Mem0Top++;
 189
 190         pci1Mem0Base = pci1Mem0Base >> 21;
 191         pci1Mem0Top = ((pci1Mem0Top - 1) & 0x0fffffff) >> 21;
 192         GT_WRITE(GT_PCI1M0LD_OFS, pci1Mem0Base);
 193         GT_WRITE(GT_PCI1M0HD_OFS, pci1Mem0Top);
 194 }
 195
 196 /*
 197  * pci0MapMemory1space - Maps PCI0 memory1 space for the master.
 198  * Inputs: base and length of pci0Mem1
 199  */
 200
 201 static void pci0MapMemory1space(unsigned int pci0Mem1Base,
 202                                 unsigned int pci0Mem1Length)
 203 {
 204         unsigned int pci0Mem1Top = pci0Mem1Base + pci0Mem1Length;
 205
 206         if (pci0Mem1Length == 0)
 207                 pci0Mem1Top++;
 208
 209         pci0Mem1Base = pci0Mem1Base >> 21;
 210         pci0Mem1Top = ((pci0Mem1Top - 1) & 0x0fffffff) >> 21;
 211         GT_WRITE(GT_PCI0M1LD_OFS, pci0Mem1Base);
 212         GT_WRITE(GT_PCI0M1HD_OFS, pci0Mem1Top);
 213
 214 }
 215
 216 /*
 217  * pci1MapMemory1space - Maps PCI1 memory1 space for the master.
 218  * Inputs: base and length of pci1Mem1
 219  */
 220
 221 static void pci1MapMemory1space(unsigned int pci1Mem1Base,
 222                                 unsigned int pci1Mem1Length)
 223 {
 224         unsigned int pci1Mem1Top = pci1Mem1Base + pci1Mem1Length;
 225
 226         if (pci1Mem1Length == 0)
 227                 pci1Mem1Top++;
 228
 229         pci1Mem1Base = pci1Mem1Base >> 21;
 230         pci1Mem1Top = ((pci1Mem1Top - 1) & 0x0fffffff) >> 21;
 231         GT_WRITE(GT_PCI1M1LD_OFS, pci1Mem1Base);
 232         GT_WRITE(GT_PCI1M1HD_OFS, pci1Mem1Top);
 233 }
 234
 235 /*
 236  * pci0GetIOspaceBase - Return PCI0 IO Base Address.
 237  * Inputs: N/A
 238  * Returns: PCI0 IO Base Address.
 239  */
 240
 241 static unsigned int pci0GetIOspaceBase(void)
 242 {
 243         unsigned int base;
 244         GT_READ(GT_PCI0IOLD_OFS, &base);
 245         base = base << 21;
 246         return base;
 247 }
 248
 249 /*
 250  * pci0GetIOspaceSize - Return PCI0 IO Bar Size.
 251  * Inputs: N/A
 252  * Returns: PCI0 IO Bar Size.
 253  */
 254
 255 static unsigned int pci0GetIOspaceSize(void)
 256 {
 257         unsigned int top, base, size;
 258         GT_READ(GT_PCI0IOLD_OFS, &base);
 259         base = base << 21;
 260         GT_READ(GT_PCI0IOHD_OFS, &top);
 261         top = (top << 21);
 262         size = ((top - base) & 0xfffffff);
 263         size = size | 0x1fffff;
 264         return (size + 1);
 265 }
 266
 267 /*
 268  * pci0GetMemory0Base - Return PCI0 Memory 0 Base Address.
 269  * Inputs: N/A
 270  * Returns: PCI0 Memory 0 Base Address.
 271  */
 272
 273 static unsigned int pci0GetMemory0Base(void)
 274 {
 275         unsigned int base;
 276         GT_READ(GT_PCI0M0LD_OFS, &base);
 277         base = base << 21;
 278         return base;
 279 }
 280
 281 /*
 282  * pci0GetMemory0Size - Return PCI0 Memory 0 Bar Size.
 283  * Inputs: N/A
 284  * Returns: PCI0 Memory 0 Bar Size.
 285  */
 286
 287 static unsigned int pci0GetMemory0Size(void)
 288 {
 289         unsigned int top, base, size;
 290         GT_READ(GT_PCI0M0LD_OFS, &base);
 291         base = base << 21;
 292         GT_READ(GT_PCI0M0HD_OFS, &top);
 293         top = (top << 21);
 294         size = ((top - base) & 0xfffffff);
 295         size = size | 0x1fffff;
 296         return (size + 1);
 297 }
 298
 299 /*
 300  * pci0GetMemory1Base - Return PCI0 Memory 1 Base Address.
 301  * Inputs: N/A
 302  * Returns: PCI0 Memory 1 Base Address.
 303  */
 304
 305 static unsigned int pci0GetMemory1Base(void)
 306 {
 307         unsigned int base;
 308         GT_READ(GT_PCI0M1LD_OFS, &base);
 309         base = base << 21;
 310         return base;
 311 }
 312
 313 /*
 314  * pci0GetMemory1Size - Return PCI0 Memory 1 Bar Size.
 315  * Inputs: N/A
 316  * Returns: PCI0 Memory 1 Bar Size.
 317  */
 318
 319 static unsigned int pci0GetMemory1Size(void)
 320 {
 321         unsigned int top, base, size;
 322         GT_READ(GT_PCI0M1LD_OFS, &base);
 323         base = base << 21;
 324         GT_READ(GT_PCI0M1HD_OFS, &top);
 325         top = (top << 21);
 326         size = ((top - base) & 0xfffffff);
 327         size = size | 0x1fffff;
 328         return (size + 1);
 329 }
 330
 331 /*
 332  * pci1GetIOspaceBase - Return PCI1 IO Base Address.
 333  * Inputs: N/A
 334  * Returns: PCI1 IO Base Address.
 335  */
 336
 337 static unsigned int pci1GetIOspaceBase(void)
 338 {
 339         unsigned int base;
 340         GT_READ(GT_PCI1IOLD_OFS, &base);
 341         base = base << 21;
 342         return base;
 343 }
 344
 345 /*
 346  * pci1GetIOspaceSize - Return PCI1 IO Bar Size.
 347  * Inputs: N/A
 348  * Returns: PCI1 IO Bar Size.
 349  */
 350
 351 static unsigned int pci1GetIOspaceSize(void)
 352 {
 353         unsigned int top, base, size;
 354         GT_READ(GT_PCI1IOLD_OFS, &base);
 355         base = base << 21;
 356         GT_READ(GT_PCI1IOHD_OFS, &top);
 357         top = (top << 21);
 358         size = ((top - base) & 0xfffffff);
 359         size = size | 0x1fffff;
 360         return (size + 1);
 361 }
 362
 363 /*
 364  * pci1GetMemory0Base - Return PCI1 Memory 0 Base Address.
 365  * Inputs: N/A
 366  * Returns: PCI1 Memory 0 Base Address.
 367  */
 368
 369 static unsigned int pci1GetMemory0Base(void)
 370 {
 371         unsigned int base;
 372         GT_READ(GT_PCI1M0LD_OFS, &base);
 373         base = base << 21;
 374         return base;
 375 }
 376
 377 /*
 378  * pci1GetMemory0Size - Return PCI1 Memory 0 Bar Size.
 379  * Inputs: N/A
 380  * Returns: PCI1 Memory 0 Bar Size.
 381  */
 382
 383 static unsigned int pci1GetMemory0Size(void)
 384 {
 385         unsigned int top, base, size;
 386         GT_READ(GT_PCI1M1LD_OFS, &base);
 387         base = base << 21;
 388         GT_READ(GT_PCI1M1HD_OFS, &top);
 389         top = (top << 21);
 390         size = ((top - base) & 0xfffffff);
 391         size = size | 0x1fffff;
 392         return (size + 1);
 393 }
 394
 395 /*
 396  * pci1GetMemory1Base - Return PCI1 Memory 1 Base Address.
 397  * Inputs: N/A
 398  * Returns: PCI1 Memory 1 Base Address.
 399  */
 400
 401 static unsigned int pci1GetMemory1Base(void)
 402 {
 403         unsigned int base;
 404         GT_READ(GT_PCI1M1LD_OFS, &base);
 405         base = base << 21;
 406         return base;
 407 }
 408
 409 /*
 410  * pci1GetMemory1Size - Return PCI1 Memory 1 Bar Size.
 411  * Inputs: N/A
 412  * Returns: PCI1 Memory 1 Bar Size.
 413  */
 414
 415 static unsigned int pci1GetMemory1Size(void)
 416 {
 417         unsigned int top, base, size;
 418         GT_READ(GT_PCI1M1LD_OFS, &base);
 419         base = base << 21;
 420         GT_READ(GT_PCI1M1HD_OFS, &top);
 421         top = (top << 21);
 422         size = ((top - base) & 0xfffffff);
 423         size = size | 0x1fffff;
 424         return (size + 1);
 425 }
 426
 427
 428
 429 /*
 430  * pci_range_ck -
 431  *
 432  * Check if the pci device that are trying to access does really exists
 433  * on the evaluation board.
 434  *
 435  * Inputs :
 436  * bus - bus number (0 for PCI 0 ; 1 for PCI 1)
 437  * dev - number of device on the specific pci bus
 438  *
 439  * Outpus :
 440  * 0 - if OK , 1 - if failure
 441  */
 442 static __inline__ int pci_range_ck(unsigned char bus, unsigned char dev)
 443 {
 444         /*
 445          * We don't even pretend to handle other busses than bus 0 correctly.
 446          * Accessing device 31 crashes the CP7000 for some reason.
 447          */
 448         if ((bus == 0) && (dev != 31))
 449                 return 0;
 450         return -1;
 451 }
 452
 453 /*
 454  * pciXReadConfigReg  - Read from a PCI configuration register
 455  *                    - Make sure the GT is configured as a master before
 456  *                      reading from another device on the PCI.
 457  *                   - The function takes care of Big/Little endian conversion.
 458  * INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
 459  *                        spec)
 460  *           pciDevNum: The device number needs to be addressed.
 461  * RETURNS: data , if the data == 0xffffffff check the master abort bit in the
 462  *                 cause register to make sure the data is valid
 463  *
 464  *  Configuration Address 0xCF8:
 465  *
 466  *       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
 467  *  |congif|Reserved|  Bus |Device|Function|Register|00|
 468  *  |Enable|        |Number|Number| Number | Number |  |    <=field Name
 469  *
 470  */
 471 static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device)
 472 {
 473         unsigned int DataForRegCf8;
 474         unsigned int data;
 475
 476         DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
 477                          (PCI_FUNC(device->devfn) << 8) |
 478                          (offset & ~0x3)) | 0x80000000;
 479         GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
 480
 481         /*
 482          * The casual observer might wonder why the READ is duplicated here,
 483          * rather than immediately following the WRITE, and just have the swap
 484          * in the "if".  That's because there is a latency problem with trying
 485          * to read immediately after setting up the address register.  The "if"
 486          * check gives enough time for the address to stabilize, so the READ
 487          * can work.
 488          */
 489         if (PCI_SLOT(device->devfn) == SELF) {  /* This board */
 490                 GT_READ(GT_PCI0_CFGDATA_OFS, &data);
 491                 return data;
 492         } else {                /* The PCI is working in LE Mode so swap the Data. */
 493                 GT_READ(GT_PCI0_CFGDATA_OFS, &data);
 494                 return cpu_to_le32(data);
 495         }
 496 }
 497
 498 static unsigned int pci1ReadConfigReg(int offset, struct pci_dev *device)
 499 {
 500         unsigned int DataForRegCf8;
 501         unsigned int data;
 502
 503         DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
 504                          (PCI_FUNC(device->devfn) << 8) |
 505                          (offset & ~0x3)) | 0x80000000;
 506         /*
 507          * The casual observer might wonder why the READ is duplicated here,
 508          * rather than immediately following the WRITE, and just have the
 509          * swap in the "if".  That's because there is a latency problem
 510          * with trying to read immediately after setting up the address
 511          * register.  The "if" check gives enough time for the address
 512          * to stabilize, so the READ can work.
 513          */
 514         if (PCI_SLOT(device->devfn) == SELF) {  /* This board */
 515                 /* when configurating our own PCI 1 L-unit the access is through
 516                    the PCI 0 interface with reg number = reg number + 0x80 */
 517                 DataForRegCf8 |= 0x80;
 518                 GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
 519         } else {                /* The PCI is working in LE Mode so swap the Data. */
 520                 GT_WRITE(GT_PCI1_CFGADDR_OFS, DataForRegCf8);
 521         }
 522         if (PCI_SLOT(device->devfn) == SELF) {  /* This board */
 523                 GT_READ(GT_PCI0_CFGDATA_OFS, &data);
 524                 return data;
 525         } else {
 526                 GT_READ(GT_PCI1_CFGDATA_OFS, &data);
 527                 return cpu_to_le32(data);
 528         }
 529 }
 530
 531
 532
 533 /*
 534  * pciXWriteConfigReg - Write to a PCI configuration register
 535  *                    - Make sure the GT is configured as a master before
 536  *                      writingto another device on the PCI.
 537  *                    - The function takes care of Big/Little endian conversion.
 538  * Inputs:   unsigned int regOffset: The register offset as it apears in the
 539  *           GT spec
 540  *                   (or any other PCI device spec)
 541  *           pciDevNum: The device number needs to be addressed.
 542  *
 543  *  Configuration Address 0xCF8:
 544  *
 545  *       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
 546  *  |congif|Reserved|  Bus |Device|Function|Register|00|
 547  *  |Enable|        |Number|Number| Number | Number |  |    <=field Name
 548  *
 549  */
 550 static void pci0WriteConfigReg(unsigned int offset,
 551                                struct pci_dev *device, unsigned int data)
 552 {
 553         unsigned int DataForRegCf8;
 554
 555         DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
 556                          (PCI_FUNC(device->devfn) << 8) |
 557                          (offset & ~0x3)) | 0x80000000;
 558         GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
 559         if (PCI_SLOT(device->devfn) == SELF) {  /* This board */
 560                 GT_WRITE(GT_PCI0_CFGDATA_OFS, data);
 561         } else {                /* configuration Transaction over the pci. */
 562                 /* The PCI is working in LE Mode so swap the Data. */
 563                 GT_WRITE(GT_PCI0_CFGDATA_OFS, le32_to_cpu(data));
 564         }
 565 }
 566
 567 static void pci1WriteConfigReg(unsigned int offset,
 568                                struct pci_dev *device, unsigned int data)
 569 {
 570         unsigned int DataForRegCf8;
 571
 572         DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
 573                          (PCI_FUNC(device->devfn) << 8) |
 574                          (offset & ~0x3)) | 0x80000000;
 575         /*
 576          * There is a latency problem
 577          * with trying to read immediately after setting up the address
 578          * register.  The "if" check gives enough time for the address
 579          * to stabilize, so the WRITE can work.
 580          */
 581         if (PCI_SLOT(device->devfn) == SELF) {  /* This board */
 582                 /*
 583                  * when configurating our own PCI 1 L-unit the access is through
 584                  * the PCI 0 interface with reg number = reg number + 0x80
 585                  */
 586                 DataForRegCf8 |= 0x80;
 587                 GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
 588         } else {                /* configuration Transaction over the pci. */
 589                 /* The PCI is working in LE Mode so swap the Data. */
 590                 GT_WRITE(GT_PCI1_CFGADDR_OFS, DataForRegCf8);
 591         }
 592         if (PCI_SLOT(device->devfn) == SELF) {  /* This board */
 593                 GT_WRITE(GT_PCI0_CFGDATA_OFS, data);
 594         } else {                /* configuration Transaction over the pci. */
 595                 GT_WRITE(GT_PCI1_CFGADDR_OFS, le32_to_cpu(data));
 596         }
 597 }
 598
 599
 600 /*
 601  * galileo_pcibios_(read/write) -
 602  *
 603  * reads/write a dword/word/byte register from the configuration space
 604  * of a device.
 605  *
 606  * Inputs :
 607  * bus - bus number
 608  * devfn - device function index
 609  * offset - register offset in the configuration space
 610  * size - size of value (1=byte,2=word,4-dword)
 611  * val - value to be written / read
 612  *
 613  * Outputs :
 614  * PCIBIOS_SUCCESSFUL when operation was succesfull
 615  * PCIBIOS_DEVICE_NOT_FOUND when the bus or dev is errorneous
 616  * PCIBIOS_BAD_REGISTER_NUMBER when accessing non aligned
 617  */
 618
 619 static int galileo_pcibios_read(struct pci_bus *bus, unsigned int devfn,
 620                                 int offset, int size, u32 * val)
 621 {
 622         int dev, busnum;
 623
 624         busnum = bus->number;
 625         dev = PCI_SLOT(devfn);
 626
 627         if (pci_range_ck(busnum, dev)) {
 628                 if (size == 1)
 629                         *val = (u8) 0xff;
 630                 else if (size == 2)
 631                         *val = (u16) 0xffff;
 632                 else if (size == 4)
 633                         *val = 0xffffffff;
 634                 return PCIBIOS_DEVICE_NOT_FOUND;
 635         }
 636         if ((size == 2) && (offset & 0x1))
 637                 return PCIBIOS_BAD_REGISTER_NUMBER;
 638         else if ((size == 4) && (offset & 0x3))
 639                 return PCIBIOS_BAD_REGISTER_NUMBER;
 640
 641         if (busnum == 0) {
 642                 if (size == 1) {
 643                         *val = (u8) (pci0ReadConfigReg(offset, bus->dev) >>
 644                                      ((offset & ~0x3) * 8));
 645                 } else if (size == 2) {
 646                         *val =
 647                             (u16) (pci0ReadConfigReg(offset, bus->dev) >>
 648                                    ((offset & ~0x3) * 8));
 649                 } else if (size == 4) {
 650                         *val = pci0ReadConfigReg(offset, bus->dev);
 651                 }
 652         }
 653
 654         /*
 655          *  This is so that the upper PCI layer will get the correct return
 656          * value if we're not attached to anything.
 657          */
 658         switch (size) {
 659         case 1:
 660                 if ((offset == 0xe) && (*val == (u8) 0xff)) {
 661                         u32 MasterAbort;
 662                         GT_READ(GT_INTRCAUSE_OFS, &MasterAbort);
 663                         if (MasterAbort & 0x40000) {
 664                                 GT_WRITE(GT_INTRCAUSE_OFS,
 665                                          (MasterAbort & 0xfffbffff));
 666                                 return PCIBIOS_DEVICE_NOT_FOUND;
 667                         }
 668                 }
 669                 break;
 670         case 4:
 671                 if ((offset == 0) && (*val == 0xffffffff)) {
 672                         return PCIBIOS_DEVICE_NOT_FOUND;
 673                 }
 674         break}
 675         return PCIBIOS_SUCCESSFUL;
 676 }
 677
 678 static int galileo_pcibios_write(struct pci_bus *bus, unsigned int devfn,
 679                                  int offset, int size, u32 val)
 680 {
 681         int dev, busnum;
 682         unsigned long tmp;
 683
 684         busnum = bus->number;
 685         dev = PCI_SLOT(devfn);
 686
 687         if (pci_range_ck(busnum, dev))
 688                 return PCIBIOS_DEVICE_NOT_FOUND;
 689         if (size == 4) {
 690                 if (offset & 0x3)
 691                         return PCIBIOS_BAD_REGISTER_NUMBER;
 692                 if (busnum == 0)
 693                         pci0WriteConfigReg(offset, bus->dev, val);
 694                 //if (busnum == 1) pci1WriteConfigReg (offset,bus->dev,val);
 695                 return PCIBIOS_SUCCESSFUL;
 696         }
 697         if ((size == 2) && (offset & 0x1))
 698                 return PCIBIOS_BAD_REGISTER_NUMBER;
 699         if (busnum == 0) {
 700                 tmp = pci0ReadConfigReg(offset, bus->dev);
 701                 //if (busnum == 1) tmp = pci1ReadConfigReg (offset,bus->dev);
 702                 if (size == 1) {
 703                         if ((offset % 4) == 0)
 704                                 tmp =
 705                                     (tmp & 0xffffff00) | (val & (u8) 0xff);
 706                         if ((offset % 4) == 1)
 707                                 tmp =
 708                                     (tmp & 0xffff00ff) | ((val & (u8) 0xff)
 709                                                           << 8);
 710                         if ((offset % 4) == 2)
 711                                 tmp =
 712                                     (tmp & 0xff00ffff) | ((val & (u8) 0xff)
 713                                                           << 16);
 714                         if ((offset % 4) == 3)
 715                                 tmp =
 716                                     (tmp & 0x00ffffff) | ((val & (u8) 0xff)
 717                                                           << 24);
 718                 } else if (size == 2) {
 719                         if ((offset % 4) == 0)
 720                                 tmp =
 721                                     (tmp & 0xffff0000) | (val & (u16)
 722                                                           0xffff);
 723                         if ((offset % 4) == 2)
 724                                 tmp =
 725                                     (tmp & 0x0000ffff) |
 726                                     ((val & (u16) 0xffff) << 16);
 727                 }
 728                 if (busnum == 0)
 729                         pci0WriteConfigReg(offset, bus->dev, tmp);
 730                 //if (busnum == 1) pci1WriteConfigReg (offset,bus->dev,tmp);
 731         }
 732         return PCIBIOS_SUCCESSFUL;
 733 }
 734
 735 static void galileo_pcibios_set_master(struct pci_dev *dev)
 736 {
 737         u16 cmd;
 738
 739         galileo_pcibios_read(dev->bus, dev->devfn, PCI_COMMAND, 2, &cmd);
 740         cmd |= PCI_COMMAND_MASTER;
 741         galileo_pcibios_write(dev->bus, dev->devfn, PCI_COMMAND, 2, cmd);
 742 }
 743
 744 /*  Externally-expected functions.  Do not change function names  */
 745
 746 int pcibios_enable_resources(struct pci_dev *dev)
 747 {
 748         u16 cmd, old_cmd;
 749         u8 tmp1;
 750         int idx;
 751         struct resource *r;
 752
 753         galileo_pcibios_read(dev->bus, dev->devfn, PCI_COMMAND, 2, &cmd);
 754         old_cmd = cmd;
 755         for (idx = 0; idx < 6; idx++) {
 756                 r = &dev->resource[idx];
 757                 if (!r->start && r->end) {
 758                         printk(KERN_ERR
 759                                "PCI: Device %s not available because of "
 760                                "resource collisions\n", dev->slot_name);
 761                         return -EINVAL;
 762                 }
 763                 if (r->flags & IORESOURCE_IO)
 764                         cmd |= PCI_COMMAND_IO;
 765                 if (r->flags & IORESOURCE_MEM)
 766                         cmd |= PCI_COMMAND_MEMORY;
 767         }
 768         if (cmd != old_cmd) {
 769                 galileo_pcibios_write(dev->bus, dev->devfn, PCI_COMMAND, 2,
 770                                       cmd);
 771         }
 772
 773         /*
 774          * Let's fix up the latency timer and cache line size here.  Cache
 775          * line size = 32 bytes / sizeof dword (4) = 8.
 776          * Latency timer must be > 8.  32 is random but appears to work.
 777          */
 778         galileo_pcibios_read(dev->bus, dev->devfn, PCI_CACHE_LINE_SIZE, 1,
 779                              &tmp1);
 780         if (tmp1 != 8) {
 781                 printk(KERN_WARNING
 782                        "PCI setting cache line size to 8 from " "%d\n",
 783                        tmp1);
 784                 galileo_pcibios_write(dev->bus, dev->devfn,
 785                                       PCI_CACHE_LINE_SIZE, 1, 8);
 786         }
 787         galileo_pcibios_read(dev->bus, dev->devfn, PCI_LATENCY_TIMER, 1,
 788                              &tmp1);
 789         if (tmp1 < 32) {
 790                 printk(KERN_WARNING
 791                        "PCI setting latency timer to 32 from %d\n", tmp1);
 792                 galileo_pcibios_write(dev->bus, dev->devfn,
 793                                       PCI_LATENCY_TIMER, 1, 32);
 794         }
 795
 796         return 0;
 797 }
 798
 799 int pcibios_enable_device(struct pci_dev *dev, int mask)
 800 {
 801         return pcibios_enable_resources(dev);
 802 }
 803
 804 void pcibios_align_resource(void *data, struct resource *res,
 805                             unsigned long size, unsigned long align)
 806 {
 807         struct pci_dev *dev = data;
 808
 809         if (res->flags & IORESOURCE_IO) {
 810                 unsigned long start = res->start;
 811
 812                 /* We need to avoid collisions with `mirrored' VGA ports
 813                    and other strange ISA hardware, so we always want the
 814                    addresses kilobyte aligned.  */
 815                 if (size > 0x100) {
 816                         printk(KERN_ERR "PCI: I/O Region %s/%d too large"
 817                                " (%ld bytes)\n", dev->slot_name,
 818                                dev->resource - res, size);
 819                 }
 820
 821                 start = (start + 1024 - 1) & ~(1024 - 1);
 822                 res->start = start;
 823         }
 824 }
 825
 826 struct pci_ops galileo_pci_ops = {
 827         .read = galileo_pcibios_read,
 828         .write = galileo_pcibios_write,
 829 };
 830
 831 struct pci_fixup pcibios_fixups[] = {
 832         {0}
 833 };
 834
 835 void __devinit pcibios_fixup_bus(struct pci_bus *c)
 836 {
 837         gt64120_board_pcibios_fixup_bus(c);
 838 }
 839
 840 /*
 841  * This code was derived from Galileo Technology's example
 842  * and significantly reworked.
 843  *
 844  * This is very simple.  It does not scan multiple function devices.  It does
 845  * not scan behind bridges.  Those would be simple to implement, but we don't
 846  * currently need this.
 847  */
 848
 849 static void __init scan_and_initialize_pci(void)
 850 {
 851         struct pci_device pci_devices[MAX_PCI_DEVS];
 852
 853         if (scan_pci_bus(pci_devices)) {
 854                 allocate_pci_space(pci_devices);
 855         }
 856 }
 857
 858 /*
 859  * This is your basic PCI scan.  It goes through each slot and checks to
 860  * see if there's something that responds.  If so, then get the size and
 861  * type of each of the responding BARs.  Save them for later.
 862  */
 863
 864 static u32 __init scan_pci_bus(struct pci_device *pci_devices)
 865 {
 866         u32 arrayCounter = 0;
 867         u32 memType;
 868         u32 memSize;
 869         u32 pci_slot, bar;
 870         u32 id;
 871         u32 c18RegValue;
 872         struct pci_dev device;
 873
 874         /*
 875          * According to PCI REV 2.1 MAX agents on the bus are 21.
 876          * We don't bother scanning ourselves (slot 0).
 877          */
 878         for (pci_slot = 1; pci_slot < 22; pci_slot++) {
 879
 880                 device.devfn = PCI_DEVFN(pci_slot, 0);
 881                 id = pci0ReadConfigReg(PCI_VENDOR_ID, &device);
 882
 883                 /*
 884                  *  Check for a PCI Master Abort (nothing responds in the
 885                  * slot)
 886                  */
 887                 GT_READ(GT_INTRCAUSE_OFS, &c18RegValue);
 888                 /*
 889                  * Clearing bit 18 of in the Cause Register 0xc18 by
 890                  * writting 0.
 891                  */
 892                 GT_WRITE(GT_INTRCAUSE_OFS, (c18RegValue & 0xfffbffff));
 893                 if ((id != 0xffffffff) && !(c18RegValue & 0x40000)) {
 894                         pci_devices[arrayCounter].slot = pci_slot;
 895                         for (bar = 0; bar < 6; bar++) {
 896                                 memType =
 897                                     pci0ReadConfigReg(PCI_BASE_ADDRESS_0 +
 898                                                       (bar * 4), &device);
 899                                 pci_devices[arrayCounter].BARtype[bar] =
 900                                     memType & 1;
 901                                 pci0WriteConfigReg(PCI_BASE_ADDRESS_0 +
 902                                                    (bar * 4), &device,
 903                                                    0xffffffff);
 904                                 memSize =
 905                                     pci0ReadConfigReg(PCI_BASE_ADDRESS_0 +
 906                                                       (bar * 4), &device);
 907                                 if (memType & 1) {      /*  IO space  */
 908                                         pci_devices[arrayCounter].
 909                                             BARsize[bar] =
 910                                             ~(memSize & 0xfffffffc) + 1;
 911                                 } else {        /*  memory space */
 912                                         pci_devices[arrayCounter].
 913                                             BARsize[bar] =
 914                                             ~(memSize & 0xfffffff0) + 1;
 915                                 }
 916                         }       /*  BAR counter  */
 917
 918                         arrayCounter++;
 919                 }
 920                 /*  found a device  */
 921         }                       /*  slot counter  */
 922
 923         if (arrayCounter < MAX_PCI_DEVS)
 924                 pci_devices[arrayCounter].slot = -1;
 925
 926         return arrayCounter;
 927 }
 928
 929 /*
 930  * This function goes through the list of devices and allocates the BARs in
 931  * either IO or MEM space.  It does it in order of size, which will limit the
 932  * amount of fragmentation we have in the IO and MEM spaces.
 933  */
 934
 935 static void __init allocate_pci_space(struct pci_device *pci_devices)
 936 {
 937         u32 count, maxcount, bar;
 938         u32 maxSize, maxDevice, maxBAR;
 939         u32 alignto;
 940         u32 base;
 941         u32 pci0_mem_base = pci0GetMemory0Base();
 942         u32 pci0_io_base = pci0GetIOspaceBase();
 943         struct pci_dev device;
 944
 945         /*  How many PCI devices do we have?  */
 946         maxcount = MAX_PCI_DEVS;
 947         for (count = 0; count < MAX_PCI_DEVS; count++) {
 948                 if (pci_devices[count].slot == -1) {
 949                         maxcount = count;
 950                         break;
 951                 }
 952         }
 953
 954         do {
 955                 /*  Find the largest size BAR we need to allocate  */
 956                 maxSize = 0;
 957                 for (count = 0; count < maxcount; count++) {
 958                         for (bar = 0; bar < 6; bar++) {
 959                                 if (pci_devices[count].BARsize[bar] >
 960                                     maxSize) {
 961                                         maxSize =
 962                                             pci_devices[count].
 963                                             BARsize[bar];
 964                                         maxDevice = count;
 965                                         maxBAR = bar;
 966                                 }
 967                         }
 968                 }
 969
 970                 /*
 971                  * We've found the largest BAR.  Allocate it into IO or
 972                  * mem space.  We don't idiot check the bases to make
 973                  * sure they haven't overflowed the current size for that
 974                  * aperture.
 975                  * Don't bother to enable the device's IO or MEM space here.
 976                  * That will be done in pci_enable_resources if the device is
 977                  * activated by a driver.
 978                  */
 979                 if (maxSize) {
 980                         device.devfn =
 981                             PCI_DEVFN(pci_devices[maxDevice].slot, 0);
 982                         if (pci_devices[maxDevice].BARtype[maxBAR] == 1) {
 983                                 alignto = max(0x1000U, maxSize);
 984                                 base = ALIGN(pci0_io_base, alignto);
 985                                 pci0WriteConfigReg(PCI_BASE_ADDRESS_0 +
 986                                                    (maxBAR * 4), &device,
 987                                                    base | 0x1);
 988                                 pci0_io_base = base + alignto;
 989                         } else {
 990                                 alignto = max(0x1000U, maxSize);
 991                                 base = ALIGN(pci0_mem_base, alignto);
 992                                 pci0WriteConfigReg(PCI_BASE_ADDRESS_0 +
 993                                                    (maxBAR * 4), &device,
 994                                                    base);
 995                                 pci0_mem_base = base + alignto;
 996                         }
 997                         /*
 998                          * This entry is finished.  Remove it from the list
 999                          * we'll scan.
1000                          */
1001                         pci_devices[maxDevice].BARsize[maxBAR] = 0;
1002                 }
1003         } while (maxSize);
1004 }
1005
1006 static int __init pcibios_init(void)
1007 {
1008         u32 tmp;
1009         struct pci_dev controller;
1010
1011         controller.devfn = SELF;
1012
1013         GT_READ(GT_PCI0_CMD_OFS, &tmp);
1014         GT_READ(GT_PCI0_BARE_OFS, &tmp);
1015
1016         /*
1017          * You have to enable bus mastering to configure any other
1018          * card on the bus.
1019          */
1020         tmp = pci0ReadConfigReg(PCI_COMMAND, &controller);
1021         tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
1022         pci0WriteConfigReg(PCI_COMMAND, &controller, tmp);
1023
1024         /*  This scans the PCI bus and sets up initial values.  */
1025         scan_and_initialize_pci();
1026
1027         /*
1028          *  Reset PCI I/O and PCI MEM values to ones supported by EVM.
1029          */
1030         ioport_resource.start = GT_PCI_IO_BASE;
1031         ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
1032         iomem_resource.start = GT_PCI_MEM_BASE;
1033         iomem_resource.end = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1;
1034
1035         pci_scan_bus(0, &galileo_pci_ops, NULL);
1036
1037         return 0;
1038 }
1039
1040 subsys_initcall(pcibios_init);
1041
1042 /*
1043  * for parsing "pci=" kernel boot arguments.
1044  */
1045 char *pcibios_setup(char *str)
1046 {
1047         printk(KERN_INFO "rr: pcibios_setup\n");
1048         /* Nothing to do for now.  */
1049
1050         return str;
1051 }
1052
1053 unsigned __init int pcibios_assign_all_busses(void)
1054 {
1055         return 1;
1056 }