arch/mips/pci/ops-jmr3927.c

   1 /***********************************************************************
   2  * Copyright 2001 MontaVista Software Inc.
   3  * Author: MontaVista Software, Inc.
   4  *              ahennessy@mvista.com
   5  *
   6  * Copyright (C) 2000-2001 Toshiba Corporation
   7  *
   8  * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c
   9  *
  10  *     Define the pci_ops for JMR3927.
  11  *
  12  * Much of the code is derived from the original DDB5074 port by
  13  * Geert Uytterhoeven <geert@sonycom.com>
  14  *
  15  *  This program is free software; you can redistribute  it and/or modify it
  16  *  under  the terms of  the GNU General  Public License as published by the
  17  *  Free Software Foundation;  either version 2 of the  License, or (at your
  18  *  option) any later version.
  19  *
  20  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  21  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  22  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  23  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  24  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  26  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  27  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  28  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  *  You should have received a copy of the  GNU General Public License along
  32  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  33  *  675 Mass Ave, Cambridge, MA 02139, USA.
  34  */
  35 #include <linux/types.h>
  36 #include <linux/pci.h>
  37 #include <linux/kernel.h>
  38 #include <linux/init.h>
  39
  40 #include <asm/addrspace.h>
  41 #include <asm/pci_channel.h>
  42 #include <asm/jmr3927/jmr3927.h>
  43 #include <asm/debug.h>
  44
  45 struct resource pci_io_resource = {
  46         "pci IO space",
  47         0x1000,                 /* reserve regacy I/O space */
  48         0x1000 + JMR3927_PCIIO_SIZE - 1,
  49         IORESOURCE_IO
  50 };
  51
  52 struct resource pci_mem_resource = {
  53         "pci memory space",
  54         JMR3927_PCIMEM,
  55         JMR3927_PCIMEM + JMR3927_PCIMEM_SIZE - 1,
  56         IORESOURCE_MEM
  57 };
  58
  59 extern struct pci_ops jmr3927_pci_ops;
  60
  61 struct pci_channel mips_pci_channels[] = {
  62         {&jmr3927_pci_ops, &pci_io_resource, &pci_mem_resource, 0, 0xff},
  63         {NULL, NULL, NULL, NULL, NULL}
  64 };
  65
  66 unsigned int pcibios_assign_all_busses(void)
  67 {
  68         return 1;
  69 }
  70
  71 static int
  72 mkaddr(unsigned char bus, unsigned char dev_fn, unsigned char where,
  73        int *flagsp)
  74 {
  75         if (bus == 0 && dev_fn >= PCI_DEVFN(TX3927_PCIC_MAX_DEVNU, 0))
  76                 return -1;
  77
  78         tx3927_pcicptr->ica = ((bus & 0xff) << 0x10) |
  79             ((dev_fn & 0xff) << 0x08) | (where & 0xfc);
  80         /* clear M_ABORT and Disable M_ABORT Int. */
  81         tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
  82         tx3927_pcicptr->pcistatim &= ~PCI_STATUS_REC_MASTER_ABORT;
  83         return 0;
  84 }
  85
  86 static int check_abort(int flags)
  87 {
  88         int code = PCIBIOS_SUCCESSFUL;
  89         if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT) {
  90                 tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
  91                 tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT;
  92                 code = PCIBIOS_DEVICE_NOT_FOUND;
  93         }
  94         return code;
  95 }
  96
  97 /*
  98  * We can't address 8 and 16 bit words directly.  Instead we have to
  99  * read/write a 32bit word and mask/modify the data we actually want.
 100  */
 101 static int jmr3927_pcibios_read_config_byte(struct pci_dev *dev,
 102                                             int where, unsigned char *val)
 103 {
 104         int flags;
 105         unsigned char bus, func_num;
 106
 107         db_assert((where & 3) == 0);
 108         db_assert(where < (1 << 8));
 109
 110         /* check if the bus is top-level */
 111         if (dev->bus->parent != NULL) {
 112                 bus = dev->bus->number;
 113                 db_assert(bus != 0);
 114         } else {
 115                 bus = 0;
 116         }
 117
 118         func_num = PCI_FUNC(dev->devfn);
 119         if (mkaddr(bus, dev->devfn, where, &flags))
 120                 return -1;
 121         *val =
 122             *(volatile u8 *) ((ulong) & tx3927_pcicptr->icd | (where & 3));
 123         return check_abort(flags);
 124 }
 125
 126 static int jmr3927_pcibios_read_config_word(struct pci_dev *dev,
 127                                             int where, unsigned short *val)
 128 {
 129         int flags;
 130         unsigned char bus, func_num;
 131
 132         if (where & 1)
 133                 return PCIBIOS_BAD_REGISTER_NUMBER;
 134
 135         db_assert((where & 3) == 0);
 136         db_assert(where < (1 << 8));
 137
 138         /* check if the bus is top-level */
 139         if (dev->bus->parent != NULL) {
 140                 bus = dev->bus->number;
 141                 db_assert(bus != 0);
 142         } else {
 143                 bus = 0;
 144         }
 145
 146         func_num = PCI_FUNC(dev->devfn);
 147         if (mkaddr(bus, dev->devfn, where, &flags))
 148                 return -1;
 149         *val =
 150             le16_to_cpu(*(volatile u16 *)
 151                         ((ulong) & tx3927_pcicptr->icd | (where & 3)));
 152         return check_abort(flags);
 153 }
 154
 155 static int jmr3927_pcibios_read_config_dword(struct pci_dev *dev,
 156                                              int where, unsigned int *val)
 157 {
 158         int flags;
 159         unsigned char bus, func_num;
 160
 161         if (where & 3)
 162                 return PCIBIOS_BAD_REGISTER_NUMBER;
 163
 164         db_assert((where & 3) == 0);
 165         db_assert(where < (1 << 8));
 166
 167         /* check if the bus is top-level */
 168         if (dev->bus->parent != NULL) {
 169                 bus = dev->bus->number;
 170                 db_assert(bus != 0);
 171         } else {
 172                 bus = 0;
 173         }
 174
 175         func_num = PCI_FUNC(dev->devfn);
 176         if (mkaddr(bus, dev->devfn, where, &flags))
 177                 return -1;
 178         *val = le32_to_cpu(tx3927_pcicptr->icd);
 179         return check_abort(flags);
 180 }
 181
 182 static int jmr3927_pcibios_write_config_byte(struct pci_dev *dev,
 183                                              int where, unsigned char val)
 184 {
 185         int flags;
 186         unsigned char bus, func_num;
 187
 188         /* check if the bus is top-level */
 189         if (dev->bus->parent != NULL) {
 190                 bus = dev->bus->number;
 191                 db_assert(bus != 0);
 192         } else {
 193                 bus = 0;
 194         }
 195
 196         func_num = PCI_FUNC(dev->devfn);
 197         if (mkaddr(bus, dev->devfn, where, &flags))
 198                 return -1;
 199         *(volatile u8 *) ((ulong) & tx3927_pcicptr->icd | (where & 3)) =
 200             val;
 201         return check_abort(flags);
 202 }
 203
 204 static int jmr3927_pcibios_write_config_word(struct pci_dev *dev,
 205                                              int where, unsigned short val)
 206 {
 207         int flags;
 208         unsigned char bus, func_num;
 209
 210         if (where & 1)
 211                 return PCIBIOS_BAD_REGISTER_NUMBER;
 212
 213         /* check if the bus is top-level */
 214         if (dev->bus->parent != NULL) {
 215                 bus = dev->bus->number;
 216                 db_assert(bus != 0);
 217         } else {
 218                 bus = 0;
 219         }
 220
 221         func_num = PCI_FUNC(dev->devfn);
 222         if (mkaddr(bus, dev->devfn, where, &flags))
 223                 return -1;
 224         *(volatile u16 *) ((ulong) & tx3927_pcicptr->icd | (where & 3)) =
 225             cpu_to_le16(val);
 226         return check_abort(flags);
 227 }
 228
 229 static int jmr3927_pcibios_write_config_dword(struct pci_dev *dev,
 230                                               int where, unsigned int val)
 231 {
 232         int flags;
 233         unsigned char bus, func_num;
 234
 235         if (where & 3)
 236                 return PCIBIOS_BAD_REGISTER_NUMBER;
 237
 238         /* check if the bus is top-level */
 239         if (dev->bus->parent != NULL) {
 240                 bus = dev->bus->number;
 241                 db_assert(bus != 0);
 242         } else {
 243                 bus = 0;
 244         }
 245
 246         func_num = PCI_FUNC(dev->devfn);
 247         if (mkaddr(bus, dev->devfn, where, &flags))
 248                 return -1;
 249         tx3927_pcicptr->icd = cpu_to_le32(val);
 250         return check_abort(flags);
 251 }
 252 struct pci_ops jmr3927_pci_ops = {
 253         jmr3927_pcibios_read_config_byte,
 254         jmr3927_pcibios_read_config_word,
 255         jmr3927_pcibios_read_config_dword,
 256         jmr3927_pcibios_write_config_byte,
 257         jmr3927_pcibios_write_config_word,
 258         jmr3927_pcibios_write_config_dword
 259 };
 260
 261 #ifndef JMR3927_INIT_INDIRECT_PCI
 262 inline unsigned long tc_readl(volatile __u32 * addr)
 263 {
 264         return readl(addr);
 265 }
 266 inline void tc_writel(unsigned long data, volatile __u32 * addr)
 267 {
 268         writel(data, addr);
 269 }
 270 #else
 271 unsigned long tc_readl(volatile __u32 * addr)
 272 {
 273         unsigned long val;
 274
 275         addr = PHYSADDR(addr);
 276         *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr =
 277             (unsigned long) addr;
 278         *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe =
 279             (PCI_IPCIBE_ICMD_MEMREAD << PCI_IPCIBE_ICMD_SHIFT) |
 280             PCI_IPCIBE_IBE_LONG;
 281         while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
 282         val =
 283             le32_to_cpu(*(volatile u32 *) (ulong) & tx3927_pcicptr->
 284                         ipcidata);
 285         /* clear by setting */
 286         tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
 287         return val;
 288 }
 289 void tc_writel(unsigned long data, volatile __u32 * addr)
 290 {
 291         addr = PHYSADDR(addr);
 292         *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcidata =
 293             cpu_to_le32(data);
 294         *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr =
 295             (unsigned long) addr;
 296         *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe =
 297             (PCI_IPCIBE_ICMD_MEMWRITE << PCI_IPCIBE_ICMD_SHIFT) |
 298             PCI_IPCIBE_IBE_LONG;
 299         while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
 300         /* clear by setting */
 301         tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
 302 }
 303 unsigned char tx_ioinb(unsigned char *addr)
 304 {
 305         unsigned long val;
 306         __u32 ioaddr;
 307         int offset;
 308         int byte;
 309
 310         ioaddr = (unsigned long) addr;
 311         offset = ioaddr & 0x3;
 312         if (offset == 0)
 313                 byte = 0x7;
 314         else if (offset == 1)
 315                 byte = 0xb;
 316         else if (offset == 2)
 317                 byte = 0xd;
 318         else if (offset == 3)
 319                 byte = 0xe;
 320         *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr =
 321             (unsigned long) ioaddr;
 322         *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe =
 323             (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte;
 324         while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
 325         val =
 326             le32_to_cpu(*(volatile u32 *) (ulong) & tx3927_pcicptr->
 327                         ipcidata);
 328         val = val & 0xff;
 329         /* clear by setting */
 330         tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
 331         return val;
 332 }
 333 void tx_iooutb(unsigned long data, unsigned char *addr)
 334 {
 335         __u32 ioaddr;
 336         int offset;
 337         int byte;
 338
 339         data = data | (data << 8) | (data << 16) | (data << 24);
 340         ioaddr = (unsigned long) addr;
 341         offset = ioaddr & 0x3;
 342         if (offset == 0)
 343                 byte = 0x7;
 344         else if (offset == 1)
 345                 byte = 0xb;
 346         else if (offset == 2)
 347                 byte = 0xd;
 348         else if (offset == 3)
 349                 byte = 0xe;
 350         *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcidata = data;
 351         *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr =
 352             (unsigned long) ioaddr;
 353         *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe =
 354             (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte;
 355         while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
 356         /* clear by setting */
 357         tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
 358 }
 359 unsigned short tx_ioinw(unsigned short *addr)
 360 {
 361         unsigned long val;
 362         __u32 ioaddr;
 363         int offset;
 364         int byte;
 365
 366         ioaddr = (unsigned long) addr;
 367         offset = ioaddr & 0x3;
 368         if (offset == 0)
 369                 byte = 0x3;
 370         else if (offset == 2)
 371                 byte = 0xc;
 372         *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr =
 373             (unsigned long) ioaddr;
 374         *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe =
 375             (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte;
 376         while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
 377         val =
 378             le32_to_cpu(*(volatile u32 *) (ulong) & tx3927_pcicptr->
 379                         ipcidata);
 380         val = val & 0xffff;
 381         /* clear by setting */
 382         tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
 383         return val;
 384
 385 }
 386 void tx_iooutw(unsigned long data, unsigned short *addr)
 387 {
 388         __u32 ioaddr;
 389         int offset;
 390         int byte;
 391
 392         data = data | (data << 16);
 393         ioaddr = (unsigned long) addr;
 394         offset = ioaddr & 0x3;
 395         if (offset == 0)
 396                 byte = 0x3;
 397         else if (offset == 2)
 398                 byte = 0xc;
 399         *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcidata = data;
 400         *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr =
 401             (unsigned long) ioaddr;
 402         *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe =
 403             (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte;
 404         while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
 405         /* clear by setting */
 406         tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
 407 }
 408 unsigned long tx_ioinl(unsigned int *addr)
 409 {
 410         unsigned long val;
 411         __u32 ioaddr;
 412
 413         ioaddr = (unsigned long) addr;
 414         *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr =
 415             (unsigned long) ioaddr;
 416         *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe =
 417             (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) |
 418             PCI_IPCIBE_IBE_LONG;
 419         while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
 420         val =
 421             le32_to_cpu(*(volatile u32 *) (ulong) & tx3927_pcicptr->
 422                         ipcidata);
 423         /* clear by setting */
 424         tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
 425         return val;
 426 }
 427 void tx_iooutl(unsigned long data, unsigned int *addr)
 428 {
 429         __u32 ioaddr;
 430
 431         ioaddr = (unsigned long) addr;
 432         *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcidata =
 433             cpu_to_le32(data);
 434         *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr =
 435             (unsigned long) ioaddr;
 436         *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe =
 437             (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) |
 438             PCI_IPCIBE_IBE_LONG;
 439         while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
 440         /* clear by setting */
 441         tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
 442 }
 443 void tx_insbyte(unsigned char *addr, void *buffer, unsigned int count)
 444 {
 445         unsigned char *ptr = (unsigned char *) buffer;
 446
 447         while (count--) {
 448                 *ptr++ = tx_ioinb(addr);
 449         }
 450 }
 451 void tx_insword(unsigned short *addr, void *buffer, unsigned int count)
 452 {
 453         unsigned short *ptr = (unsigned short *) buffer;
 454
 455         while (count--) {
 456                 *ptr++ = tx_ioinw(addr);
 457         }
 458 }
 459 void tx_inslong(unsigned int *addr, void *buffer, unsigned int count)
 460 {
 461         unsigned long *ptr = (unsigned long *) buffer;
 462
 463         while (count--) {
 464                 *ptr++ = tx_ioinl(addr);
 465         }
 466 }
 467 void tx_outsbyte(unsigned char *addr, void *buffer, unsigned int count)
 468 {
 469         unsigned char *ptr = (unsigned char *) buffer;
 470
 471         while (count--) {
 472                 tx_iooutb(*ptr++, addr);
 473         }
 474 }
 475 void tx_outsword(unsigned short *addr, void *buffer, unsigned int count)
 476 {
 477         unsigned short *ptr = (unsigned short *) buffer;
 478
 479         while (count--) {
 480                 tx_iooutw(*ptr++, addr);
 481         }
 482 }
 483 void tx_outslong(unsigned int *addr, void *buffer, unsigned int count)
 484 {
 485         unsigned long *ptr = (unsigned long *) buffer;
 486
 487         while (count--) {
 488                 tx_iooutl(*ptr++, addr);
 489         }
 490 }
 491 #endif