arch/mips/pci/ops-it8172.c

   1 /*
   2  *
   3  * BRIEF MODULE DESCRIPTION
   4  *      IT8172 system controller specific pci support.
   5  *
   6  * Copyright 2000 MontaVista Software Inc.
   7  * Author: MontaVista Software, Inc.
   8  *              ppopov@mvista.com or source@mvista.com
   9  *
  10  *  This program is free software; you can redistribute  it and/or modify it
  11  *  under  the terms of  the GNU General  Public License as published by the
  12  *  Free Software Foundation;  either version 2 of the  License, or (at your
  13  *  option) any later version.
  14  *
  15  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  16  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  17  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  18  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  19  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  21  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  22  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  23  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  *  You should have received a copy of the  GNU General Public License along
  27  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  28  *  675 Mass Ave, Cambridge, MA 02139, USA.
  29  */
  30 #include <linux/types.h>
  31 #include <linux/pci.h>
  32 #include <linux/kernel.h>
  33 #include <linux/init.h>
  34
  35 #include <asm/pci_channel.h>
  36 #include <asm/it8172/it8172.h>
  37 #include <asm/it8172/it8172_pci.h>
  38
  39 #define PCI_ACCESS_READ  0
  40 #define PCI_ACCESS_WRITE 1
  41
  42 #undef DEBUG
  43 #ifdef DEBUG
  44 #define DBG(x...) printk(x)
  45 #else
  46 #define DBG(x...)
  47 #endif
  48
  49 static struct resource pci_mem_resource_1;
  50
  51 static struct resource pci_io_resource = {
  52         "io pci IO space",
  53         0x14018000,
  54         0x17FFFFFF,
  55         IORESOURCE_IO
  56 };
  57
  58 static struct resource pci_mem_resource_0 = {
  59         "ext pci memory space 0/1",
  60         0x10101000,
  61         0x13FFFFFF,
  62         IORESOURCE_MEM,
  63         &pci_mem_resource_0,
  64         NULL,
  65         &pci_mem_resource_1
  66 };
  67
  68 static struct resource pci_mem_resource_1 = {
  69         "ext pci memory space 2/3",
  70         0x1A000000,
  71         0x1FBFFFFF,
  72         IORESOURCE_MEM,
  73         &pci_mem_resource_0,
  74         NULL,
  75         NULL
  76 };
  77
  78 extern struct pci_ops it8172_pci_ops;
  79
  80 struct pci_channel mips_pci_channels[] = {
  81         {&it8172_pci_ops, &pci_io_resource, &pci_mem_resource_0, 0x10,
  82          0xff},
  83         {NULL, NULL, NULL, NULL, NULL}
  84 };
  85
  86 static int it8172_pcibios_config_access(unsigned char access_type,
  87                                         struct pci_bus *bus,
  88                                         unsigned int devfn, int where,
  89                                         u32 * data)
  90 {
  91         /*
  92          * config cycles are on 4 byte boundary only
  93          */
  94
  95         /* Setup address */
  96         IT_WRITE(IT_CONFADDR, (bus->number << IT_BUSNUM_SHF) |
  97                  (devfn << IT_FUNCNUM_SHF) | (where & ~0x3));
  98
  99         if (access_type == PCI_ACCESS_WRITE) {
 100                 IT_WRITE(IT_CONFDATA, *data);
 101         } else {
 102                 IT_READ(IT_CONFDATA, *data);
 103         }
 104
 105         /*
 106          * Revisit: check for master or target abort.
 107          */
 108         return 0;
 109 }
 110
 111
 112 /*
 113  * We can't address 8 and 16 bit words directly.  Instead we have to
 114  * read/write a 32bit word and mask/modify the data we actually want.
 115  */
 116 static write_config(struct pci_bus *bus, unsigned int devfn, int where,
 117                     int size, u32 val)
 118 {
 119         u32 data = 0;
 120
 121         switch (size) {
 122         case 1:
 123                 if (it8172_pcibios_config_access
 124                     (PCI_ACCESS_READ, dev, where, &data))
 125                         return -1;
 126
 127                 *val = (data >> ((where & 3) << 3)) & 0xff;
 128
 129                 return PCIBIOS_SUCCESSFUL;
 130
 131         case 2:
 132
 133                 if (where & 1)
 134                         return PCIBIOS_BAD_REGISTER_NUMBER;
 135
 136                 if (it8172_pcibios_config_access
 137                     (PCI_ACCESS_READ, dev, where, &data))
 138                         return -1;
 139
 140                 *val = (data >> ((where & 3) << 3)) & 0xffff;
 141                 DBG("cfg read word: bus %d dev_fn %x where %x: val %x\n",
 142                     dev->bus->number, dev->devfn, where, *val);
 143
 144                 return PCIBIOS_SUCCESSFUL;
 145
 146         case 4:
 147
 148                 if (where & 3)
 149                         return PCIBIOS_BAD_REGISTER_NUMBER;
 150
 151                 if (it8172_pcibios_config_access
 152                     (PCI_ACCESS_READ, dev, where, &data))
 153                         return -1;
 154
 155                 *val = data;
 156
 157                 return PCIBIOS_SUCCESSFUL;
 158         }
 159 }
 160
 161
 162 static write_config(struct pci_bus *bus, unsigned int devfn, int where,
 163                     int size, u32 val)
 164 {
 165         u32 data = 0;
 166
 167         switch (size) {
 168         case 1:
 169                 if (it8172_pcibios_config_access
 170                     (PCI_ACCESS_READ, dev, where, &data))
 171                         return -1;
 172
 173                 data = (data & ~(0xff << ((where & 3) << 3))) |
 174                     (val << ((where & 3) << 3));
 175
 176                 if (it8172_pcibios_config_access
 177                     (PCI_ACCESS_WRITE, dev, where, &data))
 178                         return -1;
 179
 180                 return PCIBIOS_SUCCESSFUL;
 181
 182         case 2:
 183                 if (where & 1)
 184                         return PCIBIOS_BAD_REGISTER_NUMBER;
 185
 186                 if (it8172_pcibios_config_access
 187                     (PCI_ACCESS_READ, dev, where, &data))
 188                         eturn - 1;
 189
 190                 data = (data & ~(0xffff << ((where & 3) << 3))) |
 191                     (val << ((where & 3) << 3));
 192
 193                 if (it8172_pcibios_config_access
 194                     (PCI_ACCESS_WRITE, dev, where, &data))
 195                         return -1;
 196
 197                 return PCIBIOS_SUCCESSFUL;
 198
 199         case 4:
 200                 if (where & 3)
 201                         return PCIBIOS_BAD_REGISTER_NUMBER;
 202
 203                 if (it8172_pcibios_config_access
 204                     (PCI_ACCESS_WRITE, dev, where, &val))
 205                         return -1;
 206
 207                 return PCIBIOS_SUCCESSFUL;
 208         }
 209 }
 210
 211 struct pci_ops it8172_pci_ops = {
 212         .read = read_config,
 213         .write = write_config,
 214 };
 215
 216 unsigned __init int pcibios_assign_all_busses(void)
 217 {
 218         return 1;
 219 }