arch/mips/pci/ops-ev96100.c

   1 /*
   2  *
   3  * BRIEF MODULE DESCRIPTION
   4  *      Galileo EV96100 board specific pci support.
   5  *
   6  * Copyright 2000 MontaVista Software Inc.
   7  * Author: MontaVista Software, Inc.
   8  *              ppopov@mvista.com or source@mvista.com
   9  *
  10  * This file was derived from Carsten Langgaard's
  11  * arch/mips/mips-boards/generic/pci.c
  12  *
  13  * Carsten Langgaard, carstenl@mips.com
  14  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
  15  *
  16  *  This program is free software; you can redistribute  it and/or modify it
  17  *  under  the terms of  the GNU General  Public License as published by the
  18  *  Free Software Foundation;  either version 2 of the  License, or (at your
  19  *  option) any later version.
  20  *
  21  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  22  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  23  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  24  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  25  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  27  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  28  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  *  You should have received a copy of the  GNU General Public License along
  33  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  34  *  675 Mass Ave, Cambridge, MA 02139, USA.
  35  */
  36 #include <linux/types.h>
  37 #include <linux/pci.h>
  38 #include <linux/kernel.h>
  39 #include <linux/init.h>
  40
  41 #include <asm/delay.h>
  42 #include <asm                   //gt64120.h>
  43 #include <asm/galileo-boards/ev96100.h>
  44 #include <asm/pci_channel.h>
  45
  46 #define PCI_ACCESS_READ  0
  47 #define PCI_ACCESS_WRITE 1
  48
  49 #undef DEBUG
  50
  51 #ifdef DEBUG
  52 #define DBG(x...) printk(x)
  53 #else
  54 #define DBG(x...)
  55 #endif
  56
  57 #define GT_PCI_MEM_BASE    0x12000000
  58 #define GT_PCI_MEM_SIZE    0x02000000
  59 #define GT_PCI_IO_BASE     0x10000000
  60 #define GT_PCI_IO_SIZE     0x02000000
  61 static struct resource pci_io_resource = {
  62         "io pci IO space",
  63         0x10000000,
  64         0x10000000 + 0x02000000,
  65         IORESOURCE_IO
  66 };
  67
  68 static struct resource pci_mem_resource = {
  69         "ext pci memory space",
  70         0x12000000,
  71         0x12000000 + 0x02000000,
  72         IORESOURCE_MEM
  73 };
  74
  75 extern struct pci_ops gt96100_pci_ops;
  76
  77 struct pci_channel mips_pci_channels[] = {
  78         {&gt96100_pci_ops, &pci_io_resource, &pci_mem_resource, 1, 0xff},
  79         {NULL, NULL, NULL, NULL, NULL}
  80 };
  81
  82 int
  83 static gt96100_config_access(unsigned char access_type,
  84                              struct pci_dev *dev, unsigned char where,
  85                              u32 * data)
  86 {
  87         unsigned char bus = dev->bus->number;
  88         unsigned char dev_fn = dev->devfn;
  89         u32 intr;
  90
  91
  92         if ((bus == 0) && (dev_fn >= PCI_DEVFN(31, 0))) {
  93                 return -1;      /* Because of a bug in the galileo (for slot 31). */
  94         }
  95
  96         /* Clear cause register bits */
  97         GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
  98                                      GT_INTRCAUSE_TARABORT0_BIT));
  99
 100         /* Setup address */
 101         GT_WRITE(GT_PCI0_CFGADDR_OFS,
 102                  (bus << GT_PCI0_CFGADDR_BUSNUM_SHF) |
 103                  (dev_fn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
 104                  ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
 105                  GT_PCI0_CFGADDR_CONFIGEN_BIT);
 106         udelay(2);
 107
 108
 109         if (access_type == PCI_ACCESS_WRITE) {
 110                 if (dev_fn != 0) {
 111                         *data = le32_to_cpu(*data);
 112                 }
 113                 GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
 114         } else {
 115                 GT_READ(GT_PCI0_CFGDATA_OFS, *data);
 116                 if (dev_fn != 0) {
 117                         *data = le32_to_cpu(*data);
 118                 }
 119         }
 120
 121         udelay(2);
 122
 123         /* Check for master or target abort */
 124         GT_READ(GT_INTRCAUSE_OFS, intr);
 125
 126         if (intr &
 127             (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) {
 128                 //printk("config access error:  %x:%x\n", dev_fn,where);
 129                 /* Error occured */
 130
 131                 /* Clear bits */
 132                 GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
 133                                              GT_INTRCAUSE_TARABORT0_BIT));
 134
 135                 if (access_type == PCI_ACCESS_READ) {
 136                         *data = 0xffffffff;
 137                 }
 138                 return -1;
 139         }
 140         return 0;
 141 }
 142
 143
 144 /*
 145  * We can't address 8 and 16 bit words directly.  Instead we have to
 146  * read/write a 32bit word and mask/modify the data we actually want.
 147  */
 148 static int read_config_byte(struct pci_dev *dev, int where, u8 * val)
 149 {
 150         u32 data = 0;
 151
 152         if (gt96100_config_access(PCI_ACCESS_READ, dev, where, &data)) {
 153                 *val = 0xff;
 154                 return -1;
 155         }
 156
 157         *val = (data >> ((where & 3) << 3)) & 0xff;
 158         DBG("cfg read byte: bus %d dev_fn %x where %x: val %x\n",
 159             dev->bus->number, dev->devfn, where, *val);
 160
 161         return PCIBIOS_SUCCESSFUL;
 162 }
 163
 164
 165 static int read_config_word(struct pci_dev *dev, int where, u16 * val)
 166 {
 167         u32 data = 0;
 168
 169         if (where & 1)
 170                 return PCIBIOS_BAD_REGISTER_NUMBER;
 171
 172         if (gt96100_config_access(PCI_ACCESS_READ, dev, where, &data)) {
 173                 *val = 0xffff;
 174                 return -1;
 175         }
 176
 177         *val = (data >> ((where & 3) << 3)) & 0xffff;
 178         DBG("cfg read word: bus %d dev_fn %x where %x: val %x\n",
 179             dev->bus->number, dev->devfn, where, *val);
 180
 181         return PCIBIOS_SUCCESSFUL;
 182 }
 183
 184 static int read_config_dword(struct pci_dev *dev, int where, u32 * val)
 185 {
 186         u32 data = 0;
 187
 188         if (where & 3)
 189                 return PCIBIOS_BAD_REGISTER_NUMBER;
 190
 191         if (gt96100_config_access(PCI_ACCESS_READ, dev, where, &data)) {
 192                 *val = 0xffffffff;
 193                 return -1;
 194         }
 195
 196         *val = data;
 197         DBG("cfg read dword: bus %d dev_fn %x where %x: val %x\n",
 198             dev->bus->number, dev->devfn, where, *val);
 199
 200         return PCIBIOS_SUCCESSFUL;
 201 }
 202
 203
 204 static int write_config_byte(struct pci_dev *dev, int where, u8 val)
 205 {
 206         u32 data = 0;
 207
 208         if (gt96100_config_access(PCI_ACCESS_READ, dev, where, &data))
 209                 return -1;
 210
 211         data = (data & ~(0xff << ((where & 3) << 3))) |
 212             (val << ((where & 3) << 3));
 213         DBG("cfg write byte: bus %d dev_fn %x where %x: val %x\n",
 214             dev->bus->number, dev->devfn, where, val);
 215
 216         if (gt96100_config_access(PCI_ACCESS_WRITE, dev, where, &data))
 217                 return -1;
 218
 219         return PCIBIOS_SUCCESSFUL;
 220 }
 221
 222 static int write_config_word(struct pci_dev *dev, int where, u16 val)
 223 {
 224         u32 data = 0;
 225
 226         if (where & 1)
 227                 return PCIBIOS_BAD_REGISTER_NUMBER;
 228
 229         if (gt96100_config_access(PCI_ACCESS_READ, dev, where, &data))
 230                 return -1;
 231
 232         data = (data & ~(0xffff << ((where & 3) << 3))) |
 233             (val << ((where & 3) << 3));
 234         DBG("cfg write word: bus %d dev_fn %x where %x: val %x\n",
 235             dev->bus->number, dev->devfn, where, val);
 236
 237         if (gt96100_config_access(PCI_ACCESS_WRITE, dev, where, &data))
 238                 return -1;
 239
 240
 241         return PCIBIOS_SUCCESSFUL;
 242 }
 243
 244 static int write_config_dword(struct pci_dev *dev, int where, u32 val)
 245 {
 246         if (where & 3)
 247                 return PCIBIOS_BAD_REGISTER_NUMBER;
 248
 249         if (gt96100_config_access(PCI_ACCESS_WRITE, dev, where, &val))
 250                 return -1;
 251         DBG("cfg write dword: bus %d dev_fn %x where %x: val %x\n",
 252             dev->bus->number, dev->devfn, where, val);
 253
 254         return PCIBIOS_SUCCESSFUL;
 255 }
 256
 257 struct pci_ops gt96100_pci_ops = {
 258         read_config_byte,
 259         read_config_word,
 260         read_config_dword,
 261         write_config_byte,
 262         write_config_word,
 263         write_config_dword
 264 };