arch/mips/pci/ops-ev64120.c

   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  * Galileo Evaluation Boards PCI support.
   4  *
   5  * The general-purpose functions to read/write and configure the GT64120A's
   6  * PCI registers (function names start with pci0 or pci1) are either direct
   7  * copies of functions written by Galileo Technology, or are modifications
   8  * of their functions to work with Linux 2.4 vs Linux 2.2.  These functions
   9  * are Copyright - Galileo Technology.
  10  *
  11  * Other functions are derived from other MIPS PCI implementations, or were
  12  * written by RidgeRun, Inc,  Copyright (C) 2000 RidgeRun, Inc.
  13  *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
  14  *
  15  *  This program is free software; you can redistribute  it and/or modify it
  16  *  under  the terms of  the GNU General  Public License as published by the
  17  *  Free Software Foundation;  either version 2 of the  License, or (at your
  18  *  option) any later version.
  19  *
  20  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  21  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  22  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  23  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  24  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  26  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  27  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  28  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  *  You should have received a copy of the  GNU General Public License along
  32  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  33  *  675 Mass Ave, Cambridge, MA 02139, USA.
  34  */
  35 #include <linux/types.h>
  36 #include <linux/pci.h>
  37 #include <linux/kernel.h>
  38 #include <linux/slab.h>
  39 #include <linux/version.h>
  40 #include <asm/pci.h>
  41 #include <asm/io.h>
  42 #include <asm/galileo-boards/ev64120.h>
  43 #include <asm/gt64120.h>
  44
  45 #include <linux/init.h>
  46
  47 #undef PCI_DEBUG
  48
  49 #ifdef PCI_DEBUG
  50 #define DBG(x...) printk(x)
  51 #else
  52 #define DBG(x...)
  53 #endif
  54
  55 #define SELF 0
  56
  57 /*
  58  * These functions and structures provide the BIOS scan and mapping of the PCI
  59  * devices.
  60  */
  61
  62 #define MAX_PCI_DEVS 10
  63
  64 struct pci_device {
  65         u32 slot;
  66         u32 BARtype[6];
  67         u32 BARsize[6];
  68 };
  69
  70 static void __init scan_and_initialize_pci(void);
  71 static u32 __init scan_pci_bus(struct pci_device *pci_devices);
  72 static void __init allocate_pci_space(struct pci_device *pci_devices);
  73
  74 static void __devinit galileo_pcibios_fixup_bus(struct pci_bus *bus);
  75
  76 /*
  77  * The functions that actually read and write to the controller.
  78  * Copied from or modified from Galileo Technology code.
  79  */
  80 static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device);
  81 static void pci0WriteConfigReg(unsigned int offset,
  82                                struct pci_dev *device, unsigned int data);
  83 static unsigned int pci1ReadConfigReg(int offset, struct pci_dev *device);
  84 static void pci1WriteConfigReg(unsigned int offset,
  85                                struct pci_dev *device, unsigned int data);
  86
  87 static void pci0MapIOspace(unsigned int pci0IoBase,
  88                            unsigned int pci0IoLength);
  89 static void pci1MapIOspace(unsigned int pci1IoBase,
  90                            unsigned int pci1IoLength);
  91 static void pci0MapMemory0space(unsigned int pci0Mem0Base,
  92                                 unsigned int pci0Mem0Length);
  93 static void pci1MapMemory0space(unsigned int pci1Mem0Base,
  94                                 unsigned int pci1Mem0Length);
  95 static void pci0MapMemory1space(unsigned int pci0Mem1Base,
  96                                 unsigned int pci0Mem1Length);
  97 static void pci1MapMemory1space(unsigned int pci1Mem1Base,
  98                                 unsigned int pci1Mem1Length);
  99 static unsigned int pci0GetIOspaceBase(void);
 100 static unsigned int pci0GetIOspaceSize(void);
 101 static unsigned int pci0GetMemory0Base(void);
 102 static unsigned int pci0GetMemory0Size(void);
 103 static unsigned int pci0GetMemory1Base(void);
 104 static unsigned int pci0GetMemory1Size(void);
 105 static unsigned int pci1GetIOspaceBase(void);
 106 static unsigned int pci1GetIOspaceSize(void);
 107 static unsigned int pci1GetMemory0Base(void);
 108 static unsigned int pci1GetMemory0Size(void);
 109 static unsigned int pci1GetMemory1Base(void);
 110 static unsigned int pci1GetMemory1Size(void);
 111
 112
 113 /*  Functions to implement "pci ops"  */
 114 static int galileo_pcibios_read_config_word(struct pci_dev *dev,
 115                                             int offset, u16 * val);
 116 static int galileo_pcibios_read_config_byte(struct pci_dev *dev,
 117                                             int offset, u8 * val);
 118 static int galileo_pcibios_read_config_dword(struct pci_dev *dev,
 119                                              int offset, u32 * val);
 120 static int galileo_pcibios_write_config_byte(struct pci_dev *dev,
 121                                              int offset, u8 val);
 122 static int galileo_pcibios_write_config_word(struct pci_dev *dev,
 123                                              int offset, u16 val);
 124 static int galileo_pcibios_write_config_dword(struct pci_dev *dev,
 125                                               int offset, u32 val);
 126 static void galileo_pcibios_set_master(struct pci_dev *dev);
 127
 128 /*
 129  * General-purpose PCI functions.
 130  */
 131
 132 /*
 133  * pci0MapIOspace - Maps PCI0 IO space for the master.
 134  * Inputs: base and length of pci0Io
 135  */
 136 static void pci0MapIOspace(unsigned int pci0IoBase,
 137                            unsigned int pci0IoLength)
 138 {
 139         unsigned int pci0IoTop =
 140             (unsigned int) (pci0IoBase + pci0IoLength);
 141
 142         if (pci0IoLength == 0)
 143                 pci0IoTop++;
 144
 145         pci0IoBase = (unsigned int) (pci0IoBase >> 21);
 146         pci0IoTop = (unsigned int) (((pci0IoTop - 1) & 0x0fffffff) >> 21);
 147         GT_WRITE(GT_PCI0IOLD_OFS, pci0IoBase);
 148         GT_WRITE(GT_PCI0IOHD_OFS, pci0IoTop);
 149 }
 150
 151 /*
 152  * pci1MapIOspace - Maps PCI1 IO space for the master.
 153  * Inputs: base and length of pci1Io
 154  */
 155
 156 static void pci1MapIOspace(unsigned int pci1IoBase,
 157                            unsigned int pci1IoLength)
 158 {
 159         unsigned int pci1IoTop =
 160             (unsigned int) (pci1IoBase + pci1IoLength);
 161
 162         if (pci1IoLength == 0)
 163                 pci1IoTop++;
 164
 165         pci1IoBase = (unsigned int) (pci1IoBase >> 21);
 166         pci1IoTop = (unsigned int) (((pci1IoTop - 1) & 0x0fffffff) >> 21);
 167         GT_WRITE(GT_PCI1IOLD_OFS, pci1IoBase);
 168         GT_WRITE(GT_PCI1IOHD_OFS, pci1IoTop);
 169 }
 170
 171 /*
 172  * pci0MapMemory0space - Maps PCI0 memory0 space for the master.
 173  * Inputs: base and length of pci0Mem0
 174  */
 175
 176 static void pci0MapMemory0space(unsigned int pci0Mem0Base,
 177                                 unsigned int pci0Mem0Length)
 178 {
 179         unsigned int pci0Mem0Top = pci0Mem0Base + pci0Mem0Length;
 180
 181         if (pci0Mem0Length == 0)
 182                 pci0Mem0Top++;
 183
 184         pci0Mem0Base = pci0Mem0Base >> 21;
 185         pci0Mem0Top = ((pci0Mem0Top - 1) & 0x0fffffff) >> 21;
 186         GT_WRITE(GT_PCI0M0LD_OFS, pci0Mem0Base);
 187         GT_WRITE(GT_PCI0M0HD_OFS, pci0Mem0Top);
 188 }
 189
 190 /*
 191  * pci1MapMemory0space - Maps PCI1 memory0 space for the master.
 192  * Inputs: base and length of pci1Mem0
 193  */
 194
 195 static void pci1MapMemory0space(unsigned int pci1Mem0Base,
 196                                 unsigned int pci1Mem0Length)
 197 {
 198         unsigned int pci1Mem0Top = pci1Mem0Base + pci1Mem0Length;
 199
 200         if (pci1Mem0Length == 0)
 201                 pci1Mem0Top++;
 202
 203         pci1Mem0Base = pci1Mem0Base >> 21;
 204         pci1Mem0Top = ((pci1Mem0Top - 1) & 0x0fffffff) >> 21;
 205         GT_WRITE(GT_PCI1M0LD_OFS, pci1Mem0Base);
 206         GT_WRITE(GT_PCI1M0HD_OFS, pci1Mem0Top);
 207 }
 208
 209 /*
 210  * pci0MapMemory1space - Maps PCI0 memory1 space for the master.
 211  * Inputs: base and length of pci0Mem1
 212  */
 213
 214 static void pci0MapMemory1space(unsigned int pci0Mem1Base,
 215                                 unsigned int pci0Mem1Length)
 216 {
 217         unsigned int pci0Mem1Top = pci0Mem1Base + pci0Mem1Length;
 218
 219         if (pci0Mem1Length == 0)
 220                 pci0Mem1Top++;
 221
 222         pci0Mem1Base = pci0Mem1Base >> 21;
 223         pci0Mem1Top = ((pci0Mem1Top - 1) & 0x0fffffff) >> 21;
 224         GT_WRITE(GT_PCI0M1LD_OFS, pci0Mem1Base);
 225         GT_WRITE(GT_PCI0M1HD_OFS, pci0Mem1Top);
 226
 227 }
 228
 229 /*
 230  * pci1MapMemory1space - Maps PCI1 memory1 space for the master.
 231  * Inputs: base and length of pci1Mem1
 232  */
 233
 234 static void pci1MapMemory1space(unsigned int pci1Mem1Base,
 235                                 unsigned int pci1Mem1Length)
 236 {
 237         unsigned int pci1Mem1Top = pci1Mem1Base + pci1Mem1Length;
 238
 239         if (pci1Mem1Length == 0)
 240                 pci1Mem1Top++;
 241
 242         pci1Mem1Base = pci1Mem1Base >> 21;
 243         pci1Mem1Top = ((pci1Mem1Top - 1) & 0x0fffffff) >> 21;
 244         GT_WRITE(GT_PCI1M1LD_OFS, pci1Mem1Base);
 245         GT_WRITE(GT_PCI1M1HD_OFS, pci1Mem1Top);
 246 }
 247
 248 /*
 249  * pci0GetIOspaceBase - Return PCI0 IO Base Address.
 250  * Inputs: N/A
 251  * Returns: PCI0 IO Base Address.
 252  */
 253
 254 static unsigned int pci0GetIOspaceBase(void)
 255 {
 256         unsigned int base;
 257         GT_READ(GT_PCI0IOLD_OFS, &base);
 258         base = base << 21;
 259         return base;
 260 }
 261
 262 /*
 263  * pci0GetIOspaceSize - Return PCI0 IO Bar Size.
 264  * Inputs: N/A
 265  * Returns: PCI0 IO Bar Size.
 266  */
 267 static unsigned int pci0GetIOspaceSize(void)
 268 {
 269         unsigned int top, base, size;
 270         GT_READ(GT_PCI0IOLD_OFS, &base);
 271         base = base << 21;
 272         GT_READ(GT_PCI0IOHD_OFS, &top);
 273         top = (top << 21);
 274         size = ((top - base) & 0xfffffff);
 275         size = size | 0x1fffff;
 276         return (size + 1);
 277 }
 278
 279 /*
 280  * pci0GetMemory0Base - Return PCI0 Memory 0 Base Address.
 281  * Inputs: N/A
 282  * Returns: PCI0 Memory 0 Base Address.
 283  */
 284 static unsigned int pci0GetMemory0Base(void)
 285 {
 286         unsigned int base;
 287         GT_READ(GT_PCI0M0LD_OFS, &base);
 288         base = base << 21;
 289         return base;
 290 }
 291
 292 /*
 293  * pci0GetMemory0Size - Return PCI0 Memory 0 Bar Size.
 294  * Inputs: N/A
 295  * Returns: PCI0 Memory 0 Bar Size.
 296  */
 297 static unsigned int pci0GetMemory0Size(void)
 298 {
 299         unsigned int top, base, size;
 300         GT_READ(GT_PCI0M0LD_OFS, &base);
 301         base = base << 21;
 302         GT_READ(GT_PCI0M0HD_OFS, &top);
 303         top = (top << 21);
 304         size = ((top - base) & 0xfffffff);
 305         size = size | 0x1fffff;
 306         return (size + 1);
 307 }
 308
 309 /*
 310  * pci0GetMemory1Base - Return PCI0 Memory 1 Base Address.
 311  * Inputs: N/A
 312  * Returns: PCI0 Memory 1 Base Address.
 313  */
 314 static unsigned int pci0GetMemory1Base(void)
 315 {
 316         unsigned int base;
 317         GT_READ(GT_PCI0M1LD_OFS, &base);
 318         base = base << 21;
 319         return base;
 320 }
 321
 322 /*
 323  * pci0GetMemory1Size - Return PCI0 Memory 1 Bar Size.
 324  * Inputs: N/A
 325  * Returns: PCI0 Memory 1 Bar Size.
 326  */
 327
 328 static unsigned int pci0GetMemory1Size(void)
 329 {
 330         unsigned int top, base, size;
 331         GT_READ(GT_PCI0M1LD_OFS, &base);
 332         base = base << 21;
 333         GT_READ(GT_PCI0M1HD_OFS, &top);
 334         top = (top << 21);
 335         size = ((top - base) & 0xfffffff);
 336         size = size | 0x1fffff;
 337         return (size + 1);
 338 }
 339
 340 /*
 341  * pci1GetIOspaceBase - Return PCI1 IO Base Address.
 342  * Inputs: N/A
 343  * Returns: PCI1 IO Base Address.
 344  */
 345
 346 static unsigned int pci1GetIOspaceBase(void)
 347 {
 348         unsigned int base;
 349         GT_READ(GT_PCI1IOLD_OFS, &base);
 350         base = base << 21;
 351         return base;
 352 }
 353
 354 /*
 355  * pci1GetIOspaceSize - Return PCI1 IO Bar Size.
 356  * Inputs: N/A
 357  * Returns: PCI1 IO Bar Size.
 358  */
 359
 360 static unsigned int pci1GetIOspaceSize(void)
 361 {
 362         unsigned int top, base, size;
 363         GT_READ(GT_PCI1IOLD_OFS, &base);
 364         base = base << 21;
 365         GT_READ(GT_PCI1IOHD_OFS, &top);
 366         top = (top << 21);
 367         size = ((top - base) & 0xfffffff);
 368         size = size | 0x1fffff;
 369         return (size + 1);
 370 }
 371
 372 /*
 373  * pci1GetMemory0Base - Return PCI1 Memory 0 Base Address.
 374  * Inputs: N/A
 375  * Returns: PCI1 Memory 0 Base Address.
 376  */
 377
 378 static unsigned int pci1GetMemory0Base(void)
 379 {
 380         unsigned int base;
 381         GT_READ(GT_PCI1M0LD_OFS, &base);
 382         base = base << 21;
 383         return base;
 384 }
 385
 386 /*
 387  * pci1GetMemory0Size - Return PCI1 Memory 0 Bar Size.
 388  * Inputs: N/A
 389  * Returns: PCI1 Memory 0 Bar Size.
 390  */
 391
 392 static unsigned int pci1GetMemory0Size(void)
 393 {
 394         unsigned int top, base, size;
 395         GT_READ(GT_PCI1M1LD_OFS, &base);
 396         base = base << 21;
 397         GT_READ(GT_PCI1M1HD_OFS, &top);
 398         top = (top << 21);
 399         size = ((top - base) & 0xfffffff);
 400         size = size | 0x1fffff;
 401         return (size + 1);
 402 }
 403
 404 /*
 405  * pci1GetMemory1Base - Return PCI1 Memory 1 Base Address.
 406  * Inputs: N/A
 407  * Returns: PCI1 Memory 1 Base Address.
 408  */
 409
 410 static unsigned int pci1GetMemory1Base(void)
 411 {
 412         unsigned int base;
 413         GT_READ(GT_PCI1M1LD_OFS, &base);
 414         base = base << 21;
 415         return base;
 416 }
 417
 418 /*
 419  * pci1GetMemory1Size - Return PCI1 Memory 1 Bar Size.
 420  * Inputs: N/A
 421  * Returns: PCI1 Memory 1 Bar Size.
 422  */
 423
 424 static unsigned int pci1GetMemory1Size(void)
 425 {
 426         unsigned int top, base, size;
 427         GT_READ(GT_PCI1M1LD_OFS, &base);
 428         base = base << 21;
 429         GT_READ(GT_PCI1M1HD_OFS, &top);
 430         top = (top << 21);
 431         size = ((top - base) & 0xfffffff);
 432         size = size | 0x1fffff;
 433         return (size + 1);
 434 }
 435
 436
 437
 438 /*
 439  * pci_range_ck -
 440  *
 441  * Check if the pci device that are trying to access does really exists
 442  * on the evaluation board.
 443  *
 444  * Inputs :
 445  * bus - bus number (0 for PCI 0 ; 1 for PCI 1)
 446  * dev - number of device on the specific pci bus
 447  *
 448  * Outpus :
 449  * 0 - if OK , 1 - if failure
 450  */
 451 static __inline__ int pci_range_ck(unsigned char bus, unsigned char dev)
 452 {
 453         //DBG(KERN_INFO "p_r_c %d %d\n",bus,dev);
 454         if (((bus == 0) || (bus == 1)) && (dev >= 6) && (dev <= 8))
 455                 return 0;       // Bus/Device Number OK
 456         return -1;              // Bus/Device Number not OK
 457 }
 458
 459 /*
 460  * pciXReadConfigReg  - Read from a PCI configuration register
 461  *                    - Make sure the GT is configured as a master before
 462  *                      reading from another device on the PCI.
 463  *                   - The function takes care of Big/Little endian conversion.
 464  * INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
 465  *                        spec)
 466  *           pciDevNum: The device number needs to be addressed.
 467  * RETURNS: data , if the data == 0xffffffff check the master abort bit in the
 468  *                 cause register to make sure the data is valid
 469  *
 470  *  Configuration Address 0xCF8:
 471  *
 472  *       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
 473  *  |congif|Reserved|  Bus |Device|Function|Register|00|
 474  *  |Enable|        |Number|Number| Number | Number |  |    <=field Name
 475  *
 476  */
 477 static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device)
 478 {
 479         unsigned int DataForRegCf8;
 480         unsigned int data;
 481
 482         DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
 483                          (PCI_FUNC(device->devfn) << 8) |
 484                          (offset & ~0x3)) | 0x80000000;
 485         GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
 486
 487         /*  The casual observer might wonder why the READ is duplicated here,
 488            rather than immediately following the WRITE, and just have the
 489            swap in the "if".  That's because there is a latency problem
 490            with trying to read immediately after setting up the address
 491            register.  The "if" check gives enough time for the address
 492            to stabilize, so the READ can work.
 493          */
 494         if (PCI_SLOT(device->devfn) == SELF) {  /* This board */
 495                 GT_READ(GT_PCI0_CFGDATA_OFS, &data);
 496                 return data;
 497         } else {                /* The PCI is working in LE Mode so swap the Data. */
 498                 GT_READ(GT_PCI0_CFGDATA_OFS, &data);
 499                 return cpu_to_le32(data);
 500         }
 501 }
 502
 503 static unsigned int pci1ReadConfigReg(int offset, struct pci_dev *device)
 504 {
 505         unsigned int DataForRegCf8;
 506         unsigned int data;
 507
 508         DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
 509                          (PCI_FUNC(device->devfn) << 8) |
 510                          (offset & ~0x3)) | 0x80000000;
 511         /*  The casual observer might wonder why the READ is duplicated here,
 512            rather than immediately following the WRITE, and just have the
 513            swap in the "if".  That's because there is a latency problem
 514            with trying to read immediately after setting up the address
 515            register.  The "if" check gives enough time for the address
 516            to stabilize, so the READ can work.
 517          */
 518         if (PCI_SLOT(device->devfn) == SELF) {  /* This board */
 519                 /* when configurating our own PCI 1 L-unit the access is through
 520                    the PCI 0 interface with reg number = reg number + 0x80 */
 521                 DataForRegCf8 |= 0x80;
 522                 GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
 523         } else {                /* The PCI is working in LE Mode so swap the Data. */
 524                 GT_WRITE(GT_PCI1_CFGADDR_OFS, DataForRegCf8);
 525         }
 526         if (PCI_SLOT(device->devfn) == SELF) {  /* This board */
 527                 GT_READ(GT_PCI0_CFGDATA_OFS, &data);
 528                 return data;
 529         } else {
 530                 GT_READ(GT_PCI1_CFGDATA_OFS, &data);
 531                 return cpu_to_le32(data);
 532         }
 533 }
 534
 535
 536
 537 /*
 538  * pciXWriteConfigReg - Write to a PCI configuration register
 539  *                    - Make sure the GT is configured as a master before
 540  *                      writingto another device on the PCI.
 541  *                    - The function takes care of Big/Little endian conversion.
 542  * Inputs:   unsigned int regOffset: The register offset as it apears in the
 543  *           GT spec
 544  *                   (or any other PCI device spec)
 545  *           pciDevNum: The device number needs to be addressed.
 546  *
 547  *  Configuration Address 0xCF8:
 548  *
 549  *       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
 550  *  |congif|Reserved|  Bus |Device|Function|Register|00|
 551  *  |Enable|        |Number|Number| Number | Number |  |    <=field Name
 552  *
 553  */
 554 static void pci0WriteConfigReg(unsigned int offset,
 555                                struct pci_dev *device, unsigned int data)
 556 {
 557         unsigned int DataForRegCf8;
 558
 559         DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
 560                          (PCI_FUNC(device->devfn) << 8) |
 561                          (offset & ~0x3)) | 0x80000000;
 562         GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
 563         if (PCI_SLOT(device->devfn) == SELF) {  /* This board */
 564                 GT_WRITE(GT_PCI0_CFGDATA_OFS, data);
 565         } else {                /* configuration Transaction over the pci. */
 566                 /* The PCI is working in LE Mode so swap the Data. */
 567                 GT_WRITE(GT_PCI0_CFGDATA_OFS, le32_to_cpu(data));
 568         }
 569 }
 570
 571 static void pci1WriteConfigReg(unsigned int offset,
 572                                struct pci_dev *device, unsigned int data)
 573 {
 574         unsigned int DataForRegCf8;
 575
 576         DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
 577                          (PCI_FUNC(device->devfn) << 8) |
 578                          (offset & ~0x3)) | 0x80000000;
 579         /*  There is a latency problem
 580            with trying to read immediately after setting up the address
 581            register.  The "if" check gives enough time for the address
 582            to stabilize, so the WRITE can work.
 583          */
 584         if (PCI_SLOT(device->devfn) == SELF) {  /* This board */
 585                 /* when configurating our own PCI 1 L-unit the access is through
 586                    the PCI 0 interface with reg number = reg number + 0x80 */
 587                 DataForRegCf8 |= 0x80;
 588                 GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
 589         } else {                /* configuration Transaction over the pci. */
 590                 /* The PCI is working in LE Mode so swap the Data. */
 591                 GT_WRITE(GT_PCI1_CFGADDR_OFS, DataForRegCf8);
 592         }
 593         if (PCI_SLOT(device->devfn) == SELF) {  /* This board */
 594                 GT_WRITE(GT_PCI0_CFGDATA_OFS, data);
 595         } else {                /* configuration Transaction over the pci. */
 596                 GT_WRITE(GT_PCI1_CFGADDR_OFS, le32_to_cpu(data));
 597         }
 598 }
 599
 600
 601 /*
 602  * galileo_pcibios_(read/write)_config_(dword/word/byte) -
 603  *
 604  * reads/write a dword/word/byte register from the configuration space
 605  * of a device.
 606  *
 607  * Inputs :
 608  * bus - bus number
 609  * dev - device number
 610  * offset - register offset in the configuration space
 611  * val - value to be written / read
 612  *
 613  * Outputs :
 614  * PCIBIOS_SUCCESSFUL when operation was succesfull
 615  * PCIBIOS_DEVICE_NOT_FOUND when the bus or dev is errorneous
 616  * PCIBIOS_BAD_REGISTER_NUMBER when accessing non aligned
 617  */
 618
 619 static int galileo_pcibios_read_config_dword(struct pci_dev *device,
 620                                              int offset, u32 * val)
 621 {
 622         int dev, bus;
 623         //DBG(KERN_INFO "rcd entry \n",offset,val);
 624         bus = device->bus->number;
 625         dev = PCI_SLOT(device->devfn);
 626
 627         if (pci_range_ck(bus, dev)) {
 628                 *val = 0xffffffff;
 629                 return PCIBIOS_DEVICE_NOT_FOUND;
 630         }
 631         if (offset & 0x3)
 632                 return PCIBIOS_BAD_REGISTER_NUMBER;
 633         if (bus == 0)
 634                 *val = pci0ReadConfigReg(offset, device);
 635 //  if (bus == 1) *val = pci1ReadConfigReg (offset,device);
 636         DBG(KERN_INFO "rr: rcd dev %d offset %x %x\n", dev, offset, *val);
 637
 638         /*
 639          * This is so that the upper PCI layer will get the correct return
 640          * value if we're not attached to anything.
 641          */
 642         if ((offset == 0) && (*val == 0xffffffff)) {
 643                 return PCIBIOS_DEVICE_NOT_FOUND;
 644         }
 645
 646         return PCIBIOS_SUCCESSFUL;
 647 }
 648
 649 static int galileo_pcibios_read_config_word(struct pci_dev *device,
 650                                             int offset, u16 * val)
 651 {
 652         int dev, bus;
 653
 654         bus = device->bus->number;
 655         dev = PCI_SLOT(device->devfn);
 656
 657         if (pci_range_ck(bus, dev)) {
 658                 *val = 0xffff;
 659                 return PCIBIOS_DEVICE_NOT_FOUND;
 660         }
 661         if (offset & 0x1)
 662                 return PCIBIOS_BAD_REGISTER_NUMBER;
 663
 664         if (bus == 0)
 665                 *val =
 666                     (unsigned short) (pci0ReadConfigReg(offset, device) >>
 667                                       ((offset & ~0x3) * 8));
 668 //  if (bus == 1) *val = (unsigned short) (pci1ReadConfigReg(offset,device) >> ((offset & ~0x3) * 8));
 669
 670         DBG(KERN_INFO "rr: rcw dev %d offset %x %x\n", dev, offset, *val);
 671
 672         return PCIBIOS_SUCCESSFUL;
 673 }
 674
 675 static int galileo_pcibios_read_config_byte(struct pci_dev *device,
 676                                             int offset, u8 * val)
 677 {
 678         int dev, bus;
 679
 680         bus = device->bus->number;
 681         dev = PCI_SLOT(device->devfn);
 682
 683         if (pci_range_ck(bus, dev)) {
 684                 *val = 0xff;
 685                 return PCIBIOS_DEVICE_NOT_FOUND;
 686         }
 687
 688         if (bus == 0)
 689                 *val =
 690                     (unsigned char) (pci0ReadConfigReg(offset, device) >>
 691                                      ((offset & ~0x3) * 8));
 692 //  if (bus == 1) *val = (unsigned char) (pci1ReadConfigReg(offset,device) >> ((offset & ~0x3) * 8));
 693
 694         DBG(KERN_INFO "rr: rcb dev %d offset %x %x\n", dev, offset, *val);
 695
 696         /*  This is so that the upper PCI layer will get the correct return value if
 697            we're not attached to anything.  */
 698         if ((offset == 0xe) && (*val == 0xff)) {
 699                 u32 MasterAbort;
 700                 GT_READ(GT_INTRCAUSE_OFS, &MasterAbort);
 701                 if (MasterAbort & 0x40000) {
 702                         DBG(KERN_INFO "PCI Master Abort, ICR %x\n",
 703                             MasterAbort);
 704                         GT_WRITE(GT_INTRCAUSE_OFS,
 705                                  (MasterAbort & 0xfffbffff));
 706                         return PCIBIOS_DEVICE_NOT_FOUND;
 707                 }
 708         }
 709
 710         return PCIBIOS_SUCCESSFUL;
 711 }
 712
 713 static int galileo_pcibios_write_config_dword(struct pci_dev *device,
 714                                               int offset, u32 val)
 715 {
 716         int dev, bus;
 717
 718         bus = device->bus->number;
 719         dev = PCI_SLOT(device->devfn);
 720
 721         if (pci_range_ck(bus, dev))
 722                 return PCIBIOS_DEVICE_NOT_FOUND;
 723         if (offset & 0x3)
 724                 return PCIBIOS_BAD_REGISTER_NUMBER;
 725         if (bus == 0)
 726                 pci0WriteConfigReg(offset, device, val);
 727 //  if (bus == 1) pci1WriteConfigReg (offset,device,val);
 728
 729         DBG(KERN_INFO "rr: wcd dev %d, offset %x, val %x\n", dev, offset,
 730             val);
 731         return PCIBIOS_SUCCESSFUL;
 732 }
 733
 734
 735 static int galileo_pcibios_write_config_word(struct pci_dev *device,
 736                                              int offset, u16 val)
 737 {
 738         int dev, bus;
 739         unsigned long tmp;
 740
 741         bus = device->bus->number;
 742         dev = PCI_SLOT(device->devfn);
 743
 744         if (pci_range_ck(bus, dev))
 745                 return PCIBIOS_DEVICE_NOT_FOUND;
 746         if (offset & 0x1)
 747                 return PCIBIOS_BAD_REGISTER_NUMBER;
 748         if (bus == 0)
 749                 tmp = pci0ReadConfigReg(offset, device);
 750 //  if (bus == 1) tmp = pci1ReadConfigReg (offset,device);
 751
 752         if ((offset % 4) == 0)
 753                 tmp = (tmp & 0xffff0000) | (val & 0xffff);
 754         if ((offset % 4) == 2)
 755                 tmp = (tmp & 0x0000ffff) | ((val & 0xffff) << 16);
 756
 757         if (bus == 0)
 758                 pci0WriteConfigReg(offset, device, tmp);
 759 //  if (bus == 1) pci1WriteConfigReg (offset,device,tmp);
 760         DBG(KERN_INFO "rr: wcw dev %d, offset %x, val %x\n", dev, offset,
 761             val);
 762         return PCIBIOS_SUCCESSFUL;
 763 }
 764
 765 static int galileo_pcibios_write_config_byte(struct pci_dev *device,
 766                                              int offset, u8 val)
 767 {
 768         int dev, bus;
 769         unsigned long tmp;
 770
 771         bus = device->bus->number;
 772         dev = PCI_SLOT(device->devfn);
 773
 774         if (pci_range_ck(bus, dev))
 775                 return PCIBIOS_DEVICE_NOT_FOUND;
 776         if (bus == 0)
 777                 tmp = pci0ReadConfigReg(offset, device);
 778 //  if (bus == 1) tmp = pci1ReadConfigReg (offset,device);
 779
 780         if ((offset % 4) == 0)
 781                 tmp = (tmp & 0xffffff00) | (val & 0xff);
 782         if ((offset % 4) == 1)
 783                 tmp = (tmp & 0xffff00ff) | ((val & 0xff) << 8);
 784         if ((offset % 4) == 2)
 785                 tmp = (tmp & 0xff00ffff) | ((val & 0xff) << 16);
 786         if ((offset % 4) == 3)
 787                 tmp = (tmp & 0x00ffffff) | ((val & 0xff) << 24);
 788
 789         if (bus == 0)
 790                 pci0WriteConfigReg(offset, device, tmp);
 791 //  if (bus == 1) pci1WriteConfigReg (offset,device,tmp);
 792         DBG(KERN_INFO "rr: wcb dev %d, offset %x, val %x\n", dev, offset,
 793             val);
 794
 795         return PCIBIOS_SUCCESSFUL;
 796 }
 797
 798 static void galileo_pcibios_set_master(struct pci_dev *dev)
 799 {
 800         u16 cmd;
 801
 802         DBG(KERN_INFO "rr: galileo_pcibios_set_master\n");
 803
 804         galileo_pcibios_read_config_word(dev, PCI_COMMAND, &cmd);
 805         cmd |= PCI_COMMAND_MASTER;
 806         galileo_pcibios_write_config_word(dev, PCI_COMMAND, cmd);
 807         DBG("PCI: Enabling device %s (%04x)\n", dev->slot_name, cmd);
 808 }
 809
 810 /*  Externally-expected functions.  Do not change function names  */
 811
 812 int pcibios_enable_resources(struct pci_dev *dev)
 813 {
 814         u16 cmd, old_cmd;
 815         u16 tmp;
 816         u8 tmp1;
 817         int idx;
 818         struct resource *r;
 819
 820         DBG(KERN_INFO "rr: pcibios_enable_resources\n");
 821
 822         galileo_pcibios_read_config_word(dev, PCI_COMMAND, &cmd);
 823         old_cmd = cmd;
 824         for (idx = 0; idx < 6; idx++) {
 825                 r = &dev->resource[idx];
 826                 DBG(KERN_INFO
 827                     "rr: BAR %d, start %lx, end %lx, flags %lx\n", idx,
 828                     r->start, r->end, r->flags);
 829                 if (!r->start && r->end) {
 830                         printk(KERN_ERR
 831                                "PCI: Device %s not available because of resource collisions\n",
 832                                dev->slot_name);
 833                         return -EINVAL;
 834                 }
 835                 if (r->flags & IORESOURCE_IO)
 836                         cmd |= PCI_COMMAND_IO;
 837                 if (r->flags & IORESOURCE_MEM)
 838                         cmd |= PCI_COMMAND_MEMORY;
 839         }
 840         if (cmd != old_cmd) {
 841                 DBG(KERN_INFO "PCI: Enabling device %s (%04x -> %04x)\n",
 842                     dev->slot_name, old_cmd, cmd);
 843                 galileo_pcibios_write_config_word(dev, PCI_COMMAND, cmd);
 844         }
 845
 846         /*
 847            Let's fix up the latency timer and cache line size here.  Cache line size =
 848            32 bytes / sizeof dword (4) = 8.
 849            Latency timer must be > 8.  32 is random but appears to work.
 850          */
 851         galileo_pcibios_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp1);
 852         if (tmp1 != 8) {
 853                 DBG(KERN_INFO
 854                     "rr: PCI setting cache line size to 8 from %d\n",
 855                     tmp1);
 856                 galileo_pcibios_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
 857                                                   8);
 858         }
 859         galileo_pcibios_read_config_byte(dev, PCI_LATENCY_TIMER, &tmp1);
 860         if (tmp1 < 32) {
 861                 DBG(KERN_INFO
 862                     "rr: PCI setting latency timer to 32 from %d\n", tmp1);
 863                 galileo_pcibios_write_config_byte(dev, PCI_LATENCY_TIMER,
 864                                                   32);
 865         }
 866
 867         return 0;
 868 }
 869
 870 int pcibios_enable_device(struct pci_dev *dev, int mask)
 871 {
 872         DBG(KERN_INFO "rr: pcibios_enable_device\n");
 873         return pcibios_enable_resources(dev);
 874 }
 875
 876 void pcibios_align_resource(void *data, struct resource *res,
 877                             unsigned long size, unsigned long align)
 878 {
 879         if (res->flags & IORESOURCE_IO) {
 880                 unsigned long start = res->start;
 881
 882                 /* We need to avoid collisions with `mirrored' VGA ports
 883                    and other strange ISA hardware, so we always want the
 884                    addresses kilobyte aligned.  */
 885                 if (size > 0x100) {
 886                         DBG(KERN_ERR "PCI: I/O Region %s/%d too large"
 887                             " (%ld bytes)\n", dev->slot_name,
 888                             dev->resource - res, size);
 889                 }
 890
 891                 start = (start + 1024 - 1) & ~(1024 - 1);
 892                 res->start = start;
 893         }
 894 }
 895
 896 /*
 897  * structure galileo_pci_ops
 898  *
 899  * This structure holds the pointers for the PCI configuration space
 900  * access, and the fixup for the interrupts.
 901  * This structure is registered to the operating system in boot time
 902  */
 903 struct pci_ops galileo_pci_ops = {
 904         galileo_pcibios_read_config_byte,
 905         galileo_pcibios_read_config_word,
 906         galileo_pcibios_read_config_dword,
 907         galileo_pcibios_write_config_byte,
 908         galileo_pcibios_write_config_word,
 909         galileo_pcibios_write_config_dword
 910 };
 911
 912 /*
 913  * galileo_pcibios_fixup_bus -
 914  *
 915  * After detecting all agents over the PCI , this function is called
 916  * in order to give an interrupt number for each PCI device starting
 917  * from IRQ 20. It does also enables master for each device.
 918  *
 919  * Inputs :
 920  * mem_start , mem_end are not relevant in MIPS architecture.
 921  *
 922  * Outpus :
 923  * return always mem_start
 924  */
 925 static void __devinit galileo_pcibios_fixup_bus(struct pci_bus *bus)
 926 {
 927         unsigned int Current_IRQ = 20;
 928         struct pci_bus *current_bus = bus;
 929         struct pci_dev *devices;
 930         struct list_head *devices_link;
 931
 932         list_for_each(devices_link, &(current_bus->devices)) {
 933                 devices = pci_dev_b(devices_link);
 934                 if (devices != NULL) {
 935                         devices->irq = Current_IRQ++;
 936
 937                         /* Assign an interrupt number for the device */
 938                         galileo_pcibios_write_config_byte(devices,
 939                                                           PCI_INTERRUPT_LINE,
 940                                                           Current_IRQ);
 941                         galileo_pcibios_set_master(devices);
 942
 943                 }
 944         }
 945
 946 }
 947
 948 struct pci_fixup pcibios_fixups[] = {
 949 //    { PCI_FIXUP_HEADER, 0x4620, 0x11ab, galileo_pcibios_fixup },
 950         {0}
 951 };
 952
 953 void __devinit pcibios_fixup_bus(struct pci_bus *c)
 954 {
 955         DBG(KERN_INFO "rr: pcibios_fixup_bus\n");
 956         galileo_pcibios_fixup_bus(c);
 957 }
 958
 959 /*
 960  * This code was derived from Galileo Technology's example
 961  * and significantly reworked.
 962  *
 963  * This is very simple.  It does not scan multiple function devices.  It does
 964  * not scan behind bridges.  Those would be simple to implement, but we don't
 965  * currently need this.
 966  */
 967 static void __init scan_and_initialize_pci(void)
 968 {
 969         struct pci_device pci_devices[MAX_PCI_DEVS];
 970
 971         if (scan_pci_bus(pci_devices)) {
 972                 allocate_pci_space(pci_devices);
 973         }
 974 }
 975
 976 /*
 977  * This is your basic PCI scan.  It goes through each slot and checks to
 978  * see if there's something that responds.  If so, then get the size and
 979  * type of each of the responding BARs.  Save them for later.
 980  */
 981
 982 static u32 __init scan_pci_bus(struct pci_device *pci_devices)
 983 {
 984         u32 arrayCounter = 0;
 985         u32 memType;
 986         u32 memSize;
 987         u32 pci_slot, bar;
 988         u32 id;
 989         u32 c18RegValue;
 990         struct pci_dev device;
 991
 992         DBG(KERN_INFO "rr: scan_pci_bus\n");
 993
 994         /*
 995            According to PCI REV 2.1 MAX agents on the bus are 21.
 996            We don't bother scanning ourselves (slot 0).
 997          */
 998         for (pci_slot = 1; pci_slot < 22; pci_slot++) {
 999
1000                 device.devfn = PCI_DEVFN(pci_slot, 0);
1001                 id = pci0ReadConfigReg(PCI_VENDOR_ID, &device);
1002
1003                 /*  Check for a PCI Master Abort (nothing responds in the slot) */
1004                 GT_READ(GT_INTRCAUSE_OFS, &c18RegValue);
1005                 /* Clearing bit 18 of in the Cause Register 0xc18 by writting 0. */
1006                 GT_WRITE(GT_INTRCAUSE_OFS, (c18RegValue & 0xfffbffff));
1007                 if ((id != 0xffffffff) && !(c18RegValue & 0x40000)) {
1008                         DBG(KERN_INFO "rr: found device %x, slot %d\n", id,
1009                             pci_slot);
1010                         pci_devices[arrayCounter].slot = pci_slot;
1011                         for (bar = 0; bar < 6; bar++) {
1012                                 memType =
1013                                     pci0ReadConfigReg(PCI_BASE_ADDRESS_0 +
1014                                                       (bar * 4), &device);
1015                                 pci_devices[arrayCounter].BARtype[bar] =
1016                                     memType & 1;
1017                                 pci0WriteConfigReg(PCI_BASE_ADDRESS_0 +
1018                                                    (bar * 4), &device,
1019                                                    0xffffffff);
1020                                 memSize =
1021                                     pci0ReadConfigReg(PCI_BASE_ADDRESS_0 +
1022                                                       (bar * 4), &device);
1023                                 if (memType & 1) {      /*  IO space  */
1024                                         pci_devices[arrayCounter].
1025                                             BARsize[bar] =
1026                                             ~(memSize & 0xfffffffc) + 1;
1027                                 } else {        /*  memory space */
1028                                         pci_devices[arrayCounter].
1029                                             BARsize[bar] =
1030                                             ~(memSize & 0xfffffff0) + 1;
1031                                 }
1032                                 DBG(KERN_INFO
1033                                     "rr: BAR %d, type %d, size %x\n", bar,
1034                                     (memType & 1),
1035                                     pci_devices[arrayCounter].
1036                                     BARsize[bar]);
1037                         }       /*  BAR counter  */
1038
1039                         arrayCounter++;
1040                 }
1041                 /*  found a device  */
1042         }                       /*  slot counter  */
1043
1044         DBG(KERN_INFO "rr: found %d devices\n", arrayCounter);
1045         if (arrayCounter < MAX_PCI_DEVS) {
1046                 pci_devices[arrayCounter].slot = -1;
1047         }
1048         return (arrayCounter);
1049 }
1050
1051 #define ALIGN(val,align)        (((val) + ((align) - 1)) & ~((align) - 1))
1052 #define MAX(val1, val2) ((val1) > (val2) ? (val1) : (val2))
1053
1054 /*
1055  * This function goes through the list of devices and allocates the BARs in
1056  * either IO or MEM space.  It does it in order of size, which will limit the
1057  * amount of fragmentation we have in the IO and MEM spaces.
1058  */
1059
1060 static void __init allocate_pci_space(struct pci_device *pci_devices)
1061 {
1062         u32 count, maxcount, bar;
1063         u32 maxSize, maxDevice, maxBAR;
1064         u32 alignto;
1065         u32 base;
1066         u32 pci0_mem_base = pci0GetMemory0Base();
1067         u32 pci0_io_base = pci0GetIOspaceBase();
1068         struct pci_dev device;
1069
1070         DBG(KERN_INFO "rr: allocate_pci_space\n");
1071
1072         DBG(KERN_INFO "pci0_io_base %x\n", pci0_io_base);
1073         DBG(KERN_INFO "pci0_mem_base %x\n", pci0_mem_base);
1074
1075         /*  How many PCI devices do we have?  */
1076         maxcount = MAX_PCI_DEVS;
1077         for (count = 0; count < MAX_PCI_DEVS; count++) {
1078                 if (pci_devices[count].slot == -1) {
1079                         maxcount = count;
1080                         break;
1081                 }
1082         }
1083
1084 //    DBG(KERN_INFO "Found %d devices\n", maxcount);
1085
1086         do {
1087                 /*  Find the largest size BAR we need to allocate  */
1088                 maxSize = 0;
1089                 for (count = 0; count < maxcount; count++) {
1090                         for (bar = 0; bar < 6; bar++) {
1091                                 if (pci_devices[count].BARsize[bar] >
1092                                     maxSize) {
1093                                         maxSize =
1094                                             pci_devices[count].
1095                                             BARsize[bar];
1096                                         maxDevice = count;
1097                                         maxBAR = bar;
1098                                 }
1099                         }
1100                 }
1101
1102                 /*
1103                    We've found the largest BAR.  Allocate it into IO or
1104                    mem space.  We don't idiot check the bases to make
1105                    sure they haven't overflowed the current size for that aperture.
1106
1107                    Don't bother to enable the device's IO or MEM space here.  That will
1108                    be done in pci_enable_resources if the device is activated by a driver.
1109                  */
1110                 if (maxSize) {
1111                         device.devfn =
1112                             PCI_DEVFN(pci_devices[maxDevice].slot, 0);
1113                         if (pci_devices[maxDevice].BARtype[maxBAR] == 1) {
1114                                 alignto = MAX(0x1000, maxSize);
1115                                 base = ALIGN(pci0_io_base, alignto);
1116                                 pci0WriteConfigReg(PCI_BASE_ADDRESS_0 +
1117                                                    (maxBAR * 4), &device,
1118                                                    base | 0x1);
1119                                 pci0_io_base = base + alignto;
1120                                 DBG(KERN_INFO
1121                                     "Device %d BAR %d address %x\n",
1122                                     pci_devices[maxDevice].slot, maxBAR,
1123                                     base);
1124                                 DBG(KERN_INFO "New IO base %x\n",
1125                                     pci0_io_base);
1126                         } else {
1127                                 alignto = MAX(0x1000, maxSize);
1128                                 base = ALIGN(pci0_mem_base, alignto);
1129                                 pci0WriteConfigReg(PCI_BASE_ADDRESS_0 +
1130                                                    (maxBAR * 4), &device,
1131                                                    base);
1132                                 pci0_mem_base = base + alignto;
1133                                 DBG(KERN_INFO
1134                                     "Device %d BAR %d address %x\n",
1135                                     pci_devices[maxDevice].slot, maxBAR,
1136                                     base);
1137                                 DBG(KERN_INFO "New mem base %x\n",
1138                                     pci0_mem_base);
1139                         }
1140                         /*
1141                            This entry is finished.  Remove it from the list we'll scan.
1142                          */
1143                         pci_devices[maxDevice].BARsize[maxBAR] = 0;
1144                 }
1145         } while (maxSize);
1146 }
1147
1148 unsigned __init int pcibios_assign_all_busses(void)
1149 {
1150         return 1;
1151 }
1152
1153 static int __init pcibios_init(void)
1154 {
1155
1156         u32 tmp;
1157         struct pci_dev controller;
1158
1159         controller.devfn = SELF;
1160
1161         DBG(KERN_INFO "rr: pcibios_init\n");
1162         GT_READ(GT_PCI0_CMD_OFS, &tmp);
1163         DBG(KERN_INFO "rr: PCI0 command - %x\n", tmp);
1164         GT_READ(GT_PCI0_BARE_OFS, &tmp);
1165         DBG(KERN_INFO "rr: BAR0 - %x\n", tmp);
1166
1167         /*
1168          * You have to enable bus mastering to configure any other
1169          * card on the bus.
1170          */
1171         tmp = pci0ReadConfigReg(PCI_COMMAND, &controller);
1172         DBG(KERN_INFO "rr: command/status - %x\n", tmp);
1173         tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
1174         DBG(KERN_INFO "rr: new command/status - %x\n", tmp);
1175         pci0WriteConfigReg(PCI_COMMAND, &controller, tmp);
1176
1177         /*  This scans the PCI bus and sets up initial values.  */
1178         scan_and_initialize_pci();
1179
1180         /*
1181          * Reset PCI I/O and PCI MEM values to ones supported by EVM.
1182          */
1183         ioport_resource.start = 0x10000000;
1184         ioport_resource.end = 0x11ffffff;       /*  32 MB */
1185         iomem_resource.start = 0x12000000;
1186         iomem_resource.end = 0x13ffffff;        /* 32 MB */
1187
1188         pci_scan_bus(0, &galileo_pci_ops, NULL);
1189
1190         return 0;
1191 }
1192
1193 subsys_initcall(pcibios_init);
1194
1195 char *pcibios_setup(char *str)
1196 {
1197         printk(KERN_INFO "rr: pcibios_setup\n");
1198         /* Nothing to do for now.  */
1199
1200         return str;
1201 }