arch/mips/pci/ops-au1000.c

   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  *      Alchemy/AMD Au1x00 pci support.
   4  *
   5  * Copyright 2001,2002,2003 MontaVista Software Inc.
   6  * Author: MontaVista Software, Inc.
   7  *              ppopov@mvista.com or source@mvista.com
   8  *
   9  *  Support for all devices (greater than 16) added by David Gathright.
  10  *
  11  *  This program is free software; you can redistribute  it and/or modify it
  12  *  under  the terms of  the GNU General  Public License as published by the
  13  *  Free Software Foundation;  either version 2 of the  License, or (at your
  14  *  option) any later version.
  15  *
  16  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  17  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  18  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  19  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  20  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  21  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  22  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  23  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  24  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  *  You should have received a copy of the  GNU General Public License along
  28  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  29  *  675 Mass Ave, Cambridge, MA 02139, USA.
  30  */
  31 #include <linux/config.h>
  32 #include <linux/types.h>
  33 #include <linux/pci.h>
  34 #include <linux/kernel.h>
  35 #include <linux/init.h>
  36
  37 #include <asm/au1000.h>
  38 #ifdef CONFIG_MIPS_PB1000
  39 #include <asm/pb1000.h>
  40 #endif
  41 #include <asm/pci_channel.h>
  42
  43 #define PCI_ACCESS_READ  0
  44 #define PCI_ACCESS_WRITE 1
  45
  46 #undef DEBUG
  47 #ifdef  DEBUG
  48 #define DBG(x...)       printk(x)
  49 #else
  50 #define DBG(x...)
  51 #endif
  52
  53 /* TBD */
  54 static struct resource pci_io_resource = {
  55         "pci IO space",
  56         (u32) PCI_IO_START,
  57         (u32) PCI_IO_END,
  58         IORESOURCE_IO
  59 };
  60
  61 static struct resource pci_mem_resource = {
  62         "pci memory space",
  63         (u32) PCI_MEM_START,
  64         (u32) PCI_MEM_END,
  65         IORESOURCE_MEM
  66 };
  67
  68 extern struct pci_ops au1x_pci_ops;
  69
  70 struct pci_channel mips_pci_channels[] = {
  71         {&au1x_pci_ops, &pci_io_resource, &pci_mem_resource,
  72          PCI_FIRST_DEVFN, PCI_LAST_DEVFN},
  73         {(struct pci_ops *) NULL, (struct resource *) NULL,
  74          (struct resource *) NULL, (int) NULL, (int) NULL}
  75 };
  76
  77
  78 #ifdef CONFIG_MIPS_PB1000
  79 /*
  80  * "Bus 2" is really the first and only external slot on the pb1000.
  81  * We'll call that bus 0, and limit the accesses to that single
  82  * external slot only. The SDRAM is already initialized in setup.c.
  83  */
  84 static int config_access(unsigned char access_type, struct pci_dev *dev,
  85                          unsigned char where, u32 * data)
  86 {
  87         unsigned char bus = dev->bus->number;
  88         unsigned char dev_fn = dev->devfn;
  89         unsigned long config;
  90
  91         if (((dev_fn >> 3) != 0) || (bus != 0)) {
  92                 *data = 0xffffffff;
  93                 return -1;
  94         }
  95
  96         config = PCI_CONFIG_BASE | (where & ~0x3);
  97
  98         if (access_type == PCI_ACCESS_WRITE) {
  99                 au_writel(*data, config);
 100         } else {
 101                 *data = au_readl(config);
 102         }
 103         au_sync_udelay(1);
 104
 105         DBG("config_access: %d bus %d dev_fn %x at %x *data %x, conf %x\n",
 106             access_type, bus, dev_fn, where, *data, config);
 107
 108         DBG("bridge config reg: %x (%x)\n", au_readl(PCI_BRIDGE_CONFIG),
 109             *data);
 110
 111         if (au_readl(PCI_BRIDGE_CONFIG) & (1 << 16)) {
 112                 *data = 0xffffffff;
 113                 return -1;
 114         } else {
 115                 return PCIBIOS_SUCCESSFUL;
 116         }
 117 }
 118
 119 #else
 120
 121 static int config_access(unsigned char access_type, struct pci_bus *bus,
 122                          unsigned int devfn, unsigned char where,
 123                          u32 * data)
 124 {
 125 #ifdef CONFIG_SOC_AU1500
 126         unsigned int device = PCI_SLOT(devfn);
 127         unsigned int function = PCI_FUNC(devfn);
 128         unsigned long config, status;
 129         unsigned long cfg_addr;
 130
 131         if (device > 19) {
 132                 *data = 0xffffffff;
 133                 return -1;
 134         }
 135
 136         au_writel(((0x2000 << 16) |
 137                    (au_readl(Au1500_PCI_STATCMD) & 0xffff)),
 138                   Au1500_PCI_STATCMD);
 139         //au_writel(au_readl(Au1500_PCI_CFG) & ~PCI_ERROR, Au1500_PCI_CFG);
 140         au_sync_udelay(1);
 141
 142         /* setup the config window */
 143         if (bus->number == 0) {
 144                 cfg_addr = (unsigned long) ioremap(Au1500_EXT_CFG |
 145                                                    ((1 << device) << 11),
 146                                                    0x00100000);
 147         } else {
 148                 cfg_addr = (unsigned long) ioremap(Au1500_EXT_CFG_TYPE1 |
 149                                                    (bus->
 150                                                     number << 16) | (device
 151                                                                      <<
 152                                                                      11),
 153                                                    0x00100000);
 154         }
 155
 156         if (!cfg_addr)
 157                 panic(KERN_ERR "PCI unable to ioremap cfg space\n");
 158
 159         /* setup the lower bits of the 36 bit address */
 160         config = cfg_addr | (function << 8) | (where & ~0x3);
 161
 162 #if 0
 163         if (access_type == PCI_ACCESS_WRITE) {
 164                 printk("cfg write:  ");
 165         } else {
 166                 printk("cfg read:  ");
 167         }
 168         printk("devfn %x, device %x func %x  \n", devfn, device, function);
 169         if (access_type == PCI_ACCESS_WRITE) {
 170                 printk("data %x\n", *data);
 171         }
 172 #endif
 173
 174         if (access_type == PCI_ACCESS_WRITE) {
 175                 au_writel(*data, config);
 176         } else {
 177                 *data = au_readl(config);
 178         }
 179         au_sync_udelay(2);
 180
 181
 182         DBG("config_access: %d bus %d device %d at %x *data %x, conf %x\n",
 183             access_type, bus->number, device, where, *data, config);
 184
 185         /* unmap io space */
 186         iounmap((void *) cfg_addr);
 187
 188         /* check master abort */
 189         status = au_readl(Au1500_PCI_STATCMD);
 190 #if 0
 191         if (access_type == PCI_ACCESS_READ) {
 192                 printk("read data: %x\n", *data);
 193         }
 194 #endif
 195         if (status & (1 << 29)) {
 196                 *data = 0xffffffff;
 197                 return -1;
 198         } else if ((status >> 28) & 0xf) {
 199                 printk("PCI ERR detected: status %x\n", status);
 200                 *data = 0xffffffff;
 201                 return -1;
 202         } else {
 203                 return PCIBIOS_SUCCESSFUL;
 204         }
 205 #endif
 206 }
 207 #endif
 208
 209 static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
 210                             int where, u8 * val)
 211 {
 212         u32 data;
 213         int ret;
 214
 215         ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
 216         if (where & 1)
 217                 data >>= 8;
 218         if (where & 2)
 219                 data >>= 16;
 220         *val = data & 0xff;
 221         return ret;
 222 }
 223
 224
 225 static int read_config_word(struct pci_bus *bus, unsigned int devfn,
 226                             int where, u16 * val)
 227 {
 228         u32 data;
 229         int ret;
 230
 231         ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
 232         if (where & 2)
 233                 data >>= 16;
 234         *val = data & 0xffff;
 235         return ret;
 236 }
 237
 238 static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
 239                              int where, u32 * val)
 240 {
 241         int ret;
 242
 243         ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
 244         return ret;
 245 }
 246
 247 static int
 248 write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
 249                   u8 val)
 250 {
 251         u32 data = 0;
 252
 253         if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 254                 return -1;
 255
 256         data = (data & ~(0xff << ((where & 3) << 3))) |
 257             (val << ((where & 3) << 3));
 258
 259         if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
 260                 return -1;
 261
 262         return PCIBIOS_SUCCESSFUL;
 263 }
 264
 265 static int
 266 write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
 267                   u16 val)
 268 {
 269         u32 data = 0;
 270
 271         if (where & 1)
 272                 return PCIBIOS_BAD_REGISTER_NUMBER;
 273
 274         if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 275                 return -1;
 276
 277         data = (data & ~(0xffff << ((where & 3) << 3))) |
 278             (val << ((where & 3) << 3));
 279
 280         if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
 281                 return -1;
 282
 283
 284         return PCIBIOS_SUCCESSFUL;
 285 }
 286
 287 static int
 288 write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
 289                    u32 val)
 290 {
 291         if (where & 3)
 292                 return PCIBIOS_BAD_REGISTER_NUMBER;
 293
 294         if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
 295                 return -1;
 296
 297         return PCIBIOS_SUCCESSFUL;
 298 }
 299
 300 static int config_read(struct pci_bus *bus, unsigned int devfn,
 301                        int where, int size, u32 * val)
 302 {
 303         switch (size) {
 304         case 1:
 305                 return read_config_byte(bus, devfn, where, (u8 *) val);
 306         case 2:
 307                 return read_config_word(bus, devfn, where, (u16 *) val);
 308         default:
 309                 return read_config_dword(bus, devfn, where, val);
 310         }
 311 }
 312
 313 static int config_write(struct pci_bus *bus, unsigned int devfn,
 314                         int where, int size, u32 val)
 315 {
 316         switch (size) {
 317         case 1:
 318                 return write_config_byte(bus, devfn, where, (u8) val);
 319         case 2:
 320                 return write_config_word(bus, devfn, where, (u16) val);
 321         default:
 322                 return write_config_dword(bus, devfn, where, val);
 323         }
 324 }
 325
 326
 327 struct pci_ops au1x_pci_ops = {
 328         config_read,
 329         config_write
 330 };