2 * $Id: cstm_mips_ixx.c,v 1.14 2005/11/07 11:14:26 gleixner Exp $
4 * Mapping of a custom board with both AMD CFI and JEDEC flash in partitions.
5 * Config with both CFI and JEDEC device support.
7 * Basically physmap.c with the addition of partitions and
8 * an array of mapping info to accomodate more than one flash type per board.
10 * Copyright 2000 MontaVista Software Inc.
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 #include <linux/module.h>
34 #include <linux/types.h>
35 #include <linux/kernel.h>
36 #include <linux/init.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/map.h>
40 #include <linux/mtd/partitions.h>
41 #include <linux/delay.h>
43 #if defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR)
44 #define CC_GCR 0xB4013818
45 #define CC_GPBCR 0xB401380A
46 #define CC_GPBDR 0xB4013808
47 #define CC_M68K_DEVICE 1
48 #define CC_M68K_FUNCTION 6
49 #define CC_CONFADDR 0xB8004000
50 #define CC_CONFDATA 0xB8004004
51 #define CC_FC_FCR 0xB8002004
52 #define CC_FC_DCR 0xB8002008
53 #define CC_GPACR 0xB4013802
54 #define CC_GPAICR 0xB4013804
55 #endif /* defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR) */
57 #if defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR)
58 void cstm_mips_ixx_set_vpp(struct map_info
*map
,int vpp
)
60 static DEFINE_SPINLOCK(vpp_lock
);
61 static int vpp_count
= 0;
64 spin_lock_irqsave(&vpp_lock
, flags
);
72 // Set GPIO port B pin3 to high
73 data
= *(__u16
*)(CC_GPBCR
);
74 data
= (data
& 0xff0f) | 0x0040;
75 *(__u16
*)CC_GPBCR
= data
;
76 *(__u8
*)CC_GPBDR
= (*(__u8
*)CC_GPBDR
) | 0x08;
79 /* need to have this delay for first
80 enabling vpp after powerup */
88 // Set GPIO port B pin3 to high
89 data
= *(__u16
*)(CC_GPBCR
);
90 data
= (data
& 0xff3f) | 0x0040;
91 *(__u16
*)CC_GPBCR
= data
;
92 *(__u8
*)CC_GPBDR
= (*(__u8
*)CC_GPBDR
) & 0xf7;
95 spin_unlock_irqrestore(&vpp_lock
, flags
);
99 /* board and partition description */
101 #define MAX_PHYSMAP_PARTITIONS 8
102 struct cstm_mips_ixx_info
{
104 unsigned long window_addr
;
105 unsigned long window_size
;
110 #if defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR)
111 #define PHYSMAP_NUMBER 1 // number of board desc structs needed, one per contiguous flash type
112 const struct cstm_mips_ixx_info cstm_mips_ixx_board_desc
[PHYSMAP_NUMBER
] =
114 { // 28F128J3A in 2x16 configuration
116 0x08000000, // window_addr
117 0x02000000, // window_size
123 static struct mtd_partition cstm_mips_ixx_partitions
[PHYSMAP_NUMBER
][MAX_PHYSMAP_PARTITIONS
] = {
124 { // 28F128J3A in 2x16 configuration
126 .name
= "main partition ",
127 .size
= 0x02000000, // 128 x 2 x 128k byte sectors
132 #else /* defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR) */
133 #define PHYSMAP_NUMBER 1 // number of board desc structs needed, one per contiguous flash type
134 const struct cstm_mips_ixx_info cstm_mips_ixx_board_desc
[PHYSMAP_NUMBER
] =
138 CONFIG_MTD_CSTM_MIPS_IXX_START
, // window_addr
139 CONFIG_MTD_CSTM_MIPS_IXX_LEN
, // window_size
140 CONFIG_MTD_CSTM_MIPS_IXX_BUSWIDTH
, // bankwidth
145 static struct mtd_partition cstm_mips_ixx_partitions
[PHYSMAP_NUMBER
][MAX_PHYSMAP_PARTITIONS
] = {
148 .name
= "main partition",
149 .size
= CONFIG_MTD_CSTM_MIPS_IXX_LEN
,
154 #endif /* defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR) */
156 struct map_info cstm_mips_ixx_map
[PHYSMAP_NUMBER
];
158 int __init
init_cstm_mips_ixx(void)
162 struct mtd_info
*mymtd
;
163 struct mtd_partition
*parts
;
165 /* Initialize mapping */
166 for (i
=0;i
<PHYSMAP_NUMBER
;i
++) {
167 printk(KERN_NOTICE
"cstm_mips_ixx flash device: 0x%lx at 0x%lx\n",
168 cstm_mips_ixx_board_desc
[i
].window_size
, cstm_mips_ixx_board_desc
[i
].window_addr
);
171 cstm_mips_ixx_map
[i
].phys
= cstm_mips_ixx_board_desc
[i
].window_addr
;
172 cstm_mips_ixx_map
[i
].virt
= ioremap(cstm_mips_ixx_board_desc
[i
].window_addr
, cstm_mips_ixx_board_desc
[i
].window_size
);
173 if (!cstm_mips_ixx_map
[i
].virt
) {
175 printk(KERN_WARNING
"Failed to ioremap\n");
176 for (j
= 0; j
< i
; j
++) {
177 if (cstm_mips_ixx_map
[j
].virt
) {
178 iounmap((void *)cstm_mips_ixx_map
[j
].virt
);
179 cstm_mips_ixx_map
[j
].virt
= 0;
184 cstm_mips_ixx_map
[i
].name
= cstm_mips_ixx_board_desc
[i
].name
;
185 cstm_mips_ixx_map
[i
].size
= cstm_mips_ixx_board_desc
[i
].window_size
;
186 cstm_mips_ixx_map
[i
].bankwidth
= cstm_mips_ixx_board_desc
[i
].bankwidth
;
187 #if defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR)
188 cstm_mips_ixx_map
[i
].set_vpp
= cstm_mips_ixx_set_vpp
;
190 simple_map_init(&cstm_mips_ixx_map
[i
]);
191 //printk(KERN_NOTICE "cstm_mips_ixx: ioremap is %x\n",(unsigned int)(cstm_mips_ixx_map[i].virt));
194 #if defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR)
195 setup_ITE_IVR_flash();
196 #endif /* defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR) */
198 for (i
=0;i
<PHYSMAP_NUMBER
;i
++) {
199 parts
= &cstm_mips_ixx_partitions
[i
][0];
201 mymtd
= (struct mtd_info
*)do_map_probe("cfi_probe", &cstm_mips_ixx_map
[i
]);
202 //printk(KERN_NOTICE "phymap %d cfi_probe: mymtd is %x\n",i,(unsigned int)mymtd);
205 mymtd
= (struct mtd_info
*)do_map_probe("jedec", &cstm_mips_ixx_map
[i
]);
206 printk(KERN_NOTICE
"cstm_mips_ixx %d jedec: mymtd is %x\n",i
,(unsigned int)mymtd
);
209 mymtd
->owner
= THIS_MODULE
;
211 cstm_mips_ixx_map
[i
].map_priv_2
= (unsigned long)mymtd
;
212 add_mtd_partitions(mymtd
, parts
, cstm_mips_ixx_board_desc
[i
].num_partitions
);
215 for (i
= 0; i
< PHYSMAP_NUMBER
; i
++) {
216 if (cstm_mips_ixx_map
[i
].virt
) {
217 iounmap((void *)cstm_mips_ixx_map
[i
].virt
);
218 cstm_mips_ixx_map
[i
].virt
= 0;
227 static void __exit
cleanup_cstm_mips_ixx(void)
230 struct mtd_info
*mymtd
;
232 for (i
=0;i
<PHYSMAP_NUMBER
;i
++) {
233 mymtd
= (struct mtd_info
*)cstm_mips_ixx_map
[i
].map_priv_2
;
235 del_mtd_partitions(mymtd
);
238 if (cstm_mips_ixx_map
[i
].virt
) {
239 iounmap((void *)cstm_mips_ixx_map
[i
].virt
);
240 cstm_mips_ixx_map
[i
].virt
= 0;
244 #if defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR)
245 void PCISetULongByOffset(__u32 DevNumber
, __u32 FuncNumber
, __u32 Offset
, __u32 data
)
249 offset
= ( unsigned long )( 0x80000000 | ( DevNumber
<< 11 ) + ( FuncNumber
<< 8 ) + Offset
) ;
251 *(__u32
*)CC_CONFADDR
= offset
;
252 *(__u32
*)CC_CONFDATA
= data
;
254 void setup_ITE_IVR_flash()
258 size
= 0x0e000000; // 32MiB
259 base
= (0x08000000) >> 8 >>1; // Bug: we must shift one more bit
261 /* need to set ITE flash to 32 bits instead of default 8 */
262 #ifdef CONFIG_MIPS_IVR
263 *(__u32
*)CC_FC_FCR
= 0x55;
264 *(__u32
*)CC_GPACR
= 0xfffc;
266 *(__u32
*)CC_FC_FCR
= 0x77;
268 /* turn bursting off */
269 *(__u32
*)CC_FC_DCR
= 0x0;
271 /* setup for one chip 4 byte PCI access */
272 PCISetULongByOffset(CC_M68K_DEVICE
, CC_M68K_FUNCTION
, 0x60, size
| base
);
273 PCISetULongByOffset(CC_M68K_DEVICE
, CC_M68K_FUNCTION
, 0x64, 0x02);
275 #endif /* defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR) */
277 module_init(init_cstm_mips_ixx
);
278 module_exit(cleanup_cstm_mips_ixx
);
281 MODULE_LICENSE("GPL");
282 MODULE_AUTHOR("Alice Hennessy <ahennessy@mvista.com>");
283 MODULE_DESCRIPTION("MTD map driver for ITE 8172G and Globespan IVR boards");