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Coarsly sort out 32-bit-only, 64-bit-only and ``portable'' MIPS lib/
[linux-2.6/linux-mips.git] / drivers / char / synclink.c
blobccb3804e49779774dbb32297a63e23bcdef84c65
1 /*
2 * linux/drivers/char/synclink.c
3 *
4 * $Id: synclink.c,v 4.12 2003/06/18 15:29:32 paulkf Exp $
5 *
6 * Device driver for Microgate SyncLink ISA and PCI
7 * high speed multiprotocol serial adapters.
8 *
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
11 *
12 * Microgate and SyncLink are trademarks of Microgate Corporation
13 *
14 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
15 *
16 * Original release 01/11/99
17 *
18 * This code is released under the GNU General Public License (GPL)
19 *
20 * This driver is primarily intended for use in synchronous
21 * HDLC mode. Asynchronous mode is also provided.
22 *
23 * When operating in synchronous mode, each call to mgsl_write()
24 * contains exactly one complete HDLC frame. Calling mgsl_put_char
25 * will start assembling an HDLC frame that will not be sent until
26 * mgsl_flush_chars or mgsl_write is called.
27 *
28 * Synchronous receive data is reported as complete frames. To accomplish
29 * this, the TTY flip buffer is bypassed (too small to hold largest
30 * frame and may fragment frames) and the line discipline
31 * receive entry point is called directly.
32 *
33 * This driver has been tested with a slightly modified ppp.c driver
34 * for synchronous PPP.
35 *
36 * 2000/02/16
37 * Added interface for syncppp.c driver (an alternate synchronous PPP
38 * implementation that also supports Cisco HDLC). Each device instance
39 * registers as a tty device AND a network device (if dosyncppp option
40 * is set for the device). The functionality is determined by which
41 * device interface is opened.
42 *
43 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
46 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
51 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
53 * OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55
56 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
57 #if defined(__i386__)
58 # define BREAKPOINT() asm(" int $3");
59 #else
60 # define BREAKPOINT() { }
61 #endif
62
63 #define MAX_ISA_DEVICES 10
64 #define MAX_PCI_DEVICES 10
65 #define MAX_TOTAL_DEVICES 20
66
67 #include <linux/config.h>
68 #include <linux/module.h>
69 #include <linux/version.h>
70 #include <linux/errno.h>
71 #include <linux/signal.h>
72 #include <linux/sched.h>
73 #include <linux/timer.h>
74 #include <linux/interrupt.h>
75 #include <linux/pci.h>
76 #include <linux/tty.h>
77 #include <linux/tty_flip.h>
78 #include <linux/serial.h>
79 #include <linux/major.h>
80 #include <linux/string.h>
81 #include <linux/fcntl.h>
82 #include <linux/ptrace.h>
83 #include <linux/ioport.h>
84 #include <linux/mm.h>
85 #include <linux/slab.h>
86
87 #include <linux/netdevice.h>
88
89 #include <linux/vmalloc.h>
90 #include <linux/init.h>
91 #include <asm/serial.h>
92
93 #include <linux/delay.h>
94 #include <linux/ioctl.h>
95
96 #include <asm/system.h>
97 #include <asm/io.h>
98 #include <asm/irq.h>
99 #include <asm/dma.h>
100 #include <asm/bitops.h>
101 #include <asm/types.h>
102 #include <linux/termios.h>
103 #include <linux/workqueue.h>
104
105 #ifdef CONFIG_SYNCLINK_SYNCPPP_MODULE
106 #define CONFIG_SYNCLINK_SYNCPPP 1
107 #endif
108
109 #ifdef CONFIG_SYNCLINK_SYNCPPP
110 #include <net/syncppp.h>
111 #endif
112
113 #define GET_USER(error,value,addr) error = get_user(value,addr)
114 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
115 #define PUT_USER(error,value,addr) error = put_user(value,addr)
116 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
117
118 #include <asm/uaccess.h>
119
120 #include "linux/synclink.h"
121
122 #define RCLRVALUE 0xffff
123
124 MGSL_PARAMS default_params = {
125 MGSL_MODE_HDLC, /* unsigned long mode */
126 0, /* unsigned char loopback; */
127 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
128 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
129 0, /* unsigned long clock_speed; */
130 0xff, /* unsigned char addr_filter; */
131 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
132 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
133 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
134 9600, /* unsigned long data_rate; */
135 8, /* unsigned char data_bits; */
136 1, /* unsigned char stop_bits; */
137 ASYNC_PARITY_NONE /* unsigned char parity; */
138 };
139
140 #define SHARED_MEM_ADDRESS_SIZE 0x40000
141 #define BUFFERLISTSIZE (PAGE_SIZE)
142 #define DMABUFFERSIZE (PAGE_SIZE)
143 #define MAXRXFRAMES 7
144
145 typedef struct _DMABUFFERENTRY
146 {
147 u32 phys_addr; /* 32-bit flat physical address of data buffer */
148 u16 count; /* buffer size/data count */
149 u16 status; /* Control/status field */
150 u16 rcc; /* character count field */
151 u16 reserved; /* padding required by 16C32 */
152 u32 link; /* 32-bit flat link to next buffer entry */
153 char *virt_addr; /* virtual address of data buffer */
154 u32 phys_entry; /* physical address of this buffer entry */
155 } DMABUFFERENTRY, *DMAPBUFFERENTRY;
156
157 /* The queue of BH actions to be performed */
158
159 #define BH_RECEIVE 1
160 #define BH_TRANSMIT 2
161 #define BH_STATUS 4
162
163 #define IO_PIN_SHUTDOWN_LIMIT 100
164
165 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
166
167 struct _input_signal_events {
168 int ri_up;
169 int ri_down;
170 int dsr_up;
171 int dsr_down;
172 int dcd_up;
173 int dcd_down;
174 int cts_up;
175 int cts_down;
176 };
177
178 /* transmit holding buffer definitions*/
179 #define MAX_TX_HOLDING_BUFFERS 5
180 struct tx_holding_buffer {
181 int buffer_size;
182 unsigned char * buffer;
183 };
184
185
186 /*
187 * Device instance data structure
188 */
189
190 struct mgsl_struct {
191 void *if_ptr; /* General purpose pointer (used by SPPP) */
192 int magic;
193 int flags;
194 int count; /* count of opens */
195 int line;
196 int hw_version;
197 unsigned short close_delay;
198 unsigned short closing_wait; /* time to wait before closing */
199
200 struct mgsl_icount icount;
201
202 struct tty_struct *tty;
203 int timeout;
204 int x_char; /* xon/xoff character */
205 int blocked_open; /* # of blocked opens */
206 u16 read_status_mask;
207 u16 ignore_status_mask;
208 unsigned char *xmit_buf;
209 int xmit_head;
210 int xmit_tail;
211 int xmit_cnt;
212
213 wait_queue_head_t open_wait;
214 wait_queue_head_t close_wait;
215
216 wait_queue_head_t status_event_wait_q;
217 wait_queue_head_t event_wait_q;
218 struct timer_list tx_timer; /* HDLC transmit timeout timer */
219 struct mgsl_struct *next_device; /* device list link */
220
221 spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */
222 struct work_struct task; /* task structure for scheduling bh */
223
224 u32 EventMask; /* event trigger mask */
225 u32 RecordedEvents; /* pending events */
226
227 u32 max_frame_size; /* as set by device config */
228
229 u32 pending_bh;
230
231 int bh_running; /* Protection from multiple */
232 int isr_overflow;
233 int bh_requested;
234
235 int dcd_chkcount; /* check counts to prevent */
236 int cts_chkcount; /* too many IRQs if a signal */
237 int dsr_chkcount; /* is floating */
238 int ri_chkcount;
239
240 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
241 unsigned long buffer_list_phys;
242
243 unsigned int rx_buffer_count; /* count of total allocated Rx buffers */
244 DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
245 unsigned int current_rx_buffer;
246
247 int num_tx_dma_buffers; /* number of tx dma frames required */
248 int tx_dma_buffers_used;
249 unsigned int tx_buffer_count; /* count of total allocated Tx buffers */
250 DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
251 int start_tx_dma_buffer; /* tx dma buffer to start tx dma operation */
252 int current_tx_buffer; /* next tx dma buffer to be loaded */
253
254 unsigned char *intermediate_rxbuffer;
255
256 int num_tx_holding_buffers; /* number of tx holding buffer allocated */
257 int get_tx_holding_index; /* next tx holding buffer for adapter to load */
258 int put_tx_holding_index; /* next tx holding buffer to store user request */
259 int tx_holding_count; /* number of tx holding buffers waiting */
260 struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
261
262 int rx_enabled;
263 int rx_overflow;
264
265 int tx_enabled;
266 int tx_active;
267 u32 idle_mode;
268
269 u16 cmr_value;
270 u16 tcsr_value;
271
272 char device_name[25]; /* device instance name */
273
274 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
275 unsigned char bus; /* expansion bus number (zero based) */
276 unsigned char function; /* PCI device number */
277
278 unsigned int io_base; /* base I/O address of adapter */
279 unsigned int io_addr_size; /* size of the I/O address range */
280 int io_addr_requested; /* nonzero if I/O address requested */
281
282 unsigned int irq_level; /* interrupt level */
283 unsigned long irq_flags;
284 int irq_requested; /* nonzero if IRQ requested */
285
286 unsigned int dma_level; /* DMA channel */
287 int dma_requested; /* nonzero if dma channel requested */
288
289 u16 mbre_bit;
290 u16 loopback_bits;
291 u16 usc_idle_mode;
292
293 MGSL_PARAMS params; /* communications parameters */
294
295 unsigned char serial_signals; /* current serial signal states */
296
297 int irq_occurred; /* for diagnostics use */
298 unsigned int init_error; /* Initialization startup error (DIAGS) */
299 int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */
300
301 u32 last_mem_alloc;
302 unsigned char* memory_base; /* shared memory address (PCI only) */
303 u32 phys_memory_base;
304 int shared_mem_requested;
305
306 unsigned char* lcr_base; /* local config registers (PCI only) */
307 u32 phys_lcr_base;
308 u32 lcr_offset;
309 int lcr_mem_requested;
310
311 u32 misc_ctrl_value;
312 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
313 char char_buf[MAX_ASYNC_BUFFER_SIZE];
314 BOOLEAN drop_rts_on_tx_done;
315
316 BOOLEAN loopmode_insert_requested;
317 BOOLEAN loopmode_send_done_requested;
318
319 struct _input_signal_events input_signal_events;
320
321 /* SPPP/Cisco HDLC device parts */
322 int netcount;
323 int dosyncppp;
324 spinlock_t netlock;
325 #ifdef CONFIG_SYNCLINK_SYNCPPP
326 struct ppp_device pppdev;
327 char netname[10];
328 struct net_device *netdev;
329 struct net_device_stats netstats;
330 struct net_device netdevice;
331 #endif
332 };
333
334 #define MGSL_MAGIC 0x5401
335
336 /*
337 * The size of the serial xmit buffer is 1 page, or 4096 bytes
338 */
339 #ifndef SERIAL_XMIT_SIZE
340 #define SERIAL_XMIT_SIZE 4096
341 #endif
342
343 /*
344 * These macros define the offsets used in calculating the
345 * I/O address of the specified USC registers.
346 */
347
348
349 #define DCPIN 2 /* Bit 1 of I/O address */
350 #define SDPIN 4 /* Bit 2 of I/O address */
351
352 #define DCAR 0 /* DMA command/address register */
353 #define CCAR SDPIN /* channel command/address register */
354 #define DATAREG DCPIN + SDPIN /* serial data register */
355 #define MSBONLY 0x41
356 #define LSBONLY 0x40
357
358 /*
359 * These macros define the register address (ordinal number)
360 * used for writing address/value pairs to the USC.
361 */
362
363 #define CMR 0x02 /* Channel mode Register */
364 #define CCSR 0x04 /* Channel Command/status Register */
365 #define CCR 0x06 /* Channel Control Register */
366 #define PSR 0x08 /* Port status Register */
367 #define PCR 0x0a /* Port Control Register */
368 #define TMDR 0x0c /* Test mode Data Register */
369 #define TMCR 0x0e /* Test mode Control Register */
370 #define CMCR 0x10 /* Clock mode Control Register */
371 #define HCR 0x12 /* Hardware Configuration Register */
372 #define IVR 0x14 /* Interrupt Vector Register */
373 #define IOCR 0x16 /* Input/Output Control Register */
374 #define ICR 0x18 /* Interrupt Control Register */
375 #define DCCR 0x1a /* Daisy Chain Control Register */
376 #define MISR 0x1c /* Misc Interrupt status Register */
377 #define SICR 0x1e /* status Interrupt Control Register */
378 #define RDR 0x20 /* Receive Data Register */
379 #define RMR 0x22 /* Receive mode Register */
380 #define RCSR 0x24 /* Receive Command/status Register */
381 #define RICR 0x26 /* Receive Interrupt Control Register */
382 #define RSR 0x28 /* Receive Sync Register */
383 #define RCLR 0x2a /* Receive count Limit Register */
384 #define RCCR 0x2c /* Receive Character count Register */
385 #define TC0R 0x2e /* Time Constant 0 Register */
386 #define TDR 0x30 /* Transmit Data Register */
387 #define TMR 0x32 /* Transmit mode Register */
388 #define TCSR 0x34 /* Transmit Command/status Register */
389 #define TICR 0x36 /* Transmit Interrupt Control Register */
390 #define TSR 0x38 /* Transmit Sync Register */
391 #define TCLR 0x3a /* Transmit count Limit Register */
392 #define TCCR 0x3c /* Transmit Character count Register */
393 #define TC1R 0x3e /* Time Constant 1 Register */
394
395
396 /*
397 * MACRO DEFINITIONS FOR DMA REGISTERS
398 */
399
400 #define DCR 0x06 /* DMA Control Register (shared) */
401 #define DACR 0x08 /* DMA Array count Register (shared) */
402 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
403 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
404 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
405 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
406 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
407
408 #define TDMR 0x02 /* Transmit DMA mode Register */
409 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
410 #define TBCR 0x2a /* Transmit Byte count Register */
411 #define TARL 0x2c /* Transmit Address Register (low) */
412 #define TARU 0x2e /* Transmit Address Register (high) */
413 #define NTBCR 0x3a /* Next Transmit Byte count Register */
414 #define NTARL 0x3c /* Next Transmit Address Register (low) */
415 #define NTARU 0x3e /* Next Transmit Address Register (high) */
416
417 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
418 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
419 #define RBCR 0xaa /* Receive Byte count Register */
420 #define RARL 0xac /* Receive Address Register (low) */
421 #define RARU 0xae /* Receive Address Register (high) */
422 #define NRBCR 0xba /* Next Receive Byte count Register */
423 #define NRARL 0xbc /* Next Receive Address Register (low) */
424 #define NRARU 0xbe /* Next Receive Address Register (high) */
425
426
427 /*
428 * MACRO DEFINITIONS FOR MODEM STATUS BITS
429 */
430
431 #define MODEMSTATUS_DTR 0x80
432 #define MODEMSTATUS_DSR 0x40
433 #define MODEMSTATUS_RTS 0x20
434 #define MODEMSTATUS_CTS 0x10
435 #define MODEMSTATUS_RI 0x04
436 #define MODEMSTATUS_DCD 0x01
437
438
439 /*
440 * Channel Command/Address Register (CCAR) Command Codes
441 */
442
443 #define RTCmd_Null 0x0000
444 #define RTCmd_ResetHighestIus 0x1000
445 #define RTCmd_TriggerChannelLoadDma 0x2000
446 #define RTCmd_TriggerRxDma 0x2800
447 #define RTCmd_TriggerTxDma 0x3000
448 #define RTCmd_TriggerRxAndTxDma 0x3800
449 #define RTCmd_PurgeRxFifo 0x4800
450 #define RTCmd_PurgeTxFifo 0x5000
451 #define RTCmd_PurgeRxAndTxFifo 0x5800
452 #define RTCmd_LoadRcc 0x6800
453 #define RTCmd_LoadTcc 0x7000
454 #define RTCmd_LoadRccAndTcc 0x7800
455 #define RTCmd_LoadTC0 0x8800
456 #define RTCmd_LoadTC1 0x9000
457 #define RTCmd_LoadTC0AndTC1 0x9800
458 #define RTCmd_SerialDataLSBFirst 0xa000
459 #define RTCmd_SerialDataMSBFirst 0xa800
460 #define RTCmd_SelectBigEndian 0xb000
461 #define RTCmd_SelectLittleEndian 0xb800
462
463
464 /*
465 * DMA Command/Address Register (DCAR) Command Codes
466 */
467
468 #define DmaCmd_Null 0x0000
469 #define DmaCmd_ResetTxChannel 0x1000
470 #define DmaCmd_ResetRxChannel 0x1200
471 #define DmaCmd_StartTxChannel 0x2000
472 #define DmaCmd_StartRxChannel 0x2200
473 #define DmaCmd_ContinueTxChannel 0x3000
474 #define DmaCmd_ContinueRxChannel 0x3200
475 #define DmaCmd_PauseTxChannel 0x4000
476 #define DmaCmd_PauseRxChannel 0x4200
477 #define DmaCmd_AbortTxChannel 0x5000
478 #define DmaCmd_AbortRxChannel 0x5200
479 #define DmaCmd_InitTxChannel 0x7000
480 #define DmaCmd_InitRxChannel 0x7200
481 #define DmaCmd_ResetHighestDmaIus 0x8000
482 #define DmaCmd_ResetAllChannels 0x9000
483 #define DmaCmd_StartAllChannels 0xa000
484 #define DmaCmd_ContinueAllChannels 0xb000
485 #define DmaCmd_PauseAllChannels 0xc000
486 #define DmaCmd_AbortAllChannels 0xd000
487 #define DmaCmd_InitAllChannels 0xf000
488
489 #define TCmd_Null 0x0000
490 #define TCmd_ClearTxCRC 0x2000
491 #define TCmd_SelectTicrTtsaData 0x4000
492 #define TCmd_SelectTicrTxFifostatus 0x5000
493 #define TCmd_SelectTicrIntLevel 0x6000
494 #define TCmd_SelectTicrdma_level 0x7000
495 #define TCmd_SendFrame 0x8000
496 #define TCmd_SendAbort 0x9000
497 #define TCmd_EnableDleInsertion 0xc000
498 #define TCmd_DisableDleInsertion 0xd000
499 #define TCmd_ClearEofEom 0xe000
500 #define TCmd_SetEofEom 0xf000
501
502 #define RCmd_Null 0x0000
503 #define RCmd_ClearRxCRC 0x2000
504 #define RCmd_EnterHuntmode 0x3000
505 #define RCmd_SelectRicrRtsaData 0x4000
506 #define RCmd_SelectRicrRxFifostatus 0x5000
507 #define RCmd_SelectRicrIntLevel 0x6000
508 #define RCmd_SelectRicrdma_level 0x7000
509
510 /*
511 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
512 */
513
514 #define RECEIVE_STATUS BIT5
515 #define RECEIVE_DATA BIT4
516 #define TRANSMIT_STATUS BIT3
517 #define TRANSMIT_DATA BIT2
518 #define IO_PIN BIT1
519 #define MISC BIT0
520
521
522 /*
523 * Receive status Bits in Receive Command/status Register RCSR
524 */
525
526 #define RXSTATUS_SHORT_FRAME BIT8
527 #define RXSTATUS_CODE_VIOLATION BIT8
528 #define RXSTATUS_EXITED_HUNT BIT7
529 #define RXSTATUS_IDLE_RECEIVED BIT6
530 #define RXSTATUS_BREAK_RECEIVED BIT5
531 #define RXSTATUS_ABORT_RECEIVED BIT5
532 #define RXSTATUS_RXBOUND BIT4
533 #define RXSTATUS_CRC_ERROR BIT3
534 #define RXSTATUS_FRAMING_ERROR BIT3
535 #define RXSTATUS_ABORT BIT2
536 #define RXSTATUS_PARITY_ERROR BIT2
537 #define RXSTATUS_OVERRUN BIT1
538 #define RXSTATUS_DATA_AVAILABLE BIT0
539 #define RXSTATUS_ALL 0x01f6
540 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
541
542 /*
543 * Values for setting transmit idle mode in
544 * Transmit Control/status Register (TCSR)
545 */
546 #define IDLEMODE_FLAGS 0x0000
547 #define IDLEMODE_ALT_ONE_ZERO 0x0100
548 #define IDLEMODE_ZERO 0x0200
549 #define IDLEMODE_ONE 0x0300
550 #define IDLEMODE_ALT_MARK_SPACE 0x0500
551 #define IDLEMODE_SPACE 0x0600
552 #define IDLEMODE_MARK 0x0700
553 #define IDLEMODE_MASK 0x0700
554
555 /*
556 * IUSC revision identifiers
557 */
558 #define IUSC_SL1660 0x4d44
559 #define IUSC_PRE_SL1660 0x4553
560
561 /*
562 * Transmit status Bits in Transmit Command/status Register (TCSR)
563 */
564
565 #define TCSR_PRESERVE 0x0F00
566
567 #define TCSR_UNDERWAIT BIT11
568 #define TXSTATUS_PREAMBLE_SENT BIT7
569 #define TXSTATUS_IDLE_SENT BIT6
570 #define TXSTATUS_ABORT_SENT BIT5
571 #define TXSTATUS_EOF_SENT BIT4
572 #define TXSTATUS_EOM_SENT BIT4
573 #define TXSTATUS_CRC_SENT BIT3
574 #define TXSTATUS_ALL_SENT BIT2
575 #define TXSTATUS_UNDERRUN BIT1
576 #define TXSTATUS_FIFO_EMPTY BIT0
577 #define TXSTATUS_ALL 0x00fa
578 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
579
580
581 #define MISCSTATUS_RXC_LATCHED BIT15
582 #define MISCSTATUS_RXC BIT14
583 #define MISCSTATUS_TXC_LATCHED BIT13
584 #define MISCSTATUS_TXC BIT12
585 #define MISCSTATUS_RI_LATCHED BIT11
586 #define MISCSTATUS_RI BIT10
587 #define MISCSTATUS_DSR_LATCHED BIT9
588 #define MISCSTATUS_DSR BIT8
589 #define MISCSTATUS_DCD_LATCHED BIT7
590 #define MISCSTATUS_DCD BIT6
591 #define MISCSTATUS_CTS_LATCHED BIT5
592 #define MISCSTATUS_CTS BIT4
593 #define MISCSTATUS_RCC_UNDERRUN BIT3
594 #define MISCSTATUS_DPLL_NO_SYNC BIT2
595 #define MISCSTATUS_BRG1_ZERO BIT1
596 #define MISCSTATUS_BRG0_ZERO BIT0
597
598 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
599 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
600
601 #define SICR_RXC_ACTIVE BIT15
602 #define SICR_RXC_INACTIVE BIT14
603 #define SICR_RXC (BIT15+BIT14)
604 #define SICR_TXC_ACTIVE BIT13
605 #define SICR_TXC_INACTIVE BIT12
606 #define SICR_TXC (BIT13+BIT12)
607 #define SICR_RI_ACTIVE BIT11
608 #define SICR_RI_INACTIVE BIT10
609 #define SICR_RI (BIT11+BIT10)
610 #define SICR_DSR_ACTIVE BIT9
611 #define SICR_DSR_INACTIVE BIT8
612 #define SICR_DSR (BIT9+BIT8)
613 #define SICR_DCD_ACTIVE BIT7
614 #define SICR_DCD_INACTIVE BIT6
615 #define SICR_DCD (BIT7+BIT6)
616 #define SICR_CTS_ACTIVE BIT5
617 #define SICR_CTS_INACTIVE BIT4
618 #define SICR_CTS (BIT5+BIT4)
619 #define SICR_RCC_UNDERFLOW BIT3
620 #define SICR_DPLL_NO_SYNC BIT2
621 #define SICR_BRG1_ZERO BIT1
622 #define SICR_BRG0_ZERO BIT0
623
624 void usc_DisableMasterIrqBit( struct mgsl_struct *info );
625 void usc_EnableMasterIrqBit( struct mgsl_struct *info );
626 void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
627 void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
628 void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
629
630 #define usc_EnableInterrupts( a, b ) \
631 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
632
633 #define usc_DisableInterrupts( a, b ) \
634 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
635
636 #define usc_EnableMasterIrqBit(a) \
637 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
638
639 #define usc_DisableMasterIrqBit(a) \
640 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
641
642 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
643
644 /*
645 * Transmit status Bits in Transmit Control status Register (TCSR)
646 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
647 */
648
649 #define TXSTATUS_PREAMBLE_SENT BIT7
650 #define TXSTATUS_IDLE_SENT BIT6
651 #define TXSTATUS_ABORT_SENT BIT5
652 #define TXSTATUS_EOF BIT4
653 #define TXSTATUS_CRC_SENT BIT3
654 #define TXSTATUS_ALL_SENT BIT2
655 #define TXSTATUS_UNDERRUN BIT1
656 #define TXSTATUS_FIFO_EMPTY BIT0
657
658 #define DICR_MASTER BIT15
659 #define DICR_TRANSMIT BIT0
660 #define DICR_RECEIVE BIT1
661
662 #define usc_EnableDmaInterrupts(a,b) \
663 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
664
665 #define usc_DisableDmaInterrupts(a,b) \
666 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
667
668 #define usc_EnableStatusIrqs(a,b) \
669 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
670
671 #define usc_DisablestatusIrqs(a,b) \
672 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
673
674 /* Transmit status Bits in Transmit Control status Register (TCSR) */
675 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
676
677
678 #define DISABLE_UNCONDITIONAL 0
679 #define DISABLE_END_OF_FRAME 1
680 #define ENABLE_UNCONDITIONAL 2
681 #define ENABLE_AUTO_CTS 3
682 #define ENABLE_AUTO_DCD 3
683 #define usc_EnableTransmitter(a,b) \
684 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
685 #define usc_EnableReceiver(a,b) \
686 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
687
688 u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
689 void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
690 void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
691
692 u16 usc_InReg( struct mgsl_struct *info, u16 Port );
693 void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
694 void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
695 void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
696 void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
697
698 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
699 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
700
701 #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
702
703 void usc_process_rxoverrun_sync( struct mgsl_struct *info );
704 void usc_start_receiver( struct mgsl_struct *info );
705 void usc_stop_receiver( struct mgsl_struct *info );
706
707 void usc_start_transmitter( struct mgsl_struct *info );
708 void usc_stop_transmitter( struct mgsl_struct *info );
709 void usc_set_txidle( struct mgsl_struct *info );
710 void usc_load_txfifo( struct mgsl_struct *info );
711
712 void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
713 void usc_enable_loopback( struct mgsl_struct *info, int enable );
714
715 void usc_get_serial_signals( struct mgsl_struct *info );
716 void usc_set_serial_signals( struct mgsl_struct *info );
717
718 void usc_reset( struct mgsl_struct *info );
719
720 void usc_set_sync_mode( struct mgsl_struct *info );
721 void usc_set_sdlc_mode( struct mgsl_struct *info );
722 void usc_set_async_mode( struct mgsl_struct *info );
723 void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
724
725 void usc_loopback_frame( struct mgsl_struct *info );
726
727 void mgsl_tx_timeout(unsigned long context);
728
729
730 void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
731 void usc_loopmode_insert_request( struct mgsl_struct * info );
732 int usc_loopmode_active( struct mgsl_struct * info);
733 void usc_loopmode_send_done( struct mgsl_struct * info );
734 int usc_loopmode_send_active( struct mgsl_struct * info );
735
736 int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
737
738 #ifdef CONFIG_SYNCLINK_SYNCPPP
739 /* SPPP/HDLC stuff */
740 void mgsl_sppp_init(struct mgsl_struct *info);
741 void mgsl_sppp_delete(struct mgsl_struct *info);
742 int mgsl_sppp_open(struct net_device *d);
743 int mgsl_sppp_close(struct net_device *d);
744 void mgsl_sppp_tx_timeout(struct net_device *d);
745 int mgsl_sppp_tx(struct sk_buff *skb, struct net_device *d);
746 void mgsl_sppp_rx_done(struct mgsl_struct *info, char *buf, int size);
747 void mgsl_sppp_tx_done(struct mgsl_struct *info);
748 int mgsl_sppp_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
749 struct net_device_stats *mgsl_net_stats(struct net_device *dev);
750 #endif
751
752 /*
753 * Defines a BUS descriptor value for the PCI adapter
754 * local bus address ranges.
755 */
756
757 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
758 (0x00400020 + \
759 ((WrHold) << 30) + \
760 ((WrDly) << 28) + \
761 ((RdDly) << 26) + \
762 ((Nwdd) << 20) + \
763 ((Nwad) << 15) + \
764 ((Nxda) << 13) + \
765 ((Nrdd) << 11) + \
766 ((Nrad) << 6) )
767
768 void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
769
770 /*
771 * Adapter diagnostic routines
772 */
773 BOOLEAN mgsl_register_test( struct mgsl_struct *info );
774 BOOLEAN mgsl_irq_test( struct mgsl_struct *info );
775 BOOLEAN mgsl_dma_test( struct mgsl_struct *info );
776 BOOLEAN mgsl_memory_test( struct mgsl_struct *info );
777 int mgsl_adapter_test( struct mgsl_struct *info );
778
779 /*
780 * device and resource management routines
781 */
782 int mgsl_claim_resources(struct mgsl_struct *info);
783 void mgsl_release_resources(struct mgsl_struct *info);
784 void mgsl_add_device(struct mgsl_struct *info);
785 struct mgsl_struct* mgsl_allocate_device(void);
786 int mgsl_enum_isa_devices(void);
787
788 /*
789 * DMA buffer manupulation functions.
790 */
791 void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
792 int mgsl_get_rx_frame( struct mgsl_struct *info );
793 int mgsl_get_raw_rx_frame( struct mgsl_struct *info );
794 void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
795 void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
796 int num_free_tx_dma_buffers(struct mgsl_struct *info);
797 void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
798 void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
799
800 /*
801 * DMA and Shared Memory buffer allocation and formatting
802 */
803 int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
804 void mgsl_free_dma_buffers(struct mgsl_struct *info);
805 int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
806 void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
807 int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
808 void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
809 int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
810 void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
811 int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
812 void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
813 int load_next_tx_holding_buffer(struct mgsl_struct *info);
814 int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
815
816 /*
817 * Bottom half interrupt handlers
818 */
819 void mgsl_bh_handler(void* Context);
820 void mgsl_bh_receive(struct mgsl_struct *info);
821 void mgsl_bh_transmit(struct mgsl_struct *info);
822 void mgsl_bh_status(struct mgsl_struct *info);
823
824 /*
825 * Interrupt handler routines and dispatch table.
826 */
827 void mgsl_isr_null( struct mgsl_struct *info );
828 void mgsl_isr_transmit_data( struct mgsl_struct *info );
829 void mgsl_isr_receive_data( struct mgsl_struct *info );
830 void mgsl_isr_receive_status( struct mgsl_struct *info );
831 void mgsl_isr_transmit_status( struct mgsl_struct *info );
832 void mgsl_isr_io_pin( struct mgsl_struct *info );
833 void mgsl_isr_misc( struct mgsl_struct *info );
834 void mgsl_isr_receive_dma( struct mgsl_struct *info );
835 void mgsl_isr_transmit_dma( struct mgsl_struct *info );
836
837 typedef void (*isr_dispatch_func)(struct mgsl_struct *);
838
839 isr_dispatch_func UscIsrTable[7] =
840 {
841 mgsl_isr_null,
842 mgsl_isr_misc,
843 mgsl_isr_io_pin,
844 mgsl_isr_transmit_data,
845 mgsl_isr_transmit_status,
846 mgsl_isr_receive_data,
847 mgsl_isr_receive_status
848 };
849
850 /*
851 * ioctl call handlers
852 */
853 static int tiocmget(struct tty_struct *tty, struct file *file);
854 static int tiocmset(struct tty_struct *tty, struct file *file,
855 unsigned int set, unsigned int clear);
856 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
857 *user_icount);
858 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS *user_params);
859 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS *new_params);
860 static int mgsl_get_txidle(struct mgsl_struct * info, int*idle_mode);
861 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
862 static int mgsl_txenable(struct mgsl_struct * info, int enable);
863 static int mgsl_txabort(struct mgsl_struct * info);
864 static int mgsl_rxenable(struct mgsl_struct * info, int enable);
865 static int mgsl_wait_event(struct mgsl_struct * info, int * mask);
866 static int mgsl_loopmode_send_done( struct mgsl_struct * info );
867
868 #define jiffies_from_ms(a) ((((a) * HZ)/1000)+1)
869
870 /*
871 * Global linked list of SyncLink devices
872 */
873 struct mgsl_struct *mgsl_device_list;
874 static int mgsl_device_count;
875
876 /*
877 * Set this param to non-zero to load eax with the
878 * .text section address and breakpoint on module load.
879 * This is useful for use with gdb and add-symbol-file command.
880 */
881 static int break_on_load;
882
883 /*
884 * Driver major number, defaults to zero to get auto
885 * assigned major number. May be forced as module parameter.
886 */
887 static int ttymajor;
888
889 /*
890 * Array of user specified options for ISA adapters.
891 */
892 static int io[MAX_ISA_DEVICES];
893 static int irq[MAX_ISA_DEVICES];
894 static int dma[MAX_ISA_DEVICES];
895 static int debug_level;
896 static int maxframe[MAX_TOTAL_DEVICES];
897 static int dosyncppp[MAX_TOTAL_DEVICES];
898 static int txdmabufs[MAX_TOTAL_DEVICES];
899 static int txholdbufs[MAX_TOTAL_DEVICES];
900
901 MODULE_PARM(break_on_load,"i");
902 MODULE_PARM(ttymajor,"i");
903 MODULE_PARM(io,"1-" __MODULE_STRING(MAX_ISA_DEVICES) "i");
904 MODULE_PARM(irq,"1-" __MODULE_STRING(MAX_ISA_DEVICES) "i");
905 MODULE_PARM(dma,"1-" __MODULE_STRING(MAX_ISA_DEVICES) "i");
906 MODULE_PARM(debug_level,"i");
907 MODULE_PARM(maxframe,"1-" __MODULE_STRING(MAX_TOTAL_DEVICES) "i");
908 MODULE_PARM(dosyncppp,"1-" __MODULE_STRING(MAX_TOTAL_DEVICES) "i");
909 MODULE_PARM(txdmabufs,"1-" __MODULE_STRING(MAX_TOTAL_DEVICES) "i");
910 MODULE_PARM(txholdbufs,"1-" __MODULE_STRING(MAX_TOTAL_DEVICES) "i");
911
912 static char *driver_name = "SyncLink serial driver";
913 static char *driver_version = "$Revision: 4.12 $";
914
915 static int synclink_init_one (struct pci_dev *dev,
916 const struct pci_device_id *ent);
917 static void synclink_remove_one (struct pci_dev *dev);
918
919 static struct pci_device_id synclink_pci_tbl[] __devinitdata = {
920 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
921 { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
922 { 0, }, /* terminate list */
923 };
924 MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
925
926 MODULE_LICENSE("GPL");
927
928 static struct pci_driver synclink_pci_driver = {
929 .name = "synclink",
930 .id_table = synclink_pci_tbl,
931 .probe = synclink_init_one,
932 .remove = __devexit_p(synclink_remove_one),
933 };
934
935 static struct tty_driver *serial_driver;
936
937 /* number of characters left in xmit buffer before we ask for more */
938 #define WAKEUP_CHARS 256
939
940
941 static void mgsl_change_params(struct mgsl_struct *info);
942 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
943
944 #ifndef MIN
945 #define MIN(a,b) ((a) < (b) ? (a) : (b))
946 #endif
947
948 /*
949 * 1st function defined in .text section. Calling this function in
950 * init_module() followed by a breakpoint allows a remote debugger
951 * (gdb) to get the .text address for the add-symbol-file command.
952 * This allows remote debugging of dynamically loadable modules.
953 */
954 void* mgsl_get_text_ptr(void);
955 void* mgsl_get_text_ptr() {return mgsl_get_text_ptr;}
956
957 /*
958 * tmp_buf is used as a temporary buffer by mgsl_write. We need to
959 * lock it in case the COPY_FROM_USER blocks while swapping in a page,
960 * and some other program tries to do a serial write at the same time.
961 * Since the lock will only come under contention when the system is
962 * swapping and available memory is low, it makes sense to share one
963 * buffer across all the serial ioports, since it significantly saves
964 * memory if large numbers of serial ports are open.
965 */
966 static unsigned char *tmp_buf;
967 static DECLARE_MUTEX(tmp_buf_sem);
968
969 static inline int mgsl_paranoia_check(struct mgsl_struct *info,
970 char *name, const char *routine)
971 {
972 #ifdef MGSL_PARANOIA_CHECK
973 static const char *badmagic =
974 "Warning: bad magic number for mgsl struct (%s) in %s\n";
975 static const char *badinfo =
976 "Warning: null mgsl_struct for (%s) in %s\n";
977
978 if (!info) {
979 printk(badinfo, name, routine);
980 return 1;
981 }
982 if (info->magic != MGSL_MAGIC) {
983 printk(badmagic, name, routine);
984 return 1;
985 }
986 #endif
987 return 0;
988 }
989
990 /* mgsl_stop() throttle (stop) transmitter
991 *
992 * Arguments: tty pointer to tty info structure
993 * Return Value: None
994 */
995 static void mgsl_stop(struct tty_struct *tty)
996 {
997 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
998 unsigned long flags;
999
1000 if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
1001 return;
1002
1003 if ( debug_level >= DEBUG_LEVEL_INFO )
1004 printk("mgsl_stop(%s)\n",info->device_name);
1005
1006 spin_lock_irqsave(&info->irq_spinlock,flags);
1007 if (info->tx_enabled)
1008 usc_stop_transmitter(info);
1009 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1010
1011 } /* end of mgsl_stop() */
1012
1013 /* mgsl_start() release (start) transmitter
1014 *
1015 * Arguments: tty pointer to tty info structure
1016 * Return Value: None
1017 */
1018 static void mgsl_start(struct tty_struct *tty)
1019 {
1020 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
1021 unsigned long flags;
1022
1023 if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1024 return;
1025
1026 if ( debug_level >= DEBUG_LEVEL_INFO )
1027 printk("mgsl_start(%s)\n",info->device_name);
1028
1029 spin_lock_irqsave(&info->irq_spinlock,flags);
1030 if (!info->tx_enabled)
1031 usc_start_transmitter(info);
1032 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1033
1034 } /* end of mgsl_start() */
1035
1036 /*
1037 * Bottom half work queue access functions
1038 */
1039
1040 /* mgsl_bh_action() Return next bottom half action to perform.
1041 * Return Value: BH action code or 0 if nothing to do.
1042 */
1043 int mgsl_bh_action(struct mgsl_struct *info)
1044 {
1045 unsigned long flags;
1046 int rc = 0;
1047
1048 spin_lock_irqsave(&info->irq_spinlock,flags);
1049
1050 if (info->pending_bh & BH_RECEIVE) {
1051 info->pending_bh &= ~BH_RECEIVE;
1052 rc = BH_RECEIVE;
1053 } else if (info->pending_bh & BH_TRANSMIT) {
1054 info->pending_bh &= ~BH_TRANSMIT;
1055 rc = BH_TRANSMIT;
1056 } else if (info->pending_bh & BH_STATUS) {
1057 info->pending_bh &= ~BH_STATUS;
1058 rc = BH_STATUS;
1059 }
1060
1061 if (!rc) {
1062 /* Mark BH routine as complete */
1063 info->bh_running = 0;
1064 info->bh_requested = 0;
1065 }
1066
1067 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1068
1069 return rc;
1070 }
1071
1072 /*
1073 * Perform bottom half processing of work items queued by ISR.
1074 */
1075 void mgsl_bh_handler(void* Context)
1076 {
1077 struct mgsl_struct *info = (struct mgsl_struct*)Context;
1078 int action;
1079
1080 if (!info)
1081 return;
1082
1083 if ( debug_level >= DEBUG_LEVEL_BH )
1084 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1085 __FILE__,__LINE__,info->device_name);
1086
1087 info->bh_running = 1;
1088
1089 while((action = mgsl_bh_action(info)) != 0) {
1090
1091 /* Process work item */
1092 if ( debug_level >= DEBUG_LEVEL_BH )
1093 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1094 __FILE__,__LINE__,action);
1095
1096 switch (action) {
1097
1098 case BH_RECEIVE:
1099 mgsl_bh_receive(info);
1100 break;
1101 case BH_TRANSMIT:
1102 mgsl_bh_transmit(info);
1103 break;
1104 case BH_STATUS:
1105 mgsl_bh_status(info);
1106 break;
1107 default:
1108 /* unknown work item ID */
1109 printk("Unknown work item ID=%08X!\n", action);
1110 break;
1111 }
1112 }
1113
1114 if ( debug_level >= DEBUG_LEVEL_BH )
1115 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1116 __FILE__,__LINE__,info->device_name);
1117 }
1118
1119 void mgsl_bh_receive(struct mgsl_struct *info)
1120 {
1121 int (*get_rx_frame)(struct mgsl_struct *info) =
1122 (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1123
1124 if ( debug_level >= DEBUG_LEVEL_BH )
1125 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1126 __FILE__,__LINE__,info->device_name);
1127
1128 while( (get_rx_frame)(info) );
1129 }
1130
1131 void mgsl_bh_transmit(struct mgsl_struct *info)
1132 {
1133 struct tty_struct *tty = info->tty;
1134 unsigned long flags;
1135
1136 if ( debug_level >= DEBUG_LEVEL_BH )
1137 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1138 __FILE__,__LINE__,info->device_name);
1139
1140 if (tty) {
1141 if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
1142 tty->ldisc.write_wakeup) {
1143 if ( debug_level >= DEBUG_LEVEL_BH )
1144 printk( "%s(%d):calling ldisc.write_wakeup on %s\n",
1145 __FILE__,__LINE__,info->device_name);
1146 (tty->ldisc.write_wakeup)(tty);
1147 }
1148 wake_up_interruptible(&tty->write_wait);
1149 }
1150
1151 /* if transmitter idle and loopmode_send_done_requested
1152 * then start echoing RxD to TxD
1153 */
1154 spin_lock_irqsave(&info->irq_spinlock,flags);
1155 if ( !info->tx_active && info->loopmode_send_done_requested )
1156 usc_loopmode_send_done( info );
1157 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1158 }
1159
1160 void mgsl_bh_status(struct mgsl_struct *info)
1161 {
1162 if ( debug_level >= DEBUG_LEVEL_BH )
1163 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1164 __FILE__,__LINE__,info->device_name);
1165
1166 info->ri_chkcount = 0;
1167 info->dsr_chkcount = 0;
1168 info->dcd_chkcount = 0;
1169 info->cts_chkcount = 0;
1170 }
1171
1172 /* mgsl_isr_receive_status()
1173 *
1174 * Service a receive status interrupt. The type of status
1175 * interrupt is indicated by the state of the RCSR.
1176 * This is only used for HDLC mode.
1177 *
1178 * Arguments: info pointer to device instance data
1179 * Return Value: None
1180 */
1181 void mgsl_isr_receive_status( struct mgsl_struct *info )
1182 {
1183 u16 status = usc_InReg( info, RCSR );
1184
1185 if ( debug_level >= DEBUG_LEVEL_ISR )
1186 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1187 __FILE__,__LINE__,status);
1188
1189 if ( (status & RXSTATUS_ABORT_RECEIVED) &&
1190 info->loopmode_insert_requested &&
1191 usc_loopmode_active(info) )
1192 {
1193 ++info->icount.rxabort;
1194 info->loopmode_insert_requested = FALSE;
1195
1196 /* clear CMR:13 to start echoing RxD to TxD */
1197 info->cmr_value &= ~BIT13;
1198 usc_OutReg(info, CMR, info->cmr_value);
1199
1200 /* disable received abort irq (no longer required) */
1201 usc_OutReg(info, RICR,
1202 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1203 }
1204
1205 if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
1206 if (status & RXSTATUS_EXITED_HUNT)
1207 info->icount.exithunt++;
1208 if (status & RXSTATUS_IDLE_RECEIVED)
1209 info->icount.rxidle++;
1210 wake_up_interruptible(&info->event_wait_q);
1211 }
1212
1213 if (status & RXSTATUS_OVERRUN){
1214 info->icount.rxover++;
1215 usc_process_rxoverrun_sync( info );
1216 }
1217
1218 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1219 usc_UnlatchRxstatusBits( info, status );
1220
1221 } /* end of mgsl_isr_receive_status() */
1222
1223 /* mgsl_isr_transmit_status()
1224 *
1225 * Service a transmit status interrupt
1226 * HDLC mode :end of transmit frame
1227 * Async mode:all data is sent
1228 * transmit status is indicated by bits in the TCSR.
1229 *
1230 * Arguments: info pointer to device instance data
1231 * Return Value: None
1232 */
1233 void mgsl_isr_transmit_status( struct mgsl_struct *info )
1234 {
1235 u16 status = usc_InReg( info, TCSR );
1236
1237 if ( debug_level >= DEBUG_LEVEL_ISR )
1238 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1239 __FILE__,__LINE__,status);
1240
1241 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1242 usc_UnlatchTxstatusBits( info, status );
1243
1244 if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1245 {
1246 /* finished sending HDLC abort. This may leave */
1247 /* the TxFifo with data from the aborted frame */
1248 /* so purge the TxFifo. Also shutdown the DMA */
1249 /* channel in case there is data remaining in */
1250 /* the DMA buffer */
1251 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1252 usc_RTCmd( info, RTCmd_PurgeTxFifo );
1253 }
1254
1255 if ( status & TXSTATUS_EOF_SENT )
1256 info->icount.txok++;
1257 else if ( status & TXSTATUS_UNDERRUN )
1258 info->icount.txunder++;
1259 else if ( status & TXSTATUS_ABORT_SENT )
1260 info->icount.txabort++;
1261 else
1262 info->icount.txunder++;
1263
1264 info->tx_active = 0;
1265 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1266 del_timer(&info->tx_timer);
1267
1268 if ( info->drop_rts_on_tx_done ) {
1269 usc_get_serial_signals( info );
1270 if ( info->serial_signals & SerialSignal_RTS ) {
1271 info->serial_signals &= ~SerialSignal_RTS;
1272 usc_set_serial_signals( info );
1273 }
1274 info->drop_rts_on_tx_done = 0;
1275 }
1276
1277 #ifdef CONFIG_SYNCLINK_SYNCPPP
1278 if (info->netcount)
1279 mgsl_sppp_tx_done(info);
1280 else
1281 #endif
1282 {
1283 if (info->tty->stopped || info->tty->hw_stopped) {
1284 usc_stop_transmitter(info);
1285 return;
1286 }
1287 info->pending_bh |= BH_TRANSMIT;
1288 }
1289
1290 } /* end of mgsl_isr_transmit_status() */
1291
1292 /* mgsl_isr_io_pin()
1293 *
1294 * Service an Input/Output pin interrupt. The type of
1295 * interrupt is indicated by bits in the MISR
1296 *
1297 * Arguments: info pointer to device instance data
1298 * Return Value: None
1299 */
1300 void mgsl_isr_io_pin( struct mgsl_struct *info )
1301 {
1302 struct mgsl_icount *icount;
1303 u16 status = usc_InReg( info, MISR );
1304
1305 if ( debug_level >= DEBUG_LEVEL_ISR )
1306 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1307 __FILE__,__LINE__,status);
1308
1309 usc_ClearIrqPendingBits( info, IO_PIN );
1310 usc_UnlatchIostatusBits( info, status );
1311
1312 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1313 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1314 icount = &info->icount;
1315 /* update input line counters */
1316 if (status & MISCSTATUS_RI_LATCHED) {
1317 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1318 usc_DisablestatusIrqs(info,SICR_RI);
1319 icount->rng++;
1320 if ( status & MISCSTATUS_RI )
1321 info->input_signal_events.ri_up++;
1322 else
1323 info->input_signal_events.ri_down++;
1324 }
1325 if (status & MISCSTATUS_DSR_LATCHED) {
1326 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1327 usc_DisablestatusIrqs(info,SICR_DSR);
1328 icount->dsr++;
1329 if ( status & MISCSTATUS_DSR )
1330 info->input_signal_events.dsr_up++;
1331 else
1332 info->input_signal_events.dsr_down++;
1333 }
1334 if (status & MISCSTATUS_DCD_LATCHED) {
1335 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1336 usc_DisablestatusIrqs(info,SICR_DCD);
1337 icount->dcd++;
1338 if (status & MISCSTATUS_DCD) {
1339 info->input_signal_events.dcd_up++;
1340 #ifdef CONFIG_SYNCLINK_SYNCPPP
1341 if (info->netcount)
1342 sppp_reopen(info->netdev);
1343 #endif
1344 } else
1345 info->input_signal_events.dcd_down++;
1346 }
1347 if (status & MISCSTATUS_CTS_LATCHED)
1348 {
1349 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1350 usc_DisablestatusIrqs(info,SICR_CTS);
1351 icount->cts++;
1352 if ( status & MISCSTATUS_CTS )
1353 info->input_signal_events.cts_up++;
1354 else
1355 info->input_signal_events.cts_down++;
1356 }
1357 wake_up_interruptible(&info->status_event_wait_q);
1358 wake_up_interruptible(&info->event_wait_q);
1359
1360 if ( (info->flags & ASYNC_CHECK_CD) &&
1361 (status & MISCSTATUS_DCD_LATCHED) ) {
1362 if ( debug_level >= DEBUG_LEVEL_ISR )
1363 printk("%s CD now %s...", info->device_name,
1364 (status & MISCSTATUS_DCD) ? "on" : "off");
1365 if (status & MISCSTATUS_DCD)
1366 wake_up_interruptible(&info->open_wait);
1367 else {
1368 if ( debug_level >= DEBUG_LEVEL_ISR )
1369 printk("doing serial hangup...");
1370 if (info->tty)
1371 tty_hangup(info->tty);
1372 }
1373 }
1374
1375 if ( (info->flags & ASYNC_CTS_FLOW) &&
1376 (status & MISCSTATUS_CTS_LATCHED) ) {
1377 if (info->tty->hw_stopped) {
1378 if (status & MISCSTATUS_CTS) {
1379 if ( debug_level >= DEBUG_LEVEL_ISR )
1380 printk("CTS tx start...");
1381 if (info->tty)
1382 info->tty->hw_stopped = 0;
1383 usc_start_transmitter(info);
1384 info->pending_bh |= BH_TRANSMIT;
1385 return;
1386 }
1387 } else {
1388 if (!(status & MISCSTATUS_CTS)) {
1389 if ( debug_level >= DEBUG_LEVEL_ISR )
1390 printk("CTS tx stop...");
1391 if (info->tty)
1392 info->tty->hw_stopped = 1;
1393 usc_stop_transmitter(info);
1394 }
1395 }
1396 }
1397 }
1398
1399 info->pending_bh |= BH_STATUS;
1400
1401 /* for diagnostics set IRQ flag */
1402 if ( status & MISCSTATUS_TXC_LATCHED ){
1403 usc_OutReg( info, SICR,
1404 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1405 usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1406 info->irq_occurred = 1;
1407 }
1408
1409 } /* end of mgsl_isr_io_pin() */
1410
1411 /* mgsl_isr_transmit_data()
1412 *
1413 * Service a transmit data interrupt (async mode only).
1414 *
1415 * Arguments: info pointer to device instance data
1416 * Return Value: None
1417 */
1418 void mgsl_isr_transmit_data( struct mgsl_struct *info )
1419 {
1420 if ( debug_level >= DEBUG_LEVEL_ISR )
1421 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1422 __FILE__,__LINE__,info->xmit_cnt);
1423
1424 usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1425
1426 if (info->tty->stopped || info->tty->hw_stopped) {
1427 usc_stop_transmitter(info);
1428 return;
1429 }
1430
1431 if ( info->xmit_cnt )
1432 usc_load_txfifo( info );
1433 else
1434 info->tx_active = 0;
1435
1436 if (info->xmit_cnt < WAKEUP_CHARS)
1437 info->pending_bh |= BH_TRANSMIT;
1438
1439 } /* end of mgsl_isr_transmit_data() */
1440
1441 /* mgsl_isr_receive_data()
1442 *
1443 * Service a receive data interrupt. This occurs
1444 * when operating in asynchronous interrupt transfer mode.
1445 * The receive data FIFO is flushed to the receive data buffers.
1446 *
1447 * Arguments: info pointer to device instance data
1448 * Return Value: None
1449 */
1450 void mgsl_isr_receive_data( struct mgsl_struct *info )
1451 {
1452 int Fifocount;
1453 u16 status;
1454 unsigned char DataByte;
1455 struct tty_struct *tty = info->tty;
1456 struct mgsl_icount *icount = &info->icount;
1457
1458 if ( debug_level >= DEBUG_LEVEL_ISR )
1459 printk("%s(%d):mgsl_isr_receive_data\n",
1460 __FILE__,__LINE__);
1461
1462 usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1463
1464 /* select FIFO status for RICR readback */
1465 usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1466
1467 /* clear the Wordstatus bit so that status readback */
1468 /* only reflects the status of this byte */
1469 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1470
1471 /* flush the receive FIFO */
1472
1473 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1474 /* read one byte from RxFIFO */
1475 outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1476 info->io_base + CCAR );
1477 DataByte = inb( info->io_base + CCAR );
1478
1479 /* get the status of the received byte */
1480 status = usc_InReg(info, RCSR);
1481 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1482 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
1483 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1484
1485 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
1486 continue;
1487
1488 *tty->flip.char_buf_ptr = DataByte;
1489 icount->rx++;
1490
1491 *tty->flip.flag_buf_ptr = 0;
1492 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1493 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
1494 printk("rxerr=%04X\n",status);
1495 /* update error statistics */
1496 if ( status & RXSTATUS_BREAK_RECEIVED ) {
1497 status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
1498 icount->brk++;
1499 } else if (status & RXSTATUS_PARITY_ERROR)
1500 icount->parity++;
1501 else if (status & RXSTATUS_FRAMING_ERROR)
1502 icount->frame++;
1503 else if (status & RXSTATUS_OVERRUN) {
1504 /* must issue purge fifo cmd before */
1505 /* 16C32 accepts more receive chars */
1506 usc_RTCmd(info,RTCmd_PurgeRxFifo);
1507 icount->overrun++;
1508 }
1509
1510 /* discard char if tty control flags say so */
1511 if (status & info->ignore_status_mask)
1512 continue;
1513
1514 status &= info->read_status_mask;
1515
1516 if (status & RXSTATUS_BREAK_RECEIVED) {
1517 *tty->flip.flag_buf_ptr = TTY_BREAK;
1518 if (info->flags & ASYNC_SAK)
1519 do_SAK(tty);
1520 } else if (status & RXSTATUS_PARITY_ERROR)
1521 *tty->flip.flag_buf_ptr = TTY_PARITY;
1522 else if (status & RXSTATUS_FRAMING_ERROR)
1523 *tty->flip.flag_buf_ptr = TTY_FRAME;
1524 if (status & RXSTATUS_OVERRUN) {
1525 /* Overrun is special, since it's
1526 * reported immediately, and doesn't
1527 * affect the current character
1528 */
1529 if (tty->flip.count < TTY_FLIPBUF_SIZE) {
1530 tty->flip.count++;
1531 tty->flip.flag_buf_ptr++;
1532 tty->flip.char_buf_ptr++;
1533 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
1534 }
1535 }
1536 } /* end of if (error) */
1537
1538 tty->flip.flag_buf_ptr++;
1539 tty->flip.char_buf_ptr++;
1540 tty->flip.count++;
1541 }
1542
1543 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1544 printk("%s(%d):mgsl_isr_receive_data flip count=%d\n",
1545 __FILE__,__LINE__,tty->flip.count);
1546 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1547 __FILE__,__LINE__,icount->rx,icount->brk,
1548 icount->parity,icount->frame,icount->overrun);
1549 }
1550
1551 if ( tty->flip.count )
1552 tty_flip_buffer_push(tty);
1553 }
1554
1555 /* mgsl_isr_misc()
1556 *
1557 * Service a miscellaneos interrupt source.
1558 *
1559 * Arguments: info pointer to device extension (instance data)
1560 * Return Value: None
1561 */
1562 void mgsl_isr_misc( struct mgsl_struct *info )
1563 {
1564 u16 status = usc_InReg( info, MISR );
1565
1566 if ( debug_level >= DEBUG_LEVEL_ISR )
1567 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1568 __FILE__,__LINE__,status);
1569
1570 usc_ClearIrqPendingBits( info, MISC );
1571 usc_UnlatchMiscstatusBits( info, status );
1572
1573 } /* end of mgsl_isr_misc() */
1574
1575 /* mgsl_isr_null()
1576 *
1577 * Services undefined interrupt vectors from the
1578 * USC. (hence this function SHOULD never be called)
1579 *
1580 * Arguments: info pointer to device extension (instance data)
1581 * Return Value: None
1582 */
1583 void mgsl_isr_null( struct mgsl_struct *info )
1584 {
1585
1586 } /* end of mgsl_isr_null() */
1587
1588 /* mgsl_isr_receive_dma()
1589 *
1590 * Service a receive DMA channel interrupt.
1591 * For this driver there are two sources of receive DMA interrupts
1592 * as identified in the Receive DMA mode Register (RDMR):
1593 *
1594 * BIT3 EOA/EOL End of List, all receive buffers in receive
1595 * buffer list have been filled (no more free buffers
1596 * available). The DMA controller has shut down.
1597 *
1598 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1599 * DMA buffer is terminated in response to completion
1600 * of a good frame or a frame with errors. The status
1601 * of the frame is stored in the buffer entry in the
1602 * list of receive buffer entries.
1603 *
1604 * Arguments: info pointer to device instance data
1605 * Return Value: None
1606 */
1607 void mgsl_isr_receive_dma( struct mgsl_struct *info )
1608 {
1609 u16 status;
1610
1611 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1612 usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
1613
1614 /* Read the receive DMA status to identify interrupt type. */
1615 /* This also clears the status bits. */
1616 status = usc_InDmaReg( info, RDMR );
1617
1618 if ( debug_level >= DEBUG_LEVEL_ISR )
1619 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1620 __FILE__,__LINE__,info->device_name,status);
1621
1622 info->pending_bh |= BH_RECEIVE;
1623
1624 if ( status & BIT3 ) {
1625 info->rx_overflow = 1;
1626 info->icount.buf_overrun++;
1627 }
1628
1629 } /* end of mgsl_isr_receive_dma() */
1630
1631 /* mgsl_isr_transmit_dma()
1632 *
1633 * This function services a transmit DMA channel interrupt.
1634 *
1635 * For this driver there is one source of transmit DMA interrupts
1636 * as identified in the Transmit DMA Mode Register (TDMR):
1637 *
1638 * BIT2 EOB End of Buffer. This interrupt occurs when a
1639 * transmit DMA buffer has been emptied.
1640 *
1641 * The driver maintains enough transmit DMA buffers to hold at least
1642 * one max frame size transmit frame. When operating in a buffered
1643 * transmit mode, there may be enough transmit DMA buffers to hold at
1644 * least two or more max frame size frames. On an EOB condition,
1645 * determine if there are any queued transmit buffers and copy into
1646 * transmit DMA buffers if we have room.
1647 *
1648 * Arguments: info pointer to device instance data
1649 * Return Value: None
1650 */
1651 void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1652 {
1653 u16 status;
1654
1655 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1656 usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
1657
1658 /* Read the transmit DMA status to identify interrupt type. */
1659 /* This also clears the status bits. */
1660
1661 status = usc_InDmaReg( info, TDMR );
1662
1663 if ( debug_level >= DEBUG_LEVEL_ISR )
1664 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1665 __FILE__,__LINE__,info->device_name,status);
1666
1667 if ( status & BIT2 ) {
1668 --info->tx_dma_buffers_used;
1669
1670 /* if there are transmit frames queued,
1671 * try to load the next one
1672 */
1673 if ( load_next_tx_holding_buffer(info) ) {
1674 /* if call returns non-zero value, we have
1675 * at least one free tx holding buffer
1676 */
1677 info->pending_bh |= BH_TRANSMIT;
1678 }
1679 }
1680
1681 } /* end of mgsl_isr_transmit_dma() */
1682
1683 /* mgsl_interrupt()
1684 *
1685 * Interrupt service routine entry point.
1686 *
1687 * Arguments:
1688 *
1689 * irq interrupt number that caused interrupt
1690 * dev_id device ID supplied during interrupt registration
1691 * regs interrupted processor context
1692 *
1693 * Return Value: None
1694 */
1695 static irqreturn_t mgsl_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1696 {
1697 struct mgsl_struct * info;
1698 u16 UscVector;
1699 u16 DmaVector;
1700
1701 if ( debug_level >= DEBUG_LEVEL_ISR )
1702 printk("%s(%d):mgsl_interrupt(%d)entry.\n",
1703 __FILE__,__LINE__,irq);
1704
1705 info = (struct mgsl_struct *)dev_id;
1706 if (!info)
1707 return IRQ_NONE;
1708
1709 spin_lock(&info->irq_spinlock);
1710
1711 for(;;) {
1712 /* Read the interrupt vectors from hardware. */
1713 UscVector = usc_InReg(info, IVR) >> 9;
1714 DmaVector = usc_InDmaReg(info, DIVR);
1715
1716 if ( debug_level >= DEBUG_LEVEL_ISR )
1717 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1718 __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1719
1720 if ( !UscVector && !DmaVector )
1721 break;
1722
1723 /* Dispatch interrupt vector */
1724 if ( UscVector )
1725 (*UscIsrTable[UscVector])(info);
1726 else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1727 mgsl_isr_transmit_dma(info);
1728 else
1729 mgsl_isr_receive_dma(info);
1730
1731 if ( info->isr_overflow ) {
1732 printk(KERN_ERR"%s(%d):%s isr overflow irq=%d\n",
1733 __FILE__,__LINE__,info->device_name, irq);
1734 usc_DisableMasterIrqBit(info);
1735 usc_DisableDmaInterrupts(info,DICR_MASTER);
1736 break;
1737 }
1738 }
1739
1740 /* Request bottom half processing if there's something
1741 * for it to do and the bh is not already running
1742 */
1743
1744 if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1745 if ( debug_level >= DEBUG_LEVEL_ISR )
1746 printk("%s(%d):%s queueing bh task.\n",
1747 __FILE__,__LINE__,info->device_name);
1748 schedule_work(&info->task);
1749 info->bh_requested = 1;
1750 }
1751
1752 spin_unlock(&info->irq_spinlock);
1753
1754 if ( debug_level >= DEBUG_LEVEL_ISR )
1755 printk("%s(%d):mgsl_interrupt(%d)exit.\n",
1756 __FILE__,__LINE__,irq);
1757 return IRQ_HANDLED;
1758 } /* end of mgsl_interrupt() */
1759
1760 /* startup()
1761 *
1762 * Initialize and start device.
1763 *
1764 * Arguments: info pointer to device instance data
1765 * Return Value: 0 if success, otherwise error code
1766 */
1767 static int startup(struct mgsl_struct * info)
1768 {
1769 int retval = 0;
1770
1771 if ( debug_level >= DEBUG_LEVEL_INFO )
1772 printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1773
1774 if (info->flags & ASYNC_INITIALIZED)
1775 return 0;
1776
1777 if (!info->xmit_buf) {
1778 /* allocate a page of memory for a transmit buffer */
1779 info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1780 if (!info->xmit_buf) {
1781 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1782 __FILE__,__LINE__,info->device_name);
1783 return -ENOMEM;
1784 }
1785 }
1786
1787 info->pending_bh = 0;
1788
1789 init_timer(&info->tx_timer);
1790 info->tx_timer.data = (unsigned long)info;
1791 info->tx_timer.function = mgsl_tx_timeout;
1792
1793 /* Allocate and claim adapter resources */
1794 retval = mgsl_claim_resources(info);
1795
1796 /* perform existence check and diagnostics */
1797 if ( !retval )
1798 retval = mgsl_adapter_test(info);
1799
1800 if ( retval ) {
1801 if (capable(CAP_SYS_ADMIN) && info->tty)
1802 set_bit(TTY_IO_ERROR, &info->tty->flags);
1803 mgsl_release_resources(info);
1804 return retval;
1805 }
1806
1807 /* program hardware for current parameters */
1808 mgsl_change_params(info);
1809
1810 if (info->tty)
1811 clear_bit(TTY_IO_ERROR, &info->tty->flags);
1812
1813 info->flags |= ASYNC_INITIALIZED;
1814
1815 return 0;
1816
1817 } /* end of startup() */
1818
1819 /* shutdown()
1820 *
1821 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1822 *
1823 * Arguments: info pointer to device instance data
1824 * Return Value: None
1825 */
1826 static void shutdown(struct mgsl_struct * info)
1827 {
1828 unsigned long flags;
1829
1830 if (!(info->flags & ASYNC_INITIALIZED))
1831 return;
1832
1833 if (debug_level >= DEBUG_LEVEL_INFO)
1834 printk("%s(%d):mgsl_shutdown(%s)\n",
1835 __FILE__,__LINE__, info->device_name );
1836
1837 /* clear status wait queue because status changes */
1838 /* can't happen after shutting down the hardware */
1839 wake_up_interruptible(&info->status_event_wait_q);
1840 wake_up_interruptible(&info->event_wait_q);
1841
1842 del_timer(&info->tx_timer);
1843
1844 if (info->xmit_buf) {
1845 free_page((unsigned long) info->xmit_buf);
1846 info->xmit_buf = 0;
1847 }
1848
1849 spin_lock_irqsave(&info->irq_spinlock,flags);
1850 usc_DisableMasterIrqBit(info);
1851 usc_stop_receiver(info);
1852 usc_stop_transmitter(info);
1853 usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS +
1854 TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC );
1855 usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
1856
1857 /* Disable DMAEN (Port 7, Bit 14) */
1858 /* This disconnects the DMA request signal from the ISA bus */
1859 /* on the ISA adapter. This has no effect for the PCI adapter */
1860 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
1861
1862 /* Disable INTEN (Port 6, Bit12) */
1863 /* This disconnects the IRQ request signal to the ISA bus */
1864 /* on the ISA adapter. This has no effect for the PCI adapter */
1865 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
1866
1867 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
1868 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1869 usc_set_serial_signals(info);
1870 }
1871
1872 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1873
1874 mgsl_release_resources(info);
1875
1876 if (info->tty)
1877 set_bit(TTY_IO_ERROR, &info->tty->flags);
1878
1879 info->flags &= ~ASYNC_INITIALIZED;
1880
1881 } /* end of shutdown() */
1882
1883 static void mgsl_program_hw(struct mgsl_struct *info)
1884 {
1885 unsigned long flags;
1886
1887 spin_lock_irqsave(&info->irq_spinlock,flags);
1888
1889 usc_stop_receiver(info);
1890 usc_stop_transmitter(info);
1891 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1892
1893 if (info->params.mode == MGSL_MODE_HDLC ||
1894 info->params.mode == MGSL_MODE_RAW ||
1895 info->netcount)
1896 usc_set_sync_mode(info);
1897 else
1898 usc_set_async_mode(info);
1899
1900 usc_set_serial_signals(info);
1901
1902 info->dcd_chkcount = 0;
1903 info->cts_chkcount = 0;
1904 info->ri_chkcount = 0;
1905 info->dsr_chkcount = 0;
1906
1907 usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
1908 usc_EnableInterrupts(info, IO_PIN);
1909 usc_get_serial_signals(info);
1910
1911 if (info->netcount || info->tty->termios->c_cflag & CREAD)
1912 usc_start_receiver(info);
1913
1914 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1915 }
1916
1917 /* Reconfigure adapter based on new parameters
1918 */
1919 static void mgsl_change_params(struct mgsl_struct *info)
1920 {
1921 unsigned cflag;
1922 int bits_per_char;
1923
1924 if (!info->tty || !info->tty->termios)
1925 return;
1926
1927 if (debug_level >= DEBUG_LEVEL_INFO)
1928 printk("%s(%d):mgsl_change_params(%s)\n",
1929 __FILE__,__LINE__, info->device_name );
1930
1931 cflag = info->tty->termios->c_cflag;
1932
1933 /* if B0 rate (hangup) specified then negate DTR and RTS */
1934 /* otherwise assert DTR and RTS */
1935 if (cflag & CBAUD)
1936 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1937 else
1938 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
1939
1940 /* byte size and parity */
1941
1942 switch (cflag & CSIZE) {
1943 case CS5: info->params.data_bits = 5; break;
1944 case CS6: info->params.data_bits = 6; break;
1945 case CS7: info->params.data_bits = 7; break;
1946 case CS8: info->params.data_bits = 8; break;
1947 /* Never happens, but GCC is too dumb to figure it out */
1948 default: info->params.data_bits = 7; break;
1949 }
1950
1951 if (cflag & CSTOPB)
1952 info->params.stop_bits = 2;
1953 else
1954 info->params.stop_bits = 1;
1955
1956 info->params.parity = ASYNC_PARITY_NONE;
1957 if (cflag & PARENB) {
1958 if (cflag & PARODD)
1959 info->params.parity = ASYNC_PARITY_ODD;
1960 else
1961 info->params.parity = ASYNC_PARITY_EVEN;
1962 #ifdef CMSPAR
1963 if (cflag & CMSPAR)
1964 info->params.parity = ASYNC_PARITY_SPACE;
1965 #endif
1966 }
1967
1968 /* calculate number of jiffies to transmit a full
1969 * FIFO (32 bytes) at specified data rate
1970 */
1971 bits_per_char = info->params.data_bits +
1972 info->params.stop_bits + 1;
1973
1974 /* if port data rate is set to 460800 or less then
1975 * allow tty settings to override, otherwise keep the
1976 * current data rate.
1977 */
1978 if (info->params.data_rate <= 460800)
1979 info->params.data_rate = tty_get_baud_rate(info->tty);
1980
1981 if ( info->params.data_rate ) {
1982 info->timeout = (32*HZ*bits_per_char) /
1983 info->params.data_rate;
1984 }
1985 info->timeout += HZ/50; /* Add .02 seconds of slop */
1986
1987 if (cflag & CRTSCTS)
1988 info->flags |= ASYNC_CTS_FLOW;
1989 else
1990 info->flags &= ~ASYNC_CTS_FLOW;
1991
1992 if (cflag & CLOCAL)
1993 info->flags &= ~ASYNC_CHECK_CD;
1994 else
1995 info->flags |= ASYNC_CHECK_CD;
1996
1997 /* process tty input control flags */
1998
1999 info->read_status_mask = RXSTATUS_OVERRUN;
2000 if (I_INPCK(info->tty))
2001 info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
2002 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2003 info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
2004
2005 if (I_IGNPAR(info->tty))
2006 info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
2007 if (I_IGNBRK(info->tty)) {
2008 info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
2009 /* If ignoring parity and break indicators, ignore
2010 * overruns too. (For real raw support).
2011 */
2012 if (I_IGNPAR(info->tty))
2013 info->ignore_status_mask |= RXSTATUS_OVERRUN;
2014 }
2015
2016 mgsl_program_hw(info);
2017
2018 } /* end of mgsl_change_params() */
2019
2020 /* mgsl_put_char()
2021 *
2022 * Add a character to the transmit buffer.
2023 *
2024 * Arguments: tty pointer to tty information structure
2025 * ch character to add to transmit buffer
2026 *
2027 * Return Value: None
2028 */
2029 static void mgsl_put_char(struct tty_struct *tty, unsigned char ch)
2030 {
2031 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2032 unsigned long flags;
2033
2034 if ( debug_level >= DEBUG_LEVEL_INFO ) {
2035 printk( "%s(%d):mgsl_put_char(%d) on %s\n",
2036 __FILE__,__LINE__,ch,info->device_name);
2037 }
2038
2039 if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
2040 return;
2041
2042 if (!tty || !info->xmit_buf)
2043 return;
2044
2045 spin_lock_irqsave(&info->irq_spinlock,flags);
2046
2047 if ( (info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active ) {
2048
2049 if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2050 info->xmit_buf[info->xmit_head++] = ch;
2051 info->xmit_head &= SERIAL_XMIT_SIZE-1;
2052 info->xmit_cnt++;
2053 }
2054 }
2055
2056 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2057
2058 } /* end of mgsl_put_char() */
2059
2060 /* mgsl_flush_chars()
2061 *
2062 * Enable transmitter so remaining characters in the
2063 * transmit buffer are sent.
2064 *
2065 * Arguments: tty pointer to tty information structure
2066 * Return Value: None
2067 */
2068 static void mgsl_flush_chars(struct tty_struct *tty)
2069 {
2070 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2071 unsigned long flags;
2072
2073 if ( debug_level >= DEBUG_LEVEL_INFO )
2074 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2075 __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2076
2077 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2078 return;
2079
2080 if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2081 !info->xmit_buf)
2082 return;
2083
2084 if ( debug_level >= DEBUG_LEVEL_INFO )
2085 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2086 __FILE__,__LINE__,info->device_name );
2087
2088 spin_lock_irqsave(&info->irq_spinlock,flags);
2089
2090 if (!info->tx_active) {
2091 if ( (info->params.mode == MGSL_MODE_HDLC ||
2092 info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2093 /* operating in synchronous (frame oriented) mode */
2094 /* copy data from circular xmit_buf to */
2095 /* transmit DMA buffer. */
2096 mgsl_load_tx_dma_buffer(info,
2097 info->xmit_buf,info->xmit_cnt);
2098 }
2099 usc_start_transmitter(info);
2100 }
2101
2102 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2103
2104 } /* end of mgsl_flush_chars() */
2105
2106 /* mgsl_write()
2107 *
2108 * Send a block of data
2109 *
2110 * Arguments:
2111 *
2112 * tty pointer to tty information structure
2113 * from_user flag: 1 = from user process
2114 * buf pointer to buffer containing send data
2115 * count size of send data in bytes
2116 *
2117 * Return Value: number of characters written
2118 */
2119 static int mgsl_write(struct tty_struct * tty, int from_user,
2120 const unsigned char *buf, int count)
2121 {
2122 int c, ret = 0, err;
2123 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2124 unsigned long flags;
2125
2126 if ( debug_level >= DEBUG_LEVEL_INFO )
2127 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2128 __FILE__,__LINE__,info->device_name,count);
2129
2130 if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2131 goto cleanup;
2132
2133 if (!tty || !info->xmit_buf || !tmp_buf)
2134 goto cleanup;
2135
2136 if ( info->params.mode == MGSL_MODE_HDLC ||
2137 info->params.mode == MGSL_MODE_RAW ) {
2138 /* operating in synchronous (frame oriented) mode */
2139 /* operating in synchronous (frame oriented) mode */
2140 if (info->tx_active) {
2141
2142 if ( info->params.mode == MGSL_MODE_HDLC ) {
2143 ret = 0;
2144 goto cleanup;
2145 }
2146 /* transmitter is actively sending data -
2147 * if we have multiple transmit dma and
2148 * holding buffers, attempt to queue this
2149 * frame for transmission at a later time.
2150 */
2151 if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2152 /* no tx holding buffers available */
2153 ret = 0;
2154 goto cleanup;
2155 }
2156
2157 /* queue transmit frame request */
2158 ret = count;
2159 if (from_user) {
2160 down(&tmp_buf_sem);
2161 COPY_FROM_USER(err,tmp_buf, buf, count);
2162 if (err) {
2163 if ( debug_level >= DEBUG_LEVEL_INFO )
2164 printk( "%s(%d):mgsl_write(%s) sync user buf copy failed\n",
2165 __FILE__,__LINE__,info->device_name);
2166 ret = -EFAULT;
2167 } else
2168 save_tx_buffer_request(info,tmp_buf,count);
2169 up(&tmp_buf_sem);
2170 }
2171 else
2172 save_tx_buffer_request(info,buf,count);
2173
2174 /* if we have sufficient tx dma buffers,
2175 * load the next buffered tx request
2176 */
2177 spin_lock_irqsave(&info->irq_spinlock,flags);
2178 load_next_tx_holding_buffer(info);
2179 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2180 goto cleanup;
2181 }
2182
2183 /* if operating in HDLC LoopMode and the adapter */
2184 /* has yet to be inserted into the loop, we can't */
2185 /* transmit */
2186
2187 if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2188 !usc_loopmode_active(info) )
2189 {
2190 ret = 0;
2191 goto cleanup;
2192 }
2193
2194 if ( info->xmit_cnt ) {
2195 /* Send accumulated from send_char() calls */
2196 /* as frame and wait before accepting more data. */
2197 ret = 0;
2198
2199 /* copy data from circular xmit_buf to */
2200 /* transmit DMA buffer. */
2201 mgsl_load_tx_dma_buffer(info,
2202 info->xmit_buf,info->xmit_cnt);
2203 if ( debug_level >= DEBUG_LEVEL_INFO )
2204 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2205 __FILE__,__LINE__,info->device_name);
2206 } else {
2207 if ( debug_level >= DEBUG_LEVEL_INFO )
2208 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2209 __FILE__,__LINE__,info->device_name);
2210 ret = count;
2211 info->xmit_cnt = count;
2212 if (from_user) {
2213 down(&tmp_buf_sem);
2214 COPY_FROM_USER(err,tmp_buf, buf, count);
2215 if (err) {
2216 if ( debug_level >= DEBUG_LEVEL_INFO )
2217 printk( "%s(%d):mgsl_write(%s) sync user buf copy failed\n",
2218 __FILE__,__LINE__,info->device_name);
2219 ret = -EFAULT;
2220 } else
2221 mgsl_load_tx_dma_buffer(info,tmp_buf,count);
2222 up(&tmp_buf_sem);
2223 }
2224 else
2225 mgsl_load_tx_dma_buffer(info,buf,count);
2226 }
2227 } else {
2228 if (from_user) {
2229 down(&tmp_buf_sem);
2230 while (1) {
2231 c = MIN(count,
2232 MIN(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2233 SERIAL_XMIT_SIZE - info->xmit_head));
2234 if (c <= 0)
2235 break;
2236
2237 COPY_FROM_USER(err,tmp_buf, buf, c);
2238 c -= err;
2239 if (!c) {
2240 if (!ret)
2241 ret = -EFAULT;
2242 break;
2243 }
2244 spin_lock_irqsave(&info->irq_spinlock,flags);
2245 c = MIN(c, MIN(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2246 SERIAL_XMIT_SIZE - info->xmit_head));
2247 memcpy(info->xmit_buf + info->xmit_head, tmp_buf, c);
2248 info->xmit_head = ((info->xmit_head + c) &
2249 (SERIAL_XMIT_SIZE-1));
2250 info->xmit_cnt += c;
2251 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2252 buf += c;
2253 count -= c;
2254 ret += c;
2255 }
2256 up(&tmp_buf_sem);
2257 } else {
2258 while (1) {
2259 spin_lock_irqsave(&info->irq_spinlock,flags);
2260 c = MIN(count,
2261 MIN(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2262 SERIAL_XMIT_SIZE - info->xmit_head));
2263 if (c <= 0) {
2264 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2265 break;
2266 }
2267 memcpy(info->xmit_buf + info->xmit_head, buf, c);
2268 info->xmit_head = ((info->xmit_head + c) &
2269 (SERIAL_XMIT_SIZE-1));
2270 info->xmit_cnt += c;
2271 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2272 buf += c;
2273 count -= c;
2274 ret += c;
2275 }
2276 }
2277 }
2278
2279 if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2280 spin_lock_irqsave(&info->irq_spinlock,flags);
2281 if (!info->tx_active)
2282 usc_start_transmitter(info);
2283 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2284 }
2285 cleanup:
2286 if ( debug_level >= DEBUG_LEVEL_INFO )
2287 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2288 __FILE__,__LINE__,info->device_name,ret);
2289
2290 return ret;
2291
2292 } /* end of mgsl_write() */
2293
2294 /* mgsl_write_room()
2295 *
2296 * Return the count of free bytes in transmit buffer
2297 *
2298 * Arguments: tty pointer to tty info structure
2299 * Return Value: None
2300 */
2301 static int mgsl_write_room(struct tty_struct *tty)
2302 {
2303 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2304 int ret;
2305
2306 if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2307 return 0;
2308 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2309 if (ret < 0)
2310 ret = 0;
2311
2312 if (debug_level >= DEBUG_LEVEL_INFO)
2313 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2314 __FILE__,__LINE__, info->device_name,ret );
2315
2316 if ( info->params.mode == MGSL_MODE_HDLC ||
2317 info->params.mode == MGSL_MODE_RAW ) {
2318 /* operating in synchronous (frame oriented) mode */
2319 if ( info->tx_active )
2320 return 0;
2321 else
2322 return HDLC_MAX_FRAME_SIZE;
2323 }
2324
2325 return ret;
2326
2327 } /* end of mgsl_write_room() */
2328
2329 /* mgsl_chars_in_buffer()
2330 *
2331 * Return the count of bytes in transmit buffer
2332 *
2333 * Arguments: tty pointer to tty info structure
2334 * Return Value: None
2335 */
2336 static int mgsl_chars_in_buffer(struct tty_struct *tty)
2337 {
2338 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2339
2340 if (debug_level >= DEBUG_LEVEL_INFO)
2341 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2342 __FILE__,__LINE__, info->device_name );
2343
2344 if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2345 return 0;
2346
2347 if (debug_level >= DEBUG_LEVEL_INFO)
2348 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2349 __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2350
2351 if ( info->params.mode == MGSL_MODE_HDLC ||
2352 info->params.mode == MGSL_MODE_RAW ) {
2353 /* operating in synchronous (frame oriented) mode */
2354 if ( info->tx_active )
2355 return info->max_frame_size;
2356 else
2357 return 0;
2358 }
2359
2360 return info->xmit_cnt;
2361 } /* end of mgsl_chars_in_buffer() */
2362
2363 /* mgsl_flush_buffer()
2364 *
2365 * Discard all data in the send buffer
2366 *
2367 * Arguments: tty pointer to tty info structure
2368 * Return Value: None
2369 */
2370 static void mgsl_flush_buffer(struct tty_struct *tty)
2371 {
2372 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2373 unsigned long flags;
2374
2375 if (debug_level >= DEBUG_LEVEL_INFO)
2376 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2377 __FILE__,__LINE__, info->device_name );
2378
2379 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2380 return;
2381
2382 spin_lock_irqsave(&info->irq_spinlock,flags);
2383 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2384 del_timer(&info->tx_timer);
2385 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2386
2387 wake_up_interruptible(&tty->write_wait);
2388 if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
2389 tty->ldisc.write_wakeup)
2390 (tty->ldisc.write_wakeup)(tty);
2391
2392 } /* end of mgsl_flush_buffer() */
2393
2394 /* mgsl_send_xchar()
2395 *
2396 * Send a high-priority XON/XOFF character
2397 *
2398 * Arguments: tty pointer to tty info structure
2399 * ch character to send
2400 * Return Value: None
2401 */
2402 static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2403 {
2404 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2405 unsigned long flags;
2406
2407 if (debug_level >= DEBUG_LEVEL_INFO)
2408 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2409 __FILE__,__LINE__, info->device_name, ch );
2410
2411 if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2412 return;
2413
2414 info->x_char = ch;
2415 if (ch) {
2416 /* Make sure transmit interrupts are on */
2417 spin_lock_irqsave(&info->irq_spinlock,flags);
2418 if (!info->tx_enabled)
2419 usc_start_transmitter(info);
2420 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2421 }
2422 } /* end of mgsl_send_xchar() */
2423
2424 /* mgsl_throttle()
2425 *
2426 * Signal remote device to throttle send data (our receive data)
2427 *
2428 * Arguments: tty pointer to tty info structure
2429 * Return Value: None
2430 */
2431 static void mgsl_throttle(struct tty_struct * tty)
2432 {
2433 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2434 unsigned long flags;
2435
2436 if (debug_level >= DEBUG_LEVEL_INFO)
2437 printk("%s(%d):mgsl_throttle(%s) entry\n",
2438 __FILE__,__LINE__, info->device_name );
2439
2440 if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2441 return;
2442
2443 if (I_IXOFF(tty))
2444 mgsl_send_xchar(tty, STOP_CHAR(tty));
2445
2446 if (tty->termios->c_cflag & CRTSCTS) {
2447 spin_lock_irqsave(&info->irq_spinlock,flags);
2448 info->serial_signals &= ~SerialSignal_RTS;
2449 usc_set_serial_signals(info);
2450 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2451 }
2452 } /* end of mgsl_throttle() */
2453
2454 /* mgsl_unthrottle()
2455 *
2456 * Signal remote device to stop throttling send data (our receive data)
2457 *
2458 * Arguments: tty pointer to tty info structure
2459 * Return Value: None
2460 */
2461 static void mgsl_unthrottle(struct tty_struct * tty)
2462 {
2463 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2464 unsigned long flags;
2465
2466 if (debug_level >= DEBUG_LEVEL_INFO)
2467 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2468 __FILE__,__LINE__, info->device_name );
2469
2470 if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2471 return;
2472
2473 if (I_IXOFF(tty)) {
2474 if (info->x_char)
2475 info->x_char = 0;
2476 else
2477 mgsl_send_xchar(tty, START_CHAR(tty));
2478 }
2479
2480 if (tty->termios->c_cflag & CRTSCTS) {
2481 spin_lock_irqsave(&info->irq_spinlock,flags);
2482 info->serial_signals |= SerialSignal_RTS;
2483 usc_set_serial_signals(info);
2484 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2485 }
2486
2487 } /* end of mgsl_unthrottle() */
2488
2489 /* mgsl_get_stats()
2490 *
2491 * get the current serial parameters information
2492 *
2493 * Arguments: info pointer to device instance data
2494 * user_icount pointer to buffer to hold returned stats
2495 *
2496 * Return Value: 0 if success, otherwise error code
2497 */
2498 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount *user_icount)
2499 {
2500 int err;
2501
2502 if (debug_level >= DEBUG_LEVEL_INFO)
2503 printk("%s(%d):mgsl_get_params(%s)\n",
2504 __FILE__,__LINE__, info->device_name);
2505
2506 COPY_TO_USER(err,user_icount, &info->icount, sizeof(struct mgsl_icount));
2507 if (err) {
2508 if ( debug_level >= DEBUG_LEVEL_INFO )
2509 printk( "%s(%d):mgsl_get_stats(%s) user buffer copy failed\n",
2510 __FILE__,__LINE__,info->device_name);
2511 return -EFAULT;
2512 }
2513
2514 return 0;
2515
2516 } /* end of mgsl_get_stats() */
2517
2518 /* mgsl_get_params()
2519 *
2520 * get the current serial parameters information
2521 *
2522 * Arguments: info pointer to device instance data
2523 * user_params pointer to buffer to hold returned params
2524 *
2525 * Return Value: 0 if success, otherwise error code
2526 */
2527 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS *user_params)
2528 {
2529 int err;
2530 if (debug_level >= DEBUG_LEVEL_INFO)
2531 printk("%s(%d):mgsl_get_params(%s)\n",
2532 __FILE__,__LINE__, info->device_name);
2533
2534 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2535 if (err) {
2536 if ( debug_level >= DEBUG_LEVEL_INFO )
2537 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2538 __FILE__,__LINE__,info->device_name);
2539 return -EFAULT;
2540 }
2541
2542 return 0;
2543
2544 } /* end of mgsl_get_params() */
2545
2546 /* mgsl_set_params()
2547 *
2548 * set the serial parameters
2549 *
2550 * Arguments:
2551 *
2552 * info pointer to device instance data
2553 * new_params user buffer containing new serial params
2554 *
2555 * Return Value: 0 if success, otherwise error code
2556 */
2557 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS *new_params)
2558 {
2559 unsigned long flags;
2560 MGSL_PARAMS tmp_params;
2561 int err;
2562
2563 if (debug_level >= DEBUG_LEVEL_INFO)
2564 printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2565 info->device_name );
2566 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2567 if (err) {
2568 if ( debug_level >= DEBUG_LEVEL_INFO )
2569 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2570 __FILE__,__LINE__,info->device_name);
2571 return -EFAULT;
2572 }
2573
2574 spin_lock_irqsave(&info->irq_spinlock,flags);
2575 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2576 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2577
2578 mgsl_change_params(info);
2579
2580 return 0;
2581
2582 } /* end of mgsl_set_params() */
2583
2584 /* mgsl_get_txidle()
2585 *
2586 * get the current transmit idle mode
2587 *
2588 * Arguments: info pointer to device instance data
2589 * idle_mode pointer to buffer to hold returned idle mode
2590 *
2591 * Return Value: 0 if success, otherwise error code
2592 */
2593 static int mgsl_get_txidle(struct mgsl_struct * info, int*idle_mode)
2594 {
2595 int err;
2596
2597 if (debug_level >= DEBUG_LEVEL_INFO)
2598 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2599 __FILE__,__LINE__, info->device_name, info->idle_mode);
2600
2601 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2602 if (err) {
2603 if ( debug_level >= DEBUG_LEVEL_INFO )
2604 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2605 __FILE__,__LINE__,info->device_name);
2606 return -EFAULT;
2607 }
2608
2609 return 0;
2610
2611 } /* end of mgsl_get_txidle() */
2612
2613 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2614 *
2615 * Arguments: info pointer to device instance data
2616 * idle_mode new idle mode
2617 *
2618 * Return Value: 0 if success, otherwise error code
2619 */
2620 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2621 {
2622 unsigned long flags;
2623
2624 if (debug_level >= DEBUG_LEVEL_INFO)
2625 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2626 info->device_name, idle_mode );
2627
2628 spin_lock_irqsave(&info->irq_spinlock,flags);
2629 info->idle_mode = idle_mode;
2630 usc_set_txidle( info );
2631 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2632 return 0;
2633
2634 } /* end of mgsl_set_txidle() */
2635
2636 /* mgsl_txenable()
2637 *
2638 * enable or disable the transmitter
2639 *
2640 * Arguments:
2641 *
2642 * info pointer to device instance data
2643 * enable 1 = enable, 0 = disable
2644 *
2645 * Return Value: 0 if success, otherwise error code
2646 */
2647 static int mgsl_txenable(struct mgsl_struct * info, int enable)
2648 {
2649 unsigned long flags;
2650
2651 if (debug_level >= DEBUG_LEVEL_INFO)
2652 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2653 info->device_name, enable);
2654
2655 spin_lock_irqsave(&info->irq_spinlock,flags);
2656 if ( enable ) {
2657 if ( !info->tx_enabled ) {
2658
2659 usc_start_transmitter(info);
2660 /*--------------------------------------------------
2661 * if HDLC/SDLC Loop mode, attempt to insert the
2662 * station in the 'loop' by setting CMR:13. Upon
2663 * receipt of the next GoAhead (RxAbort) sequence,
2664 * the OnLoop indicator (CCSR:7) should go active
2665 * to indicate that we are on the loop
2666 *--------------------------------------------------*/
2667 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2668 usc_loopmode_insert_request( info );
2669 }
2670 } else {
2671 if ( info->tx_enabled )
2672 usc_stop_transmitter(info);
2673 }
2674 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2675 return 0;
2676
2677 } /* end of mgsl_txenable() */
2678
2679 /* mgsl_txabort() abort send HDLC frame
2680 *
2681 * Arguments: info pointer to device instance data
2682 * Return Value: 0 if success, otherwise error code
2683 */
2684 static int mgsl_txabort(struct mgsl_struct * info)
2685 {
2686 unsigned long flags;
2687
2688 if (debug_level >= DEBUG_LEVEL_INFO)
2689 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2690 info->device_name);
2691
2692 spin_lock_irqsave(&info->irq_spinlock,flags);
2693 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2694 {
2695 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2696 usc_loopmode_cancel_transmit( info );
2697 else
2698 usc_TCmd(info,TCmd_SendAbort);
2699 }
2700 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2701 return 0;
2702
2703 } /* end of mgsl_txabort() */
2704
2705 /* mgsl_rxenable() enable or disable the receiver
2706 *
2707 * Arguments: info pointer to device instance data
2708 * enable 1 = enable, 0 = disable
2709 * Return Value: 0 if success, otherwise error code
2710 */
2711 static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2712 {
2713 unsigned long flags;
2714
2715 if (debug_level >= DEBUG_LEVEL_INFO)
2716 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2717 info->device_name, enable);
2718
2719 spin_lock_irqsave(&info->irq_spinlock,flags);
2720 if ( enable ) {
2721 if ( !info->rx_enabled )
2722 usc_start_receiver(info);
2723 } else {
2724 if ( info->rx_enabled )
2725 usc_stop_receiver(info);
2726 }
2727 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2728 return 0;
2729
2730 } /* end of mgsl_rxenable() */
2731
2732 /* mgsl_wait_event() wait for specified event to occur
2733 *
2734 * Arguments: info pointer to device instance data
2735 * mask pointer to bitmask of events to wait for
2736 * Return Value: 0 if successful and bit mask updated with
2737 * of events triggerred,
2738 * otherwise error code
2739 */
2740 static int mgsl_wait_event(struct mgsl_struct * info, int * mask_ptr)
2741 {
2742 unsigned long flags;
2743 int s;
2744 int rc=0;
2745 struct mgsl_icount cprev, cnow;
2746 int events;
2747 int mask;
2748 struct _input_signal_events oldsigs, newsigs;
2749 DECLARE_WAITQUEUE(wait, current);
2750
2751 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2752 if (rc) {
2753 return -EFAULT;
2754 }
2755
2756 if (debug_level >= DEBUG_LEVEL_INFO)
2757 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2758 info->device_name, mask);
2759
2760 spin_lock_irqsave(&info->irq_spinlock,flags);
2761
2762 /* return immediately if state matches requested events */
2763 usc_get_serial_signals(info);
2764 s = info->serial_signals;
2765 events = mask &
2766 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2767 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2768 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2769 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2770 if (events) {
2771 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2772 goto exit;
2773 }
2774
2775 /* save current irq counts */
2776 cprev = info->icount;
2777 oldsigs = info->input_signal_events;
2778
2779 /* enable hunt and idle irqs if needed */
2780 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2781 u16 oldreg = usc_InReg(info,RICR);
2782 u16 newreg = oldreg +
2783 (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2784 (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2785 if (oldreg != newreg)
2786 usc_OutReg(info, RICR, newreg);
2787 }
2788
2789 set_current_state(TASK_INTERRUPTIBLE);
2790 add_wait_queue(&info->event_wait_q, &wait);
2791
2792 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2793
2794
2795 for(;;) {
2796 schedule();
2797 if (signal_pending(current)) {
2798 rc = -ERESTARTSYS;
2799 break;
2800 }
2801
2802 /* get current irq counts */
2803 spin_lock_irqsave(&info->irq_spinlock,flags);
2804 cnow = info->icount;
2805 newsigs = info->input_signal_events;
2806 set_current_state(TASK_INTERRUPTIBLE);
2807 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2808
2809 /* if no change, wait aborted for some reason */
2810 if (newsigs.dsr_up == oldsigs.dsr_up &&
2811 newsigs.dsr_down == oldsigs.dsr_down &&
2812 newsigs.dcd_up == oldsigs.dcd_up &&
2813 newsigs.dcd_down == oldsigs.dcd_down &&
2814 newsigs.cts_up == oldsigs.cts_up &&
2815 newsigs.cts_down == oldsigs.cts_down &&
2816 newsigs.ri_up == oldsigs.ri_up &&
2817 newsigs.ri_down == oldsigs.ri_down &&
2818 cnow.exithunt == cprev.exithunt &&
2819 cnow.rxidle == cprev.rxidle) {
2820 rc = -EIO;
2821 break;
2822 }
2823
2824 events = mask &
2825 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2826 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2827 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2828 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2829 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2830 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2831 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2832 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2833 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2834 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2835 if (events)
2836 break;
2837
2838 cprev = cnow;
2839 oldsigs = newsigs;
2840 }
2841
2842 remove_wait_queue(&info->event_wait_q, &wait);
2843 set_current_state(TASK_RUNNING);
2844
2845 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2846 spin_lock_irqsave(&info->irq_spinlock,flags);
2847 if (!waitqueue_active(&info->event_wait_q)) {
2848 /* disable enable exit hunt mode/idle rcvd IRQs */
2849 usc_OutReg(info, RICR, usc_InReg(info,RICR) &
2850 ~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED));
2851 }
2852 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2853 }
2854 exit:
2855 if ( rc == 0 )
2856 PUT_USER(rc, events, mask_ptr);
2857
2858 return rc;
2859
2860 } /* end of mgsl_wait_event() */
2861
2862 static int modem_input_wait(struct mgsl_struct *info,int arg)
2863 {
2864 unsigned long flags;
2865 int rc;
2866 struct mgsl_icount cprev, cnow;
2867 DECLARE_WAITQUEUE(wait, current);
2868
2869 /* save current irq counts */
2870 spin_lock_irqsave(&info->irq_spinlock,flags);
2871 cprev = info->icount;
2872 add_wait_queue(&info->status_event_wait_q, &wait);
2873 set_current_state(TASK_INTERRUPTIBLE);
2874 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2875
2876 for(;;) {
2877 schedule();
2878 if (signal_pending(current)) {
2879 rc = -ERESTARTSYS;
2880 break;
2881 }
2882
2883 /* get new irq counts */
2884 spin_lock_irqsave(&info->irq_spinlock,flags);
2885 cnow = info->icount;
2886 set_current_state(TASK_INTERRUPTIBLE);
2887 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2888
2889 /* if no change, wait aborted for some reason */
2890 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2891 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2892 rc = -EIO;
2893 break;
2894 }
2895
2896 /* check for change in caller specified modem input */
2897 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2898 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2899 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2900 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2901 rc = 0;
2902 break;
2903 }
2904
2905 cprev = cnow;
2906 }
2907 remove_wait_queue(&info->status_event_wait_q, &wait);
2908 set_current_state(TASK_RUNNING);
2909 return rc;
2910 }
2911
2912 /* return the state of the serial control and status signals
2913 */
2914 static int tiocmget(struct tty_struct *tty, struct file *file)
2915 {
2916 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2917 unsigned int result;
2918 unsigned long flags;
2919
2920 spin_lock_irqsave(&info->irq_spinlock,flags);
2921 usc_get_serial_signals(info);
2922 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2923
2924 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2925 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2926 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2927 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2928 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2929 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2930
2931 if (debug_level >= DEBUG_LEVEL_INFO)
2932 printk("%s(%d):%s tiocmget() value=%08X\n",
2933 __FILE__,__LINE__, info->device_name, result );
2934 return result;
2935 }
2936
2937 /* set modem control signals (DTR/RTS)
2938 */
2939 static int tiocmset(struct tty_struct *tty, struct file *file,
2940 unsigned int set, unsigned int clear)
2941 {
2942 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2943 unsigned long flags;
2944
2945 if (debug_level >= DEBUG_LEVEL_INFO)
2946 printk("%s(%d):%s tiocmset(%x,%x)\n",
2947 __FILE__,__LINE__,info->device_name, set, clear);
2948
2949 if (set & TIOCM_RTS)
2950 info->serial_signals |= SerialSignal_RTS;
2951 if (set & TIOCM_DTR)
2952 info->serial_signals |= SerialSignal_DTR;
2953 if (clear & TIOCM_RTS)
2954 info->serial_signals &= ~SerialSignal_RTS;
2955 if (clear & TIOCM_DTR)
2956 info->serial_signals &= ~SerialSignal_DTR;
2957
2958 spin_lock_irqsave(&info->irq_spinlock,flags);
2959 usc_set_serial_signals(info);
2960 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2961
2962 return 0;
2963 }
2964
2965 /* mgsl_break() Set or clear transmit break condition
2966 *
2967 * Arguments: tty pointer to tty instance data
2968 * break_state -1=set break condition, 0=clear
2969 * Return Value: None
2970 */
2971 static void mgsl_break(struct tty_struct *tty, int break_state)
2972 {
2973 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
2974 unsigned long flags;
2975
2976 if (debug_level >= DEBUG_LEVEL_INFO)
2977 printk("%s(%d):mgsl_break(%s,%d)\n",
2978 __FILE__,__LINE__, info->device_name, break_state);
2979
2980 if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
2981 return;
2982
2983 spin_lock_irqsave(&info->irq_spinlock,flags);
2984 if (break_state == -1)
2985 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2986 else
2987 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2988 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2989
2990 } /* end of mgsl_break() */
2991
2992 /* mgsl_ioctl() Service an IOCTL request
2993 *
2994 * Arguments:
2995 *
2996 * tty pointer to tty instance data
2997 * file pointer to associated file object for device
2998 * cmd IOCTL command code
2999 * arg command argument/context
3000 *
3001 * Return Value: 0 if success, otherwise error code
3002 */
3003 static int mgsl_ioctl(struct tty_struct *tty, struct file * file,
3004 unsigned int cmd, unsigned long arg)
3005 {
3006 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3007
3008 if (debug_level >= DEBUG_LEVEL_INFO)
3009 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
3010 info->device_name, cmd );
3011
3012 if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
3013 return -ENODEV;
3014
3015 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
3016 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
3017 if (tty->flags & (1 << TTY_IO_ERROR))
3018 return -EIO;
3019 }
3020
3021 return mgsl_ioctl_common(info, cmd, arg);
3022 }
3023
3024 int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
3025 {
3026 int error;
3027 struct mgsl_icount cnow; /* kernel counter temps */
3028 struct serial_icounter_struct *p_cuser; /* user space */
3029 unsigned long flags;
3030
3031 switch (cmd) {
3032 case MGSL_IOCGPARAMS:
3033 return mgsl_get_params(info,(MGSL_PARAMS *)arg);
3034 case MGSL_IOCSPARAMS:
3035 return mgsl_set_params(info,(MGSL_PARAMS *)arg);
3036 case MGSL_IOCGTXIDLE:
3037 return mgsl_get_txidle(info,(int*)arg);
3038 case MGSL_IOCSTXIDLE:
3039 return mgsl_set_txidle(info,(int)arg);
3040 case MGSL_IOCTXENABLE:
3041 return mgsl_txenable(info,(int)arg);
3042 case MGSL_IOCRXENABLE:
3043 return mgsl_rxenable(info,(int)arg);
3044 case MGSL_IOCTXABORT:
3045 return mgsl_txabort(info);
3046 case MGSL_IOCGSTATS:
3047 return mgsl_get_stats(info,(struct mgsl_icount*)arg);
3048 case MGSL_IOCWAITEVENT:
3049 return mgsl_wait_event(info,(int*)arg);
3050 case MGSL_IOCLOOPTXDONE:
3051 return mgsl_loopmode_send_done(info);
3052 /* Wait for modem input (DCD,RI,DSR,CTS) change
3053 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
3054 */
3055 case TIOCMIWAIT:
3056 return modem_input_wait(info,(int)arg);
3057
3058 /*
3059 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
3060 * Return: write counters to the user passed counter struct
3061 * NB: both 1->0 and 0->1 transitions are counted except for
3062 * RI where only 0->1 is counted.
3063 */
3064 case TIOCGICOUNT:
3065 spin_lock_irqsave(&info->irq_spinlock,flags);
3066 cnow = info->icount;
3067 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3068 p_cuser = (struct serial_icounter_struct *) arg;
3069 PUT_USER(error,cnow.cts, &p_cuser->cts);
3070 if (error) return error;
3071 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
3072 if (error) return error;
3073 PUT_USER(error,cnow.rng, &p_cuser->rng);
3074 if (error) return error;
3075 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
3076 if (error) return error;
3077 PUT_USER(error,cnow.rx, &p_cuser->rx);
3078 if (error) return error;
3079 PUT_USER(error,cnow.tx, &p_cuser->tx);
3080 if (error) return error;
3081 PUT_USER(error,cnow.frame, &p_cuser->frame);
3082 if (error) return error;
3083 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
3084 if (error) return error;
3085 PUT_USER(error,cnow.parity, &p_cuser->parity);
3086 if (error) return error;
3087 PUT_USER(error,cnow.brk, &p_cuser->brk);
3088 if (error) return error;
3089 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
3090 if (error) return error;
3091 return 0;
3092 default:
3093 return -ENOIOCTLCMD;
3094 }
3095 return 0;
3096 }
3097
3098 /* mgsl_set_termios()
3099 *
3100 * Set new termios settings
3101 *
3102 * Arguments:
3103 *
3104 * tty pointer to tty structure
3105 * termios pointer to buffer to hold returned old termios
3106 *
3107 * Return Value: None
3108 */
3109 static void mgsl_set_termios(struct tty_struct *tty, struct termios *old_termios)
3110 {
3111 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
3112 unsigned long flags;
3113
3114 if (debug_level >= DEBUG_LEVEL_INFO)
3115 printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3116 tty->driver->name );
3117
3118 /* just return if nothing has changed */
3119 if ((tty->termios->c_cflag == old_termios->c_cflag)
3120 && (RELEVANT_IFLAG(tty->termios->c_iflag)
3121 == RELEVANT_IFLAG(old_termios->c_iflag)))
3122 return;
3123
3124 mgsl_change_params(info);
3125
3126 /* Handle transition to B0 status */
3127 if (old_termios->c_cflag & CBAUD &&
3128 !(tty->termios->c_cflag & CBAUD)) {
3129 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3130 spin_lock_irqsave(&info->irq_spinlock,flags);
3131 usc_set_serial_signals(info);
3132 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3133 }
3134
3135 /* Handle transition away from B0 status */
3136 if (!(old_termios->c_cflag & CBAUD) &&
3137 tty->termios->c_cflag & CBAUD) {
3138 info->serial_signals |= SerialSignal_DTR;
3139 if (!(tty->termios->c_cflag & CRTSCTS) ||
3140 !test_bit(TTY_THROTTLED, &tty->flags)) {
3141 info->serial_signals |= SerialSignal_RTS;
3142 }
3143 spin_lock_irqsave(&info->irq_spinlock,flags);
3144 usc_set_serial_signals(info);
3145 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3146 }
3147
3148 /* Handle turning off CRTSCTS */
3149 if (old_termios->c_cflag & CRTSCTS &&
3150 !(tty->termios->c_cflag & CRTSCTS)) {
3151 tty->hw_stopped = 0;
3152 mgsl_start(tty);
3153 }
3154
3155 } /* end of mgsl_set_termios() */
3156
3157 /* mgsl_close()
3158 *
3159 * Called when port is closed. Wait for remaining data to be
3160 * sent. Disable port and free resources.
3161 *
3162 * Arguments:
3163 *
3164 * tty pointer to open tty structure
3165 * filp pointer to open file object
3166 *
3167 * Return Value: None
3168 */
3169 static void mgsl_close(struct tty_struct *tty, struct file * filp)
3170 {
3171 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3172
3173 if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3174 return;
3175
3176 if (debug_level >= DEBUG_LEVEL_INFO)
3177 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3178 __FILE__,__LINE__, info->device_name, info->count);
3179
3180 if (!info->count)
3181 return;
3182
3183 if (tty_hung_up_p(filp))
3184 goto cleanup;
3185
3186 if ((tty->count == 1) && (info->count != 1)) {
3187 /*
3188 * tty->count is 1 and the tty structure will be freed.
3189 * info->count should be one in this case.
3190 * if it's not, correct it so that the port is shutdown.
3191 */
3192 printk("mgsl_close: bad refcount; tty->count is 1, "
3193 "info->count is %d\n", info->count);
3194 info->count = 1;
3195 }
3196
3197 info->count--;
3198
3199 /* if at least one open remaining, leave hardware active */
3200 if (info->count)
3201 goto cleanup;
3202
3203 info->flags |= ASYNC_CLOSING;
3204
3205 /* set tty->closing to notify line discipline to
3206 * only process XON/XOFF characters. Only the N_TTY
3207 * discipline appears to use this (ppp does not).
3208 */
3209 tty->closing = 1;
3210
3211 /* wait for transmit data to clear all layers */
3212
3213 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
3214 if (debug_level >= DEBUG_LEVEL_INFO)
3215 printk("%s(%d):mgsl_close(%s) calling tty_wait_until_sent\n",
3216 __FILE__,__LINE__, info->device_name );
3217 tty_wait_until_sent(tty, info->closing_wait);
3218 }
3219
3220 if (info->flags & ASYNC_INITIALIZED)
3221 mgsl_wait_until_sent(tty, info->timeout);
3222
3223 if (tty->driver->flush_buffer)
3224 tty->driver->flush_buffer(tty);
3225
3226 if (tty->ldisc.flush_buffer)
3227 tty->ldisc.flush_buffer(tty);
3228
3229 shutdown(info);
3230
3231 tty->closing = 0;
3232 info->tty = 0;
3233
3234 if (info->blocked_open) {
3235 if (info->close_delay) {
3236 set_current_state(TASK_INTERRUPTIBLE);
3237 schedule_timeout(info->close_delay);
3238 }
3239 wake_up_interruptible(&info->open_wait);
3240 }
3241
3242 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
3243
3244 wake_up_interruptible(&info->close_wait);
3245
3246 cleanup:
3247 if (debug_level >= DEBUG_LEVEL_INFO)
3248 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
3249 tty->driver->name, info->count);
3250
3251 } /* end of mgsl_close() */
3252
3253 /* mgsl_wait_until_sent()
3254 *
3255 * Wait until the transmitter is empty.
3256 *
3257 * Arguments:
3258 *
3259 * tty pointer to tty info structure
3260 * timeout time to wait for send completion
3261 *
3262 * Return Value: None
3263 */
3264 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3265 {
3266 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3267 unsigned long orig_jiffies, char_time;
3268
3269 if (!info )
3270 return;
3271
3272 if (debug_level >= DEBUG_LEVEL_INFO)
3273 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3274 __FILE__,__LINE__, info->device_name );
3275
3276 if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3277 return;
3278
3279 if (!(info->flags & ASYNC_INITIALIZED))
3280 goto exit;
3281
3282 orig_jiffies = jiffies;
3283
3284 /* Set check interval to 1/5 of estimated time to
3285 * send a character, and make it at least 1. The check
3286 * interval should also be less than the timeout.
3287 * Note: use tight timings here to satisfy the NIST-PCTS.
3288 */
3289
3290 if ( info->params.data_rate ) {
3291 char_time = info->timeout/(32 * 5);
3292 if (!char_time)
3293 char_time++;
3294 } else
3295 char_time = 1;
3296
3297 if (timeout)
3298 char_time = MIN(char_time, timeout);
3299
3300 if ( info->params.mode == MGSL_MODE_HDLC ||
3301 info->params.mode == MGSL_MODE_RAW ) {
3302 while (info->tx_active) {
3303 set_current_state(TASK_INTERRUPTIBLE);
3304 schedule_timeout(char_time);
3305 if (signal_pending(current))
3306 break;
3307 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3308 break;
3309 }
3310 } else {
3311 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3312 info->tx_enabled) {
3313 set_current_state(TASK_INTERRUPTIBLE);
3314 schedule_timeout(char_time);
3315 if (signal_pending(current))
3316 break;
3317 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3318 break;
3319 }
3320 }
3321
3322 exit:
3323 if (debug_level >= DEBUG_LEVEL_INFO)
3324 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3325 __FILE__,__LINE__, info->device_name );
3326
3327 } /* end of mgsl_wait_until_sent() */
3328
3329 /* mgsl_hangup()
3330 *
3331 * Called by tty_hangup() when a hangup is signaled.
3332 * This is the same as to closing all open files for the port.
3333 *
3334 * Arguments: tty pointer to associated tty object
3335 * Return Value: None
3336 */
3337 static void mgsl_hangup(struct tty_struct *tty)
3338 {
3339 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3340
3341 if (debug_level >= DEBUG_LEVEL_INFO)
3342 printk("%s(%d):mgsl_hangup(%s)\n",
3343 __FILE__,__LINE__, info->device_name );
3344
3345 if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3346 return;
3347
3348 mgsl_flush_buffer(tty);
3349 shutdown(info);
3350
3351 info->count = 0;
3352 info->flags &= ~ASYNC_NORMAL_ACTIVE;
3353 info->tty = 0;
3354
3355 wake_up_interruptible(&info->open_wait);
3356
3357 } /* end of mgsl_hangup() */
3358
3359 /* block_til_ready()
3360 *
3361 * Block the current process until the specified port
3362 * is ready to be opened.
3363 *
3364 * Arguments:
3365 *
3366 * tty pointer to tty info structure
3367 * filp pointer to open file object
3368 * info pointer to device instance data
3369 *
3370 * Return Value: 0 if success, otherwise error code
3371 */
3372 static int block_til_ready(struct tty_struct *tty, struct file * filp,
3373 struct mgsl_struct *info)
3374 {
3375 DECLARE_WAITQUEUE(wait, current);
3376 int retval;
3377 int do_clocal = 0, extra_count = 0;
3378 unsigned long flags;
3379
3380 if (debug_level >= DEBUG_LEVEL_INFO)
3381 printk("%s(%d):block_til_ready on %s\n",
3382 __FILE__,__LINE__, tty->driver->name );
3383
3384 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3385 /* nonblock mode is set or port is not enabled */
3386 info->flags |= ASYNC_NORMAL_ACTIVE;
3387 return 0;
3388 }
3389
3390 if (tty->termios->c_cflag & CLOCAL)
3391 do_clocal = 1;
3392
3393 /* Wait for carrier detect and the line to become
3394 * free (i.e., not in use by the callout). While we are in
3395 * this loop, info->count is dropped by one, so that
3396 * mgsl_close() knows when to free things. We restore it upon
3397 * exit, either normal or abnormal.
3398 */
3399
3400 retval = 0;
3401 add_wait_queue(&info->open_wait, &wait);
3402
3403 if (debug_level >= DEBUG_LEVEL_INFO)
3404 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3405 __FILE__,__LINE__, tty->driver->name, info->count );
3406
3407 spin_lock_irqsave(&info->irq_spinlock, flags);
3408 if (!tty_hung_up_p(filp)) {
3409 extra_count = 1;
3410 info->count--;
3411 }
3412 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3413 info->blocked_open++;
3414
3415 while (1) {
3416 if (tty->termios->c_cflag & CBAUD) {
3417 spin_lock_irqsave(&info->irq_spinlock,flags);
3418 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3419 usc_set_serial_signals(info);
3420 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3421 }
3422
3423 set_current_state(TASK_INTERRUPTIBLE);
3424
3425 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3426 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3427 -EAGAIN : -ERESTARTSYS;
3428 break;
3429 }
3430
3431 spin_lock_irqsave(&info->irq_spinlock,flags);
3432 usc_get_serial_signals(info);
3433 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3434
3435 if (!(info->flags & ASYNC_CLOSING) &&
3436 (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3437 break;
3438 }
3439
3440 if (signal_pending(current)) {
3441 retval = -ERESTARTSYS;
3442 break;
3443 }
3444
3445 if (debug_level >= DEBUG_LEVEL_INFO)
3446 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3447 __FILE__,__LINE__, tty->driver->name, info->count );
3448
3449 schedule();
3450 }
3451
3452 set_current_state(TASK_RUNNING);
3453 remove_wait_queue(&info->open_wait, &wait);
3454
3455 if (extra_count)
3456 info->count++;
3457 info->blocked_open--;
3458
3459 if (debug_level >= DEBUG_LEVEL_INFO)
3460 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3461 __FILE__,__LINE__, tty->driver->name, info->count );
3462
3463 if (!retval)
3464 info->flags |= ASYNC_NORMAL_ACTIVE;
3465
3466 return retval;
3467
3468 } /* end of block_til_ready() */
3469
3470 /* mgsl_open()
3471 *
3472 * Called when a port is opened. Init and enable port.
3473 * Perform serial-specific initialization for the tty structure.
3474 *
3475 * Arguments: tty pointer to tty info structure
3476 * filp associated file pointer
3477 *
3478 * Return Value: 0 if success, otherwise error code
3479 */
3480 static int mgsl_open(struct tty_struct *tty, struct file * filp)
3481 {
3482 struct mgsl_struct *info;
3483 int retval, line;
3484 unsigned long page;
3485 unsigned long flags;
3486
3487 /* verify range of specified line number */
3488 line = tty->index;
3489 if ((line < 0) || (line >= mgsl_device_count)) {
3490 printk("%s(%d):mgsl_open with illegal line #%d.\n",
3491 __FILE__,__LINE__,line);
3492 return -ENODEV;
3493 }
3494
3495 /* find the info structure for the specified line */
3496 info = mgsl_device_list;
3497 while(info && info->line != line)
3498 info = info->next_device;
3499 if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3500 return -ENODEV;
3501
3502 tty->driver_data = info;
3503 info->tty = tty;
3504
3505 if (debug_level >= DEBUG_LEVEL_INFO)
3506 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3507 __FILE__,__LINE__,tty->driver->name, info->count);
3508
3509 /* If port is closing, signal caller to try again */
3510 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
3511 if (info->flags & ASYNC_CLOSING)
3512 interruptible_sleep_on(&info->close_wait);
3513 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
3514 -EAGAIN : -ERESTARTSYS);
3515 goto cleanup;
3516 }
3517
3518 if (!tmp_buf) {
3519 page = get_zeroed_page(GFP_KERNEL);
3520 if (!page) {
3521 retval = -ENOMEM;
3522 goto cleanup;
3523 }
3524 if (tmp_buf)
3525 free_page(page);
3526 else
3527 tmp_buf = (unsigned char *) page;
3528 }
3529
3530 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3531
3532 spin_lock_irqsave(&info->netlock, flags);
3533 if (info->netcount) {
3534 retval = -EBUSY;
3535 spin_unlock_irqrestore(&info->netlock, flags);
3536 goto cleanup;
3537 }
3538 info->count++;
3539 spin_unlock_irqrestore(&info->netlock, flags);
3540
3541 if (info->count == 1) {
3542 /* 1st open on this device, init hardware */
3543 retval = startup(info);
3544 if (retval < 0)
3545 goto cleanup;
3546 }
3547
3548 retval = block_til_ready(tty, filp, info);
3549 if (retval) {
3550 if (debug_level >= DEBUG_LEVEL_INFO)
3551 printk("%s(%d):block_til_ready(%s) returned %d\n",
3552 __FILE__,__LINE__, info->device_name, retval);
3553 goto cleanup;
3554 }
3555
3556 if (debug_level >= DEBUG_LEVEL_INFO)
3557 printk("%s(%d):mgsl_open(%s) success\n",
3558 __FILE__,__LINE__, info->device_name);
3559 retval = 0;
3560
3561 cleanup:
3562 if (retval) {
3563 if (tty->count == 1)
3564 info->tty = 0; /* tty layer will release tty struct */
3565 if(info->count)
3566 info->count--;
3567 }
3568
3569 return retval;
3570
3571 } /* end of mgsl_open() */
3572
3573 /*
3574 * /proc fs routines....
3575 */
3576
3577 static inline int line_info(char *buf, struct mgsl_struct *info)
3578 {
3579 char stat_buf[30];
3580 int ret;
3581 unsigned long flags;
3582
3583 if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3584 ret = sprintf(buf, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3585 info->device_name, info->io_base, info->irq_level,
3586 info->phys_memory_base, info->phys_lcr_base);
3587 } else {
3588 ret = sprintf(buf, "%s:(E)ISA io:%04X irq:%d dma:%d",
3589 info->device_name, info->io_base,
3590 info->irq_level, info->dma_level);
3591 }
3592
3593 /* output current serial signal states */
3594 spin_lock_irqsave(&info->irq_spinlock,flags);
3595 usc_get_serial_signals(info);
3596 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3597
3598 stat_buf[0] = 0;
3599 stat_buf[1] = 0;
3600 if (info->serial_signals & SerialSignal_RTS)
3601 strcat(stat_buf, "|RTS");
3602 if (info->serial_signals & SerialSignal_CTS)
3603 strcat(stat_buf, "|CTS");
3604 if (info->serial_signals & SerialSignal_DTR)
3605 strcat(stat_buf, "|DTR");
3606 if (info->serial_signals & SerialSignal_DSR)
3607 strcat(stat_buf, "|DSR");
3608 if (info->serial_signals & SerialSignal_DCD)
3609 strcat(stat_buf, "|CD");
3610 if (info->serial_signals & SerialSignal_RI)
3611 strcat(stat_buf, "|RI");
3612
3613 if (info->params.mode == MGSL_MODE_HDLC ||
3614 info->params.mode == MGSL_MODE_RAW ) {
3615 ret += sprintf(buf+ret, " HDLC txok:%d rxok:%d",
3616 info->icount.txok, info->icount.rxok);
3617 if (info->icount.txunder)
3618 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
3619 if (info->icount.txabort)
3620 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
3621 if (info->icount.rxshort)
3622 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
3623 if (info->icount.rxlong)
3624 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
3625 if (info->icount.rxover)
3626 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
3627 if (info->icount.rxcrc)
3628 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
3629 } else {
3630 ret += sprintf(buf+ret, " ASYNC tx:%d rx:%d",
3631 info->icount.tx, info->icount.rx);
3632 if (info->icount.frame)
3633 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
3634 if (info->icount.parity)
3635 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
3636 if (info->icount.brk)
3637 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
3638 if (info->icount.overrun)
3639 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
3640 }
3641
3642 /* Append serial signal status to end */
3643 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
3644
3645 ret += sprintf(buf+ret, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3646 info->tx_active,info->bh_requested,info->bh_running,
3647 info->pending_bh);
3648
3649 spin_lock_irqsave(&info->irq_spinlock,flags);
3650 {
3651 u16 Tcsr = usc_InReg( info, TCSR );
3652 u16 Tdmr = usc_InDmaReg( info, TDMR );
3653 u16 Ticr = usc_InReg( info, TICR );
3654 u16 Rscr = usc_InReg( info, RCSR );
3655 u16 Rdmr = usc_InDmaReg( info, RDMR );
3656 u16 Ricr = usc_InReg( info, RICR );
3657 u16 Icr = usc_InReg( info, ICR );
3658 u16 Dccr = usc_InReg( info, DCCR );
3659 u16 Tmr = usc_InReg( info, TMR );
3660 u16 Tccr = usc_InReg( info, TCCR );
3661 u16 Ccar = inw( info->io_base + CCAR );
3662 ret += sprintf(buf+ret, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3663 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3664 Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3665 }
3666 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3667
3668 return ret;
3669
3670 } /* end of line_info() */
3671
3672 /* mgsl_read_proc()
3673 *
3674 * Called to print information about devices
3675 *
3676 * Arguments:
3677 * page page of memory to hold returned info
3678 * start
3679 * off
3680 * count
3681 * eof
3682 * data
3683 *
3684 * Return Value:
3685 */
3686 int mgsl_read_proc(char *page, char **start, off_t off, int count,
3687 int *eof, void *data)
3688 {
3689 int len = 0, l;
3690 off_t begin = 0;
3691 struct mgsl_struct *info;
3692
3693 len += sprintf(page, "synclink driver:%s\n", driver_version);
3694
3695 info = mgsl_device_list;
3696 while( info ) {
3697 l = line_info(page + len, info);
3698 len += l;
3699 if (len+begin > off+count)
3700 goto done;
3701 if (len+begin < off) {
3702 begin += len;
3703 len = 0;
3704 }
3705 info = info->next_device;
3706 }
3707
3708 *eof = 1;
3709 done:
3710 if (off >= len+begin)
3711 return 0;
3712 *start = page + (off-begin);
3713 return ((count < begin+len-off) ? count : begin+len-off);
3714
3715 } /* end of mgsl_read_proc() */
3716
3717 /* mgsl_allocate_dma_buffers()
3718 *
3719 * Allocate and format DMA buffers (ISA adapter)
3720 * or format shared memory buffers (PCI adapter).
3721 *
3722 * Arguments: info pointer to device instance data
3723 * Return Value: 0 if success, otherwise error
3724 */
3725 int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3726 {
3727 unsigned short BuffersPerFrame;
3728
3729 info->last_mem_alloc = 0;
3730
3731 /* Calculate the number of DMA buffers necessary to hold the */
3732 /* largest allowable frame size. Note: If the max frame size is */
3733 /* not an even multiple of the DMA buffer size then we need to */
3734 /* round the buffer count per frame up one. */
3735
3736 BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3737 if ( info->max_frame_size % DMABUFFERSIZE )
3738 BuffersPerFrame++;
3739
3740 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3741 /*
3742 * The PCI adapter has 256KBytes of shared memory to use.
3743 * This is 64 PAGE_SIZE buffers.
3744 *
3745 * The first page is used for padding at this time so the
3746 * buffer list does not begin at offset 0 of the PCI
3747 * adapter's shared memory.
3748 *
3749 * The 2nd page is used for the buffer list. A 4K buffer
3750 * list can hold 128 DMA_BUFFER structures at 32 bytes
3751 * each.
3752 *
3753 * This leaves 62 4K pages.
3754 *
3755 * The next N pages are used for transmit frame(s). We
3756 * reserve enough 4K page blocks to hold the required
3757 * number of transmit dma buffers (num_tx_dma_buffers),
3758 * each of MaxFrameSize size.
3759 *
3760 * Of the remaining pages (62-N), determine how many can
3761 * be used to receive full MaxFrameSize inbound frames
3762 */
3763 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3764 info->rx_buffer_count = 62 - info->tx_buffer_count;
3765 } else {
3766 /* Calculate the number of PAGE_SIZE buffers needed for */
3767 /* receive and transmit DMA buffers. */
3768
3769
3770 /* Calculate the number of DMA buffers necessary to */
3771 /* hold 7 max size receive frames and one max size transmit frame. */
3772 /* The receive buffer count is bumped by one so we avoid an */
3773 /* End of List condition if all receive buffers are used when */
3774 /* using linked list DMA buffers. */
3775
3776 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3777 info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3778
3779 /*
3780 * limit total TxBuffers & RxBuffers to 62 4K total
3781 * (ala PCI Allocation)
3782 */
3783
3784 if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3785 info->rx_buffer_count = 62 - info->tx_buffer_count;
3786
3787 }
3788
3789 if ( debug_level >= DEBUG_LEVEL_INFO )
3790 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3791 __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3792
3793 if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3794 mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
3795 mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
3796 mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
3797 mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3798 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3799 return -ENOMEM;
3800 }
3801
3802 mgsl_reset_rx_dma_buffers( info );
3803 mgsl_reset_tx_dma_buffers( info );
3804
3805 return 0;
3806
3807 } /* end of mgsl_allocate_dma_buffers() */
3808
3809 /*
3810 * mgsl_alloc_buffer_list_memory()
3811 *
3812 * Allocate a common DMA buffer for use as the
3813 * receive and transmit buffer lists.
3814 *
3815 * A buffer list is a set of buffer entries where each entry contains
3816 * a pointer to an actual buffer and a pointer to the next buffer entry
3817 * (plus some other info about the buffer).
3818 *
3819 * The buffer entries for a list are built to form a circular list so
3820 * that when the entire list has been traversed you start back at the
3821 * beginning.
3822 *
3823 * This function allocates memory for just the buffer entries.
3824 * The links (pointer to next entry) are filled in with the physical
3825 * address of the next entry so the adapter can navigate the list
3826 * using bus master DMA. The pointers to the actual buffers are filled
3827 * out later when the actual buffers are allocated.
3828 *
3829 * Arguments: info pointer to device instance data
3830 * Return Value: 0 if success, otherwise error
3831 */
3832 int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3833 {
3834 unsigned int i;
3835
3836 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3837 /* PCI adapter uses shared memory. */
3838 info->buffer_list = info->memory_base + info->last_mem_alloc;
3839 info->buffer_list_phys = info->last_mem_alloc;
3840 info->last_mem_alloc += BUFFERLISTSIZE;
3841 } else {
3842 /* ISA adapter uses system memory. */
3843 /* The buffer lists are allocated as a common buffer that both */
3844 /* the processor and adapter can access. This allows the driver to */
3845 /* inspect portions of the buffer while other portions are being */
3846 /* updated by the adapter using Bus Master DMA. */
3847
3848 info->buffer_list = kmalloc(BUFFERLISTSIZE, GFP_KERNEL | GFP_DMA);
3849 if ( info->buffer_list == NULL )
3850 return -ENOMEM;
3851
3852 info->buffer_list_phys = isa_virt_to_bus(info->buffer_list);
3853 }
3854
3855 /* We got the memory for the buffer entry lists. */
3856 /* Initialize the memory block to all zeros. */
3857 memset( info->buffer_list, 0, BUFFERLISTSIZE );
3858
3859 /* Save virtual address pointers to the receive and */
3860 /* transmit buffer lists. (Receive 1st). These pointers will */
3861 /* be used by the processor to access the lists. */
3862 info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3863 info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3864 info->tx_buffer_list += info->rx_buffer_count;
3865
3866 /*
3867 * Build the links for the buffer entry lists such that
3868 * two circular lists are built. (Transmit and Receive).
3869 *
3870 * Note: the links are physical addresses
3871 * which are read by the adapter to determine the next
3872 * buffer entry to use.
3873 */
3874
3875 for ( i = 0; i < info->rx_buffer_count; i++ ) {
3876 /* calculate and store physical address of this buffer entry */
3877 info->rx_buffer_list[i].phys_entry =
3878 info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3879
3880 /* calculate and store physical address of */
3881 /* next entry in cirular list of entries */
3882
3883 info->rx_buffer_list[i].link = info->buffer_list_phys;
3884
3885 if ( i < info->rx_buffer_count - 1 )
3886 info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3887 }
3888
3889 for ( i = 0; i < info->tx_buffer_count; i++ ) {
3890 /* calculate and store physical address of this buffer entry */
3891 info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3892 ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3893
3894 /* calculate and store physical address of */
3895 /* next entry in cirular list of entries */
3896
3897 info->tx_buffer_list[i].link = info->buffer_list_phys +
3898 info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3899
3900 if ( i < info->tx_buffer_count - 1 )
3901 info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3902 }
3903
3904 return 0;
3905
3906 } /* end of mgsl_alloc_buffer_list_memory() */
3907
3908 /* Free DMA buffers allocated for use as the
3909 * receive and transmit buffer lists.
3910 * Warning:
3911 *
3912 * The data transfer buffers associated with the buffer list
3913 * MUST be freed before freeing the buffer list itself because
3914 * the buffer list contains the information necessary to free
3915 * the individual buffers!
3916 */
3917 void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3918 {
3919 if ( info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI )
3920 kfree(info->buffer_list);
3921
3922 info->buffer_list = NULL;
3923 info->rx_buffer_list = NULL;
3924 info->tx_buffer_list = NULL;
3925
3926 } /* end of mgsl_free_buffer_list_memory() */
3927
3928 /*
3929 * mgsl_alloc_frame_memory()
3930 *
3931 * Allocate the frame DMA buffers used by the specified buffer list.
3932 * Each DMA buffer will be one memory page in size. This is necessary
3933 * because memory can fragment enough that it may be impossible
3934 * contiguous pages.
3935 *
3936 * Arguments:
3937 *
3938 * info pointer to device instance data
3939 * BufferList pointer to list of buffer entries
3940 * Buffercount count of buffer entries in buffer list
3941 *
3942 * Return Value: 0 if success, otherwise -ENOMEM
3943 */
3944 int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3945 {
3946 int i;
3947 unsigned long phys_addr;
3948
3949 /* Allocate page sized buffers for the receive buffer list */
3950
3951 for ( i = 0; i < Buffercount; i++ ) {
3952 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3953 /* PCI adapter uses shared memory buffers. */
3954 BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3955 phys_addr = info->last_mem_alloc;
3956 info->last_mem_alloc += DMABUFFERSIZE;
3957 } else {
3958 /* ISA adapter uses system memory. */
3959 BufferList[i].virt_addr =
3960 kmalloc(DMABUFFERSIZE, GFP_KERNEL | GFP_DMA);
3961 if ( BufferList[i].virt_addr == NULL )
3962 return -ENOMEM;
3963 phys_addr = isa_virt_to_bus(BufferList[i].virt_addr);
3964 }
3965 BufferList[i].phys_addr = phys_addr;
3966 }
3967
3968 return 0;
3969
3970 } /* end of mgsl_alloc_frame_memory() */
3971
3972 /*
3973 * mgsl_free_frame_memory()
3974 *
3975 * Free the buffers associated with
3976 * each buffer entry of a buffer list.
3977 *
3978 * Arguments:
3979 *
3980 * info pointer to device instance data
3981 * BufferList pointer to list of buffer entries
3982 * Buffercount count of buffer entries in buffer list
3983 *
3984 * Return Value: None
3985 */
3986 void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3987 {
3988 int i;
3989
3990 if ( BufferList ) {
3991 for ( i = 0 ; i < Buffercount ; i++ ) {
3992 if ( BufferList[i].virt_addr ) {
3993 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
3994 kfree(BufferList[i].virt_addr);
3995 BufferList[i].virt_addr = NULL;
3996 }
3997 }
3998 }
3999
4000 } /* end of mgsl_free_frame_memory() */
4001
4002 /* mgsl_free_dma_buffers()
4003 *
4004 * Free DMA buffers
4005 *
4006 * Arguments: info pointer to device instance data
4007 * Return Value: None
4008 */
4009 void mgsl_free_dma_buffers( struct mgsl_struct *info )
4010 {
4011 mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
4012 mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
4013 mgsl_free_buffer_list_memory( info );
4014
4015 } /* end of mgsl_free_dma_buffers() */
4016
4017
4018 /*
4019 * mgsl_alloc_intermediate_rxbuffer_memory()
4020 *
4021 * Allocate a buffer large enough to hold max_frame_size. This buffer
4022 * is used to pass an assembled frame to the line discipline.
4023 *
4024 * Arguments:
4025 *
4026 * info pointer to device instance data
4027 *
4028 * Return Value: 0 if success, otherwise -ENOMEM
4029 */
4030 int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
4031 {
4032 info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
4033 if ( info->intermediate_rxbuffer == NULL )
4034 return -ENOMEM;
4035
4036 return 0;
4037
4038 } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
4039
4040 /*
4041 * mgsl_free_intermediate_rxbuffer_memory()
4042 *
4043 *
4044 * Arguments:
4045 *
4046 * info pointer to device instance data
4047 *
4048 * Return Value: None
4049 */
4050 void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
4051 {
4052 if ( info->intermediate_rxbuffer )
4053 kfree(info->intermediate_rxbuffer);
4054
4055 info->intermediate_rxbuffer = NULL;
4056
4057 } /* end of mgsl_free_intermediate_rxbuffer_memory() */
4058
4059 /*
4060 * mgsl_alloc_intermediate_txbuffer_memory()
4061 *
4062 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
4063 * This buffer is used to load transmit frames into the adapter's dma transfer
4064 * buffers when there is sufficient space.
4065 *
4066 * Arguments:
4067 *
4068 * info pointer to device instance data
4069 *
4070 * Return Value: 0 if success, otherwise -ENOMEM
4071 */
4072 int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
4073 {
4074 int i;
4075
4076 if ( debug_level >= DEBUG_LEVEL_INFO )
4077 printk("%s %s(%d) allocating %d tx holding buffers\n",
4078 info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
4079
4080 memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
4081
4082 for ( i=0; i<info->num_tx_holding_buffers; ++i) {
4083 info->tx_holding_buffers[i].buffer =
4084 kmalloc(info->max_frame_size, GFP_KERNEL);
4085 if ( info->tx_holding_buffers[i].buffer == NULL )
4086 return -ENOMEM;
4087 }
4088
4089 return 0;
4090
4091 } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
4092
4093 /*
4094 * mgsl_free_intermediate_txbuffer_memory()
4095 *
4096 *
4097 * Arguments:
4098 *
4099 * info pointer to device instance data
4100 *
4101 * Return Value: None
4102 */
4103 void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
4104 {
4105 int i;
4106
4107 for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
4108 if ( info->tx_holding_buffers[i].buffer ) {
4109 kfree(info->tx_holding_buffers[i].buffer);
4110 info->tx_holding_buffers[i].buffer=NULL;
4111 }
4112 }
4113
4114 info->get_tx_holding_index = 0;
4115 info->put_tx_holding_index = 0;
4116 info->tx_holding_count = 0;
4117
4118 } /* end of mgsl_free_intermediate_txbuffer_memory() */
4119
4120
4121 /*
4122 * load_next_tx_holding_buffer()
4123 *
4124 * attempts to load the next buffered tx request into the
4125 * tx dma buffers
4126 *
4127 * Arguments:
4128 *
4129 * info pointer to device instance data
4130 *
4131 * Return Value: 1 if next buffered tx request loaded
4132 * into adapter's tx dma buffer,
4133 * 0 otherwise
4134 */
4135 int load_next_tx_holding_buffer(struct mgsl_struct *info)
4136 {
4137 int ret = 0;
4138
4139 if ( info->tx_holding_count ) {
4140 /* determine if we have enough tx dma buffers
4141 * to accommodate the next tx frame
4142 */
4143 struct tx_holding_buffer *ptx =
4144 &info->tx_holding_buffers[info->get_tx_holding_index];
4145 int num_free = num_free_tx_dma_buffers(info);
4146 int num_needed = ptx->buffer_size / DMABUFFERSIZE;
4147 if ( ptx->buffer_size % DMABUFFERSIZE )
4148 ++num_needed;
4149
4150 if (num_needed <= num_free) {
4151 info->xmit_cnt = ptx->buffer_size;
4152 mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
4153
4154 --info->tx_holding_count;
4155 if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
4156 info->get_tx_holding_index=0;
4157
4158 /* restart transmit timer */
4159 mod_timer(&info->tx_timer, jiffies + jiffies_from_ms(5000));
4160
4161 ret = 1;
4162 }
4163 }
4164
4165 return ret;
4166 }
4167
4168 /*
4169 * save_tx_buffer_request()
4170 *
4171 * attempt to store transmit frame request for later transmission
4172 *
4173 * Arguments:
4174 *
4175 * info pointer to device instance data
4176 * Buffer pointer to buffer containing frame to load
4177 * BufferSize size in bytes of frame in Buffer
4178 *
4179 * Return Value: 1 if able to store, 0 otherwise
4180 */
4181 int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4182 {
4183 struct tx_holding_buffer *ptx;
4184
4185 if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4186 return 0; /* all buffers in use */
4187 }
4188
4189 ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4190 ptx->buffer_size = BufferSize;
4191 memcpy( ptx->buffer, Buffer, BufferSize);
4192
4193 ++info->tx_holding_count;
4194 if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4195 info->put_tx_holding_index=0;
4196
4197 return 1;
4198 }
4199
4200 int mgsl_claim_resources(struct mgsl_struct *info)
4201 {
4202 if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4203 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4204 __FILE__,__LINE__,info->device_name, info->io_base);
4205 return -ENODEV;
4206 }
4207 info->io_addr_requested = 1;
4208
4209 if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4210 info->device_name, info ) < 0 ) {
4211 printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
4212 __FILE__,__LINE__,info->device_name, info->irq_level );
4213 goto errout;
4214 }
4215 info->irq_requested = 1;
4216
4217 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4218 if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4219 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4220 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4221 goto errout;
4222 }
4223 info->shared_mem_requested = 1;
4224 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4225 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4226 __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4227 goto errout;
4228 }
4229 info->lcr_mem_requested = 1;
4230
4231 info->memory_base = ioremap(info->phys_memory_base,0x40000);
4232 if (!info->memory_base) {
4233 printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
4234 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4235 goto errout;
4236 }
4237
4238 if ( !mgsl_memory_test(info) ) {
4239 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4240 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4241 goto errout;
4242 }
4243
4244 info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE) + info->lcr_offset;
4245 if (!info->lcr_base) {
4246 printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
4247 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4248 goto errout;
4249 }
4250
4251 } else {
4252 /* claim DMA channel */
4253
4254 if (request_dma(info->dma_level,info->device_name) < 0){
4255 printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
4256 __FILE__,__LINE__,info->device_name, info->dma_level );
4257 mgsl_release_resources( info );
4258 return -ENODEV;
4259 }
4260 info->dma_requested = 1;
4261
4262 /* ISA adapter uses bus master DMA */
4263 set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4264 enable_dma(info->dma_level);
4265 }
4266
4267 if ( mgsl_allocate_dma_buffers(info) < 0 ) {
4268 printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
4269 __FILE__,__LINE__,info->device_name, info->dma_level );
4270 goto errout;
4271 }
4272
4273 return 0;
4274 errout:
4275 mgsl_release_resources(info);
4276 return -ENODEV;
4277
4278 } /* end of mgsl_claim_resources() */
4279
4280 void mgsl_release_resources(struct mgsl_struct *info)
4281 {
4282 if ( debug_level >= DEBUG_LEVEL_INFO )
4283 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4284 __FILE__,__LINE__,info->device_name );
4285
4286 if ( info->irq_requested ) {
4287 free_irq(info->irq_level, info);
4288 info->irq_requested = 0;
4289 }
4290 if ( info->dma_requested ) {
4291 disable_dma(info->dma_level);
4292 free_dma(info->dma_level);
4293 info->dma_requested = 0;
4294 }
4295 mgsl_free_dma_buffers(info);
4296 mgsl_free_intermediate_rxbuffer_memory(info);
4297 mgsl_free_intermediate_txbuffer_memory(info);
4298
4299 if ( info->io_addr_requested ) {
4300 release_region(info->io_base,info->io_addr_size);
4301 info->io_addr_requested = 0;
4302 }
4303 if ( info->shared_mem_requested ) {
4304 release_mem_region(info->phys_memory_base,0x40000);
4305 info->shared_mem_requested = 0;
4306 }
4307 if ( info->lcr_mem_requested ) {
4308 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
4309 info->lcr_mem_requested = 0;
4310 }
4311 if (info->memory_base){
4312 iounmap(info->memory_base);
4313 info->memory_base = 0;
4314 }
4315 if (info->lcr_base){
4316 iounmap(info->lcr_base - info->lcr_offset);
4317 info->lcr_base = 0;
4318 }
4319
4320 if ( debug_level >= DEBUG_LEVEL_INFO )
4321 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4322 __FILE__,__LINE__,info->device_name );
4323
4324 } /* end of mgsl_release_resources() */
4325
4326 /* mgsl_add_device()
4327 *
4328 * Add the specified device instance data structure to the
4329 * global linked list of devices and increment the device count.
4330 *
4331 * Arguments: info pointer to device instance data
4332 * Return Value: None
4333 */
4334 void mgsl_add_device( struct mgsl_struct *info )
4335 {
4336 info->next_device = NULL;
4337 info->line = mgsl_device_count;
4338 sprintf(info->device_name,"ttySL%d",info->line);
4339
4340 if (info->line < MAX_TOTAL_DEVICES) {
4341 if (maxframe[info->line])
4342 info->max_frame_size = maxframe[info->line];
4343 info->dosyncppp = dosyncppp[info->line];
4344
4345 if (txdmabufs[info->line]) {
4346 info->num_tx_dma_buffers = txdmabufs[info->line];
4347 if (info->num_tx_dma_buffers < 1)
4348 info->num_tx_dma_buffers = 1;
4349 }
4350
4351 if (txholdbufs[info->line]) {
4352 info->num_tx_holding_buffers = txholdbufs[info->line];
4353 if (info->num_tx_holding_buffers < 1)
4354 info->num_tx_holding_buffers = 1;
4355 else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4356 info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4357 }
4358 }
4359
4360 mgsl_device_count++;
4361
4362 if ( !mgsl_device_list )
4363 mgsl_device_list = info;
4364 else {
4365 struct mgsl_struct *current_dev = mgsl_device_list;
4366 while( current_dev->next_device )
4367 current_dev = current_dev->next_device;
4368 current_dev->next_device = info;
4369 }
4370
4371 if ( info->max_frame_size < 4096 )
4372 info->max_frame_size = 4096;
4373 else if ( info->max_frame_size > 65535 )
4374 info->max_frame_size = 65535;
4375
4376 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4377 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4378 info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4379 info->phys_memory_base, info->phys_lcr_base,
4380 info->max_frame_size );
4381 } else {
4382 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4383 info->device_name, info->io_base, info->irq_level, info->dma_level,
4384 info->max_frame_size );
4385 }
4386
4387 #ifdef CONFIG_SYNCLINK_SYNCPPP
4388 #ifdef MODULE
4389 if (info->dosyncppp)
4390 #endif
4391 mgsl_sppp_init(info);
4392 #endif
4393 } /* end of mgsl_add_device() */
4394
4395 /* mgsl_allocate_device()
4396 *
4397 * Allocate and initialize a device instance structure
4398 *
4399 * Arguments: none
4400 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4401 */
4402 struct mgsl_struct* mgsl_allocate_device()
4403 {
4404 struct mgsl_struct *info;
4405
4406 info = (struct mgsl_struct *)kmalloc(sizeof(struct mgsl_struct),
4407 GFP_KERNEL);
4408
4409 if (!info) {
4410 printk("Error can't allocate device instance data\n");
4411 } else {
4412 memset(info, 0, sizeof(struct mgsl_struct));
4413 info->magic = MGSL_MAGIC;
4414 INIT_WORK(&info->task, mgsl_bh_handler, info);
4415 info->max_frame_size = 4096;
4416 info->close_delay = 5*HZ/10;
4417 info->closing_wait = 30*HZ;
4418 init_waitqueue_head(&info->open_wait);
4419 init_waitqueue_head(&info->close_wait);
4420 init_waitqueue_head(&info->status_event_wait_q);
4421 init_waitqueue_head(&info->event_wait_q);
4422 spin_lock_init(&info->irq_spinlock);
4423 spin_lock_init(&info->netlock);
4424 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4425 info->idle_mode = HDLC_TXIDLE_FLAGS;
4426 info->num_tx_dma_buffers = 1;
4427 info->num_tx_holding_buffers = 0;
4428 }
4429
4430 return info;
4431
4432 } /* end of mgsl_allocate_device()*/
4433
4434 static struct tty_operations mgsl_ops = {
4435 .open = mgsl_open,
4436 .close = mgsl_close,
4437 .write = mgsl_write,
4438 .put_char = mgsl_put_char,
4439 .flush_chars = mgsl_flush_chars,
4440 .write_room = mgsl_write_room,
4441 .chars_in_buffer = mgsl_chars_in_buffer,
4442 .flush_buffer = mgsl_flush_buffer,
4443 .ioctl = mgsl_ioctl,
4444 .throttle = mgsl_throttle,
4445 .unthrottle = mgsl_unthrottle,
4446 .send_xchar = mgsl_send_xchar,
4447 .break_ctl = mgsl_break,
4448 .wait_until_sent = mgsl_wait_until_sent,
4449 .read_proc = mgsl_read_proc,
4450 .set_termios = mgsl_set_termios,
4451 .stop = mgsl_stop,
4452 .start = mgsl_start,
4453 .hangup = mgsl_hangup,
4454 .tiocmget = tiocmget,
4455 .tiocmset = tiocmset,
4456 };
4457
4458 /*
4459 * perform tty device initialization
4460 */
4461 int mgsl_init_tty(void);
4462 int mgsl_init_tty()
4463 {
4464 serial_driver = alloc_tty_driver(mgsl_device_count);
4465 if (!serial_driver)
4466 return -ENOMEM;
4467
4468 serial_driver->owner = THIS_MODULE;
4469 serial_driver->driver_name = "synclink";
4470 serial_driver->name = "ttySL";
4471 serial_driver->major = ttymajor;
4472 serial_driver->minor_start = 64;
4473 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4474 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4475 serial_driver->init_termios = tty_std_termios;
4476 serial_driver->init_termios.c_cflag =
4477 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4478 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4479 tty_set_operations(serial_driver, &mgsl_ops);
4480 if (tty_register_driver(serial_driver) < 0)
4481 printk("%s(%d):Couldn't register serial driver\n",
4482 __FILE__,__LINE__);
4483
4484 printk("%s %s, tty major#%d\n",
4485 driver_name, driver_version,
4486 serial_driver->major);
4487 return 0;
4488 }
4489
4490 /* enumerate user specified ISA adapters
4491 */
4492 int mgsl_enum_isa_devices()
4493 {
4494 struct mgsl_struct *info;
4495 int i;
4496
4497 /* Check for user specified ISA devices */
4498
4499 for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4500 if ( debug_level >= DEBUG_LEVEL_INFO )
4501 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4502 io[i], irq[i], dma[i] );
4503
4504 info = mgsl_allocate_device();
4505 if ( !info ) {
4506 /* error allocating device instance data */
4507 if ( debug_level >= DEBUG_LEVEL_ERROR )
4508 printk( "can't allocate device instance data.\n");
4509 continue;
4510 }
4511
4512 /* Copy user configuration info to device instance data */
4513 info->io_base = (unsigned int)io[i];
4514 info->irq_level = (unsigned int)irq[i];
4515 info->irq_level = irq_canonicalize(info->irq_level);
4516 info->dma_level = (unsigned int)dma[i];
4517 info->bus_type = MGSL_BUS_TYPE_ISA;
4518 info->io_addr_size = 16;
4519 info->irq_flags = 0;
4520
4521 mgsl_add_device( info );
4522 }
4523
4524 return 0;
4525 }
4526
4527 /* mgsl_init()
4528 *
4529 * Driver initialization entry point.
4530 *
4531 * Arguments: None
4532 * Return Value: 0 if success, otherwise error code
4533 */
4534 int __init mgsl_init(void)
4535 {
4536 int rc;
4537
4538 printk("%s %s\n", driver_name, driver_version);
4539
4540 mgsl_enum_isa_devices();
4541 pci_register_driver(&synclink_pci_driver);
4542
4543 if ( !mgsl_device_list ) {
4544 printk("%s(%d):No SyncLink devices found.\n",__FILE__,__LINE__);
4545 return -ENODEV;
4546 }
4547 if ((rc = mgsl_init_tty()))
4548 return rc;
4549
4550 return 0;
4551 }
4552
4553 static int __init synclink_init(void)
4554 {
4555 /* Uncomment this to kernel debug module.
4556 * mgsl_get_text_ptr() leaves the .text address in eax
4557 * which can be used with add-symbol-file with gdb.
4558 */
4559 if (break_on_load) {
4560 mgsl_get_text_ptr();
4561 BREAKPOINT();
4562 }
4563
4564 return mgsl_init();
4565 }
4566
4567 static void __exit synclink_exit(void)
4568 {
4569 int rc;
4570 struct mgsl_struct *info;
4571 struct mgsl_struct *tmp;
4572
4573 printk("Unloading %s: %s\n", driver_name, driver_version);
4574
4575 if ((rc = tty_unregister_driver(serial_driver)))
4576 printk("%s(%d) failed to unregister tty driver err=%d\n",
4577 __FILE__,__LINE__,rc);
4578
4579 put_tty_driver(serial_driver);
4580 info = mgsl_device_list;
4581 while(info) {
4582 #ifdef CONFIG_SYNCLINK_SYNCPPP
4583 if (info->dosyncppp)
4584 mgsl_sppp_delete(info);
4585 #endif
4586 mgsl_release_resources(info);
4587 tmp = info;
4588 info = info->next_device;
4589 kfree(tmp);
4590 }
4591
4592 if (tmp_buf) {
4593 free_page((unsigned long) tmp_buf);
4594 tmp_buf = NULL;
4595 }
4596
4597 pci_unregister_driver(&synclink_pci_driver);
4598 }
4599
4600 module_init(synclink_init);
4601 module_exit(synclink_exit);
4602
4603 /*
4604 * usc_RTCmd()
4605 *
4606 * Issue a USC Receive/Transmit command to the
4607 * Channel Command/Address Register (CCAR).
4608 *
4609 * Notes:
4610 *
4611 * The command is encoded in the most significant 5 bits <15..11>
4612 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4613 * and Bits <6..0> must be written as zeros.
4614 *
4615 * Arguments:
4616 *
4617 * info pointer to device information structure
4618 * Cmd command mask (use symbolic macros)
4619 *
4620 * Return Value:
4621 *
4622 * None
4623 */
4624 void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4625 {
4626 /* output command to CCAR in bits <15..11> */
4627 /* preserve bits <10..7>, bits <6..0> must be zero */
4628
4629 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4630
4631 /* Read to flush write to CCAR */
4632 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4633 inw( info->io_base + CCAR );
4634
4635 } /* end of usc_RTCmd() */
4636
4637 /*
4638 * usc_DmaCmd()
4639 *
4640 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4641 *
4642 * Arguments:
4643 *
4644 * info pointer to device information structure
4645 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4646 *
4647 * Return Value:
4648 *
4649 * None
4650 */
4651 void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4652 {
4653 /* write command mask to DCAR */
4654 outw( Cmd + info->mbre_bit, info->io_base );
4655
4656 /* Read to flush write to DCAR */
4657 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4658 inw( info->io_base );
4659
4660 } /* end of usc_DmaCmd() */
4661
4662 /*
4663 * usc_OutDmaReg()
4664 *
4665 * Write a 16-bit value to a USC DMA register
4666 *
4667 * Arguments:
4668 *
4669 * info pointer to device info structure
4670 * RegAddr register address (number) for write
4671 * RegValue 16-bit value to write to register
4672 *
4673 * Return Value:
4674 *
4675 * None
4676 *
4677 */
4678 void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4679 {
4680 /* Note: The DCAR is located at the adapter base address */
4681 /* Note: must preserve state of BIT8 in DCAR */
4682
4683 outw( RegAddr + info->mbre_bit, info->io_base );
4684 outw( RegValue, info->io_base );
4685
4686 /* Read to flush write to DCAR */
4687 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4688 inw( info->io_base );
4689
4690 } /* end of usc_OutDmaReg() */
4691
4692 /*
4693 * usc_InDmaReg()
4694 *
4695 * Read a 16-bit value from a DMA register
4696 *
4697 * Arguments:
4698 *
4699 * info pointer to device info structure
4700 * RegAddr register address (number) to read from
4701 *
4702 * Return Value:
4703 *
4704 * The 16-bit value read from register
4705 *
4706 */
4707 u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4708 {
4709 /* Note: The DCAR is located at the adapter base address */
4710 /* Note: must preserve state of BIT8 in DCAR */
4711
4712 outw( RegAddr + info->mbre_bit, info->io_base );
4713 return inw( info->io_base );
4714
4715 } /* end of usc_InDmaReg() */
4716
4717 /*
4718 *
4719 * usc_OutReg()
4720 *
4721 * Write a 16-bit value to a USC serial channel register
4722 *
4723 * Arguments:
4724 *
4725 * info pointer to device info structure
4726 * RegAddr register address (number) to write to
4727 * RegValue 16-bit value to write to register
4728 *
4729 * Return Value:
4730 *
4731 * None
4732 *
4733 */
4734 void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4735 {
4736 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4737 outw( RegValue, info->io_base + CCAR );
4738
4739 /* Read to flush write to CCAR */
4740 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4741 inw( info->io_base + CCAR );
4742
4743 } /* end of usc_OutReg() */
4744
4745 /*
4746 * usc_InReg()
4747 *
4748 * Reads a 16-bit value from a USC serial channel register
4749 *
4750 * Arguments:
4751 *
4752 * info pointer to device extension
4753 * RegAddr register address (number) to read from
4754 *
4755 * Return Value:
4756 *
4757 * 16-bit value read from register
4758 */
4759 u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4760 {
4761 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4762 return inw( info->io_base + CCAR );
4763
4764 } /* end of usc_InReg() */
4765
4766 /* usc_set_sdlc_mode()
4767 *
4768 * Set up the adapter for SDLC DMA communications.
4769 *
4770 * Arguments: info pointer to device instance data
4771 * Return Value: NONE
4772 */
4773 void usc_set_sdlc_mode( struct mgsl_struct *info )
4774 {
4775 u16 RegValue;
4776 int PreSL1660;
4777
4778 /*
4779 * determine if the IUSC on the adapter is pre-SL1660. If
4780 * not, take advantage of the UnderWait feature of more
4781 * modern chips. If an underrun occurs and this bit is set,
4782 * the transmitter will idle the programmed idle pattern
4783 * until the driver has time to service the underrun. Otherwise,
4784 * the dma controller may get the cycles previously requested
4785 * and begin transmitting queued tx data.
4786 */
4787 usc_OutReg(info,TMCR,0x1f);
4788 RegValue=usc_InReg(info,TMDR);
4789 if ( RegValue == IUSC_PRE_SL1660 )
4790 PreSL1660 = 1;
4791 else
4792 PreSL1660 = 0;
4793
4794
4795 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4796 {
4797 /*
4798 ** Channel Mode Register (CMR)
4799 **
4800 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4801 ** <13> 0 0 = Transmit Disabled (initially)
4802 ** <12> 0 1 = Consecutive Idles share common 0
4803 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4804 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4805 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4806 **
4807 ** 1000 1110 0000 0110 = 0x8e06
4808 */
4809 RegValue = 0x8e06;
4810
4811 /*--------------------------------------------------
4812 * ignore user options for UnderRun Actions and
4813 * preambles
4814 *--------------------------------------------------*/
4815 }
4816 else
4817 {
4818 /* Channel mode Register (CMR)
4819 *
4820 * <15..14> 00 Tx Sub modes, Underrun Action
4821 * <13> 0 1 = Send Preamble before opening flag
4822 * <12> 0 1 = Consecutive Idles share common 0
4823 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4824 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4825 * <3..0> 0110 Receiver mode = HDLC/SDLC
4826 *
4827 * 0000 0110 0000 0110 = 0x0606
4828 */
4829 if (info->params.mode == MGSL_MODE_RAW) {
4830 RegValue = 0x0001; /* Set Receive mode = external sync */
4831
4832 usc_OutReg( info, IOCR, /* Set IOCR DCD is RxSync Detect Input */
4833 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4834
4835 /*
4836 * TxSubMode:
4837 * CMR <15> 0 Don't send CRC on Tx Underrun
4838 * CMR <14> x undefined
4839 * CMR <13> 0 Send preamble before openning sync
4840 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4841 *
4842 * TxMode:
4843 * CMR <11-8) 0100 MonoSync
4844 *
4845 * 0x00 0100 xxxx xxxx 04xx
4846 */
4847 RegValue |= 0x0400;
4848 }
4849 else {
4850
4851 RegValue = 0x0606;
4852
4853 if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4854 RegValue |= BIT14;
4855 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4856 RegValue |= BIT15;
4857 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4858 RegValue |= BIT15 + BIT14;
4859 }
4860
4861 if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4862 RegValue |= BIT13;
4863 }
4864
4865 if ( info->params.mode == MGSL_MODE_HDLC &&
4866 (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4867 RegValue |= BIT12;
4868
4869 if ( info->params.addr_filter != 0xff )
4870 {
4871 /* set up receive address filtering */
4872 usc_OutReg( info, RSR, info->params.addr_filter );
4873 RegValue |= BIT4;
4874 }
4875
4876 usc_OutReg( info, CMR, RegValue );
4877 info->cmr_value = RegValue;
4878
4879 /* Receiver mode Register (RMR)
4880 *
4881 * <15..13> 000 encoding
4882 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4883 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4884 * <9> 0 1 = Include Receive chars in CRC
4885 * <8> 1 1 = Use Abort/PE bit as abort indicator
4886 * <7..6> 00 Even parity
4887 * <5> 0 parity disabled
4888 * <4..2> 000 Receive Char Length = 8 bits
4889 * <1..0> 00 Disable Receiver
4890 *
4891 * 0000 0101 0000 0000 = 0x0500
4892 */
4893
4894 RegValue = 0x0500;
4895
4896 switch ( info->params.encoding ) {
4897 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4898 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4899 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4900 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4901 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4902 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4903 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4904 }
4905
4906 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4907 RegValue |= BIT9;
4908 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4909 RegValue |= ( BIT12 | BIT10 | BIT9 );
4910
4911 usc_OutReg( info, RMR, RegValue );
4912
4913 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4914 /* When an opening flag of an SDLC frame is recognized the */
4915 /* Receive Character count (RCC) is loaded with the value in */
4916 /* RCLR. The RCC is decremented for each received byte. The */
4917 /* value of RCC is stored after the closing flag of the frame */
4918 /* allowing the frame size to be computed. */
4919
4920 usc_OutReg( info, RCLR, RCLRVALUE );
4921
4922 usc_RCmd( info, RCmd_SelectRicrdma_level );
4923
4924 /* Receive Interrupt Control Register (RICR)
4925 *
4926 * <15..8> ? RxFIFO DMA Request Level
4927 * <7> 0 Exited Hunt IA (Interrupt Arm)
4928 * <6> 0 Idle Received IA
4929 * <5> 0 Break/Abort IA
4930 * <4> 0 Rx Bound IA
4931 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4932 * <2> 0 Abort/PE IA
4933 * <1> 1 Rx Overrun IA
4934 * <0> 0 Select TC0 value for readback
4935 *
4936 * 0000 0000 0000 1000 = 0x000a
4937 */
4938
4939 /* Carry over the Exit Hunt and Idle Received bits */
4940 /* in case they have been armed by usc_ArmEvents. */
4941
4942 RegValue = usc_InReg( info, RICR ) & 0xc0;
4943
4944 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4945 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4946 else
4947 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4948
4949 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4950
4951 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4952 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4953
4954 /* Transmit mode Register (TMR)
4955 *
4956 * <15..13> 000 encoding
4957 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4958 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4959 * <9> 0 1 = Tx CRC Enabled
4960 * <8> 0 1 = Append CRC to end of transmit frame
4961 * <7..6> 00 Transmit parity Even
4962 * <5> 0 Transmit parity Disabled
4963 * <4..2> 000 Tx Char Length = 8 bits
4964 * <1..0> 00 Disable Transmitter
4965 *
4966 * 0000 0100 0000 0000 = 0x0400
4967 */
4968
4969 RegValue = 0x0400;
4970
4971 switch ( info->params.encoding ) {
4972 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4973 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4974 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4975 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4976 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4977 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4978 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4979 }
4980
4981 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4982 RegValue |= BIT9 + BIT8;
4983 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4984 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4985
4986 usc_OutReg( info, TMR, RegValue );
4987
4988 usc_set_txidle( info );
4989
4990
4991 usc_TCmd( info, TCmd_SelectTicrdma_level );
4992
4993 /* Transmit Interrupt Control Register (TICR)
4994 *
4995 * <15..8> ? Transmit FIFO DMA Level
4996 * <7> 0 Present IA (Interrupt Arm)
4997 * <6> 0 Idle Sent IA
4998 * <5> 1 Abort Sent IA
4999 * <4> 1 EOF/EOM Sent IA
5000 * <3> 0 CRC Sent IA
5001 * <2> 1 1 = Wait for SW Trigger to Start Frame
5002 * <1> 1 Tx Underrun IA
5003 * <0> 0 TC0 constant on read back
5004 *
5005 * 0000 0000 0011 0110 = 0x0036
5006 */
5007
5008 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5009 usc_OutReg( info, TICR, 0x0736 );
5010 else
5011 usc_OutReg( info, TICR, 0x1436 );
5012
5013 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5014 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5015
5016 /*
5017 ** Transmit Command/Status Register (TCSR)
5018 **
5019 ** <15..12> 0000 TCmd
5020 ** <11> 0/1 UnderWait
5021 ** <10..08> 000 TxIdle
5022 ** <7> x PreSent
5023 ** <6> x IdleSent
5024 ** <5> x AbortSent
5025 ** <4> x EOF/EOM Sent
5026 ** <3> x CRC Sent
5027 ** <2> x All Sent
5028 ** <1> x TxUnder
5029 ** <0> x TxEmpty
5030 **
5031 ** 0000 0000 0000 0000 = 0x0000
5032 */
5033 info->tcsr_value = 0;
5034
5035 if ( !PreSL1660 )
5036 info->tcsr_value |= TCSR_UNDERWAIT;
5037
5038 usc_OutReg( info, TCSR, info->tcsr_value );
5039
5040 /* Clock mode Control Register (CMCR)
5041 *
5042 * <15..14> 00 counter 1 Source = Disabled
5043 * <13..12> 00 counter 0 Source = Disabled
5044 * <11..10> 11 BRG1 Input is TxC Pin
5045 * <9..8> 11 BRG0 Input is TxC Pin
5046 * <7..6> 01 DPLL Input is BRG1 Output
5047 * <5..3> XXX TxCLK comes from Port 0
5048 * <2..0> XXX RxCLK comes from Port 1
5049 *
5050 * 0000 1111 0111 0111 = 0x0f77
5051 */
5052
5053 RegValue = 0x0f40;
5054
5055 if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
5056 RegValue |= 0x0003; /* RxCLK from DPLL */
5057 else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
5058 RegValue |= 0x0004; /* RxCLK from BRG0 */
5059 else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
5060 RegValue |= 0x0006; /* RxCLK from TXC Input */
5061 else
5062 RegValue |= 0x0007; /* RxCLK from Port1 */
5063
5064 if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
5065 RegValue |= 0x0018; /* TxCLK from DPLL */
5066 else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
5067 RegValue |= 0x0020; /* TxCLK from BRG0 */
5068 else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
5069 RegValue |= 0x0038; /* RxCLK from TXC Input */
5070 else
5071 RegValue |= 0x0030; /* TxCLK from Port0 */
5072
5073 usc_OutReg( info, CMCR, RegValue );
5074
5075
5076 /* Hardware Configuration Register (HCR)
5077 *
5078 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
5079 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
5080 * <12> 0 CVOK:0=report code violation in biphase
5081 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
5082 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
5083 * <7..6> 00 reserved
5084 * <5> 0 BRG1 mode:0=continuous,1=single cycle
5085 * <4> X BRG1 Enable
5086 * <3..2> 00 reserved
5087 * <1> 0 BRG0 mode:0=continuous,1=single cycle
5088 * <0> 0 BRG0 Enable
5089 */
5090
5091 RegValue = 0x0000;
5092
5093 if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) {
5094 u32 XtalSpeed;
5095 u32 DpllDivisor;
5096 u16 Tc;
5097
5098 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
5099 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
5100
5101 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5102 XtalSpeed = 11059200;
5103 else
5104 XtalSpeed = 14745600;
5105
5106 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
5107 DpllDivisor = 16;
5108 RegValue |= BIT10;
5109 }
5110 else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
5111 DpllDivisor = 8;
5112 RegValue |= BIT11;
5113 }
5114 else
5115 DpllDivisor = 32;
5116
5117 /* Tc = (Xtal/Speed) - 1 */
5118 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5119 /* then rounding up gives a more precise time constant. Instead */
5120 /* of rounding up and then subtracting 1 we just don't subtract */
5121 /* the one in this case. */
5122
5123 /*--------------------------------------------------
5124 * ejz: for DPLL mode, application should use the
5125 * same clock speed as the partner system, even
5126 * though clocking is derived from the input RxData.
5127 * In case the user uses a 0 for the clock speed,
5128 * default to 0xffffffff and don't try to divide by
5129 * zero
5130 *--------------------------------------------------*/
5131 if ( info->params.clock_speed )
5132 {
5133 Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
5134 if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
5135 / info->params.clock_speed) )
5136 Tc--;
5137 }
5138 else
5139 Tc = -1;
5140
5141
5142 /* Write 16-bit Time Constant for BRG1 */
5143 usc_OutReg( info, TC1R, Tc );
5144
5145 RegValue |= BIT4; /* enable BRG1 */
5146
5147 switch ( info->params.encoding ) {
5148 case HDLC_ENCODING_NRZ:
5149 case HDLC_ENCODING_NRZB:
5150 case HDLC_ENCODING_NRZI_MARK:
5151 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5152 case HDLC_ENCODING_BIPHASE_MARK:
5153 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
5154 case HDLC_ENCODING_BIPHASE_LEVEL:
5155 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
5156 }
5157 }
5158
5159 usc_OutReg( info, HCR, RegValue );
5160
5161
5162 /* Channel Control/status Register (CCSR)
5163 *
5164 * <15> X RCC FIFO Overflow status (RO)
5165 * <14> X RCC FIFO Not Empty status (RO)
5166 * <13> 0 1 = Clear RCC FIFO (WO)
5167 * <12> X DPLL Sync (RW)
5168 * <11> X DPLL 2 Missed Clocks status (RO)
5169 * <10> X DPLL 1 Missed Clock status (RO)
5170 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5171 * <7> X SDLC Loop On status (RO)
5172 * <6> X SDLC Loop Send status (RO)
5173 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5174 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5175 * <1..0> 00 reserved
5176 *
5177 * 0000 0000 0010 0000 = 0x0020
5178 */
5179
5180 usc_OutReg( info, CCSR, 0x1020 );
5181
5182
5183 if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5184 usc_OutReg( info, SICR,
5185 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5186 }
5187
5188
5189 /* enable Master Interrupt Enable bit (MIE) */
5190 usc_EnableMasterIrqBit( info );
5191
5192 usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA +
5193 TRANSMIT_STATUS + TRANSMIT_DATA );
5194
5195 info->mbre_bit = 0;
5196 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5197 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5198 info->mbre_bit = BIT8;
5199 outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
5200
5201 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5202 /* Enable DMAEN (Port 7, Bit 14) */
5203 /* This connects the DMA request signal to the ISA bus */
5204 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5205 }
5206
5207 /* DMA Control Register (DCR)
5208 *
5209 * <15..14> 10 Priority mode = Alternating Tx/Rx
5210 * 01 Rx has priority
5211 * 00 Tx has priority
5212 *
5213 * <13> 1 Enable Priority Preempt per DCR<15..14>
5214 * (WARNING DCR<11..10> must be 00 when this is 1)
5215 * 0 Choose activate channel per DCR<11..10>
5216 *
5217 * <12> 0 Little Endian for Array/List
5218 * <11..10> 00 Both Channels can use each bus grant
5219 * <9..6> 0000 reserved
5220 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5221 * <4> 0 1 = drive D/C and S/D pins
5222 * <3> 1 1 = Add one wait state to all DMA cycles.
5223 * <2> 0 1 = Strobe /UAS on every transfer.
5224 * <1..0> 11 Addr incrementing only affects LS24 bits
5225 *
5226 * 0110 0000 0000 1011 = 0x600b
5227 */
5228
5229 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5230 /* PCI adapter does not need DMA wait state */
5231 usc_OutDmaReg( info, DCR, 0xa00b );
5232 }
5233 else
5234 usc_OutDmaReg( info, DCR, 0x800b );
5235
5236
5237 /* Receive DMA mode Register (RDMR)
5238 *
5239 * <15..14> 11 DMA mode = Linked List Buffer mode
5240 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5241 * <12> 1 Clear count of List Entry after fetching
5242 * <11..10> 00 Address mode = Increment
5243 * <9> 1 Terminate Buffer on RxBound
5244 * <8> 0 Bus Width = 16bits
5245 * <7..0> ? status Bits (write as 0s)
5246 *
5247 * 1111 0010 0000 0000 = 0xf200
5248 */
5249
5250 usc_OutDmaReg( info, RDMR, 0xf200 );
5251
5252
5253 /* Transmit DMA mode Register (TDMR)
5254 *
5255 * <15..14> 11 DMA mode = Linked List Buffer mode
5256 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5257 * <12> 1 Clear count of List Entry after fetching
5258 * <11..10> 00 Address mode = Increment
5259 * <9> 1 Terminate Buffer on end of frame
5260 * <8> 0 Bus Width = 16bits
5261 * <7..0> ? status Bits (Read Only so write as 0)
5262 *
5263 * 1111 0010 0000 0000 = 0xf200
5264 */
5265
5266 usc_OutDmaReg( info, TDMR, 0xf200 );
5267
5268
5269 /* DMA Interrupt Control Register (DICR)
5270 *
5271 * <15> 1 DMA Interrupt Enable
5272 * <14> 0 1 = Disable IEO from USC
5273 * <13> 0 1 = Don't provide vector during IntAck
5274 * <12> 1 1 = Include status in Vector
5275 * <10..2> 0 reserved, Must be 0s
5276 * <1> 0 1 = Rx DMA Interrupt Enabled
5277 * <0> 0 1 = Tx DMA Interrupt Enabled
5278 *
5279 * 1001 0000 0000 0000 = 0x9000
5280 */
5281
5282 usc_OutDmaReg( info, DICR, 0x9000 );
5283
5284 usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */
5285 usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */
5286 usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5287
5288 /* Channel Control Register (CCR)
5289 *
5290 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5291 * <13> 0 Trigger Tx on SW Command Disabled
5292 * <12> 0 Flag Preamble Disabled
5293 * <11..10> 00 Preamble Length
5294 * <9..8> 00 Preamble Pattern
5295 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5296 * <5> 0 Trigger Rx on SW Command Disabled
5297 * <4..0> 0 reserved
5298 *
5299 * 1000 0000 1000 0000 = 0x8080
5300 */
5301
5302 RegValue = 0x8080;
5303
5304 switch ( info->params.preamble_length ) {
5305 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5306 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5307 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break;
5308 }
5309
5310 switch ( info->params.preamble ) {
5311 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
5312 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5313 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
5314 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break;
5315 }
5316
5317 usc_OutReg( info, CCR, RegValue );
5318
5319
5320 /*
5321 * Burst/Dwell Control Register
5322 *
5323 * <15..8> 0x20 Maximum number of transfers per bus grant
5324 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5325 */
5326
5327 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5328 /* don't limit bus occupancy on PCI adapter */
5329 usc_OutDmaReg( info, BDCR, 0x0000 );
5330 }
5331 else
5332 usc_OutDmaReg( info, BDCR, 0x2000 );
5333
5334 usc_stop_transmitter(info);
5335 usc_stop_receiver(info);
5336
5337 } /* end of usc_set_sdlc_mode() */
5338
5339 /* usc_enable_loopback()
5340 *
5341 * Set the 16C32 for internal loopback mode.
5342 * The TxCLK and RxCLK signals are generated from the BRG0 and
5343 * the TxD is looped back to the RxD internally.
5344 *
5345 * Arguments: info pointer to device instance data
5346 * enable 1 = enable loopback, 0 = disable
5347 * Return Value: None
5348 */
5349 void usc_enable_loopback(struct mgsl_struct *info, int enable)
5350 {
5351 if (enable) {
5352 /* blank external TXD output */
5353 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6));
5354
5355 /* Clock mode Control Register (CMCR)
5356 *
5357 * <15..14> 00 counter 1 Disabled
5358 * <13..12> 00 counter 0 Disabled
5359 * <11..10> 11 BRG1 Input is TxC Pin
5360 * <9..8> 11 BRG0 Input is TxC Pin
5361 * <7..6> 01 DPLL Input is BRG1 Output
5362 * <5..3> 100 TxCLK comes from BRG0
5363 * <2..0> 100 RxCLK comes from BRG0
5364 *
5365 * 0000 1111 0110 0100 = 0x0f64
5366 */
5367
5368 usc_OutReg( info, CMCR, 0x0f64 );
5369
5370 /* Write 16-bit Time Constant for BRG0 */
5371 /* use clock speed if available, otherwise use 8 for diagnostics */
5372 if (info->params.clock_speed) {
5373 if (info->bus_type == MGSL_BUS_TYPE_PCI)
5374 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5375 else
5376 usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5377 } else
5378 usc_OutReg(info, TC0R, (u16)8);
5379
5380 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5381 mode = Continuous Set Bit 0 to enable BRG0. */
5382 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5383
5384 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5385 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5386
5387 /* set Internal Data loopback mode */
5388 info->loopback_bits = 0x300;
5389 outw( 0x0300, info->io_base + CCAR );
5390 } else {
5391 /* enable external TXD output */
5392 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6));
5393
5394 /* clear Internal Data loopback mode */
5395 info->loopback_bits = 0;
5396 outw( 0,info->io_base + CCAR );
5397 }
5398
5399 } /* end of usc_enable_loopback() */
5400
5401 /* usc_enable_aux_clock()
5402 *
5403 * Enabled the AUX clock output at the specified frequency.
5404 *
5405 * Arguments:
5406 *
5407 * info pointer to device extension
5408 * data_rate data rate of clock in bits per second
5409 * A data rate of 0 disables the AUX clock.
5410 *
5411 * Return Value: None
5412 */
5413 void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5414 {
5415 u32 XtalSpeed;
5416 u16 Tc;
5417
5418 if ( data_rate ) {
5419 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5420 XtalSpeed = 11059200;
5421 else
5422 XtalSpeed = 14745600;
5423
5424
5425 /* Tc = (Xtal/Speed) - 1 */
5426 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5427 /* then rounding up gives a more precise time constant. Instead */
5428 /* of rounding up and then subtracting 1 we just don't subtract */
5429 /* the one in this case. */
5430
5431
5432 Tc = (u16)(XtalSpeed/data_rate);
5433 if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5434 Tc--;
5435
5436 /* Write 16-bit Time Constant for BRG0 */
5437 usc_OutReg( info, TC0R, Tc );
5438
5439 /*
5440 * Hardware Configuration Register (HCR)
5441 * Clear Bit 1, BRG0 mode = Continuous
5442 * Set Bit 0 to enable BRG0.
5443 */
5444
5445 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5446
5447 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5448 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5449 } else {
5450 /* data rate == 0 so turn off BRG0 */
5451 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5452 }
5453
5454 } /* end of usc_enable_aux_clock() */
5455
5456 /*
5457 *
5458 * usc_process_rxoverrun_sync()
5459 *
5460 * This function processes a receive overrun by resetting the
5461 * receive DMA buffers and issuing a Purge Rx FIFO command
5462 * to allow the receiver to continue receiving.
5463 *
5464 * Arguments:
5465 *
5466 * info pointer to device extension
5467 *
5468 * Return Value: None
5469 */
5470 void usc_process_rxoverrun_sync( struct mgsl_struct *info )
5471 {
5472 int start_index;
5473 int end_index;
5474 int frame_start_index;
5475 int start_of_frame_found = FALSE;
5476 int end_of_frame_found = FALSE;
5477 int reprogram_dma = FALSE;
5478
5479 DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
5480 u32 phys_addr;
5481
5482 usc_DmaCmd( info, DmaCmd_PauseRxChannel );
5483 usc_RCmd( info, RCmd_EnterHuntmode );
5484 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5485
5486 /* CurrentRxBuffer points to the 1st buffer of the next */
5487 /* possibly available receive frame. */
5488
5489 frame_start_index = start_index = end_index = info->current_rx_buffer;
5490
5491 /* Search for an unfinished string of buffers. This means */
5492 /* that a receive frame started (at least one buffer with */
5493 /* count set to zero) but there is no terminiting buffer */
5494 /* (status set to non-zero). */
5495
5496 while( !buffer_list[end_index].count )
5497 {
5498 /* Count field has been reset to zero by 16C32. */
5499 /* This buffer is currently in use. */
5500
5501 if ( !start_of_frame_found )
5502 {
5503 start_of_frame_found = TRUE;
5504 frame_start_index = end_index;
5505 end_of_frame_found = FALSE;
5506 }
5507
5508 if ( buffer_list[end_index].status )
5509 {
5510 /* Status field has been set by 16C32. */
5511 /* This is the last buffer of a received frame. */
5512
5513 /* We want to leave the buffers for this frame intact. */
5514 /* Move on to next possible frame. */
5515
5516 start_of_frame_found = FALSE;
5517 end_of_frame_found = TRUE;
5518 }
5519
5520 /* advance to next buffer entry in linked list */
5521 end_index++;
5522 if ( end_index == info->rx_buffer_count )
5523 end_index = 0;
5524
5525 if ( start_index == end_index )
5526 {
5527 /* The entire list has been searched with all Counts == 0 and */
5528 /* all Status == 0. The receive buffers are */
5529 /* completely screwed, reset all receive buffers! */
5530 mgsl_reset_rx_dma_buffers( info );
5531 frame_start_index = 0;
5532 start_of_frame_found = FALSE;
5533 reprogram_dma = TRUE;
5534 break;
5535 }
5536 }
5537
5538 if ( start_of_frame_found && !end_of_frame_found )
5539 {
5540 /* There is an unfinished string of receive DMA buffers */
5541 /* as a result of the receiver overrun. */
5542
5543 /* Reset the buffers for the unfinished frame */
5544 /* and reprogram the receive DMA controller to start */
5545 /* at the 1st buffer of unfinished frame. */
5546
5547 start_index = frame_start_index;
5548
5549 do
5550 {
5551 *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
5552
5553 /* Adjust index for wrap around. */
5554 if ( start_index == info->rx_buffer_count )
5555 start_index = 0;
5556
5557 } while( start_index != end_index );
5558
5559 reprogram_dma = TRUE;
5560 }
5561
5562 if ( reprogram_dma )
5563 {
5564 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
5565 usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5566 usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5567
5568 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5569
5570 /* This empties the receive FIFO and loads the RCC with RCLR */
5571 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5572
5573 /* program 16C32 with physical address of 1st DMA buffer entry */
5574 phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
5575 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5576 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5577
5578 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5579 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5580 usc_EnableInterrupts( info, RECEIVE_STATUS );
5581
5582 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5583 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5584
5585 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5586 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5587 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5588 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5589 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5590 else
5591 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5592 }
5593 else
5594 {
5595 /* This empties the receive FIFO and loads the RCC with RCLR */
5596 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5597 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5598 }
5599
5600 } /* end of usc_process_rxoverrun_sync() */
5601
5602 /* usc_stop_receiver()
5603 *
5604 * Disable USC receiver
5605 *
5606 * Arguments: info pointer to device instance data
5607 * Return Value: None
5608 */
5609 void usc_stop_receiver( struct mgsl_struct *info )
5610 {
5611 if (debug_level >= DEBUG_LEVEL_ISR)
5612 printk("%s(%d):usc_stop_receiver(%s)\n",
5613 __FILE__,__LINE__, info->device_name );
5614
5615 /* Disable receive DMA channel. */
5616 /* This also disables receive DMA channel interrupts */
5617 usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5618
5619 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5620 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5621 usc_DisableInterrupts( info, RECEIVE_DATA + RECEIVE_STATUS );
5622
5623 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5624
5625 /* This empties the receive FIFO and loads the RCC with RCLR */
5626 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5627 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5628
5629 info->rx_enabled = 0;
5630 info->rx_overflow = 0;
5631
5632 } /* end of stop_receiver() */
5633
5634 /* usc_start_receiver()
5635 *
5636 * Enable the USC receiver
5637 *
5638 * Arguments: info pointer to device instance data
5639 * Return Value: None
5640 */
5641 void usc_start_receiver( struct mgsl_struct *info )
5642 {
5643 u32 phys_addr;
5644
5645 if (debug_level >= DEBUG_LEVEL_ISR)
5646 printk("%s(%d):usc_start_receiver(%s)\n",
5647 __FILE__,__LINE__, info->device_name );
5648
5649 mgsl_reset_rx_dma_buffers( info );
5650 usc_stop_receiver( info );
5651
5652 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5653 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5654
5655 if ( info->params.mode == MGSL_MODE_HDLC ||
5656 info->params.mode == MGSL_MODE_RAW ) {
5657 /* DMA mode Transfers */
5658 /* Program the DMA controller. */
5659 /* Enable the DMA controller end of buffer interrupt. */
5660
5661 /* program 16C32 with physical address of 1st DMA buffer entry */
5662 phys_addr = info->rx_buffer_list[0].phys_entry;
5663 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5664 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5665
5666 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5667 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5668 usc_EnableInterrupts( info, RECEIVE_STATUS );
5669
5670 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5671 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5672
5673 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5674 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5675 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5676 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5677 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5678 else
5679 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5680 } else {
5681 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
5682 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
5683 usc_EnableInterrupts(info, RECEIVE_DATA);
5684
5685 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5686 usc_RCmd( info, RCmd_EnterHuntmode );
5687
5688 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5689 }
5690
5691 usc_OutReg( info, CCSR, 0x1020 );
5692
5693 info->rx_enabled = 1;
5694
5695 } /* end of usc_start_receiver() */
5696
5697 /* usc_start_transmitter()
5698 *
5699 * Enable the USC transmitter and send a transmit frame if
5700 * one is loaded in the DMA buffers.
5701 *
5702 * Arguments: info pointer to device instance data
5703 * Return Value: None
5704 */
5705 void usc_start_transmitter( struct mgsl_struct *info )
5706 {
5707 u32 phys_addr;
5708 unsigned int FrameSize;
5709
5710 if (debug_level >= DEBUG_LEVEL_ISR)
5711 printk("%s(%d):usc_start_transmitter(%s)\n",
5712 __FILE__,__LINE__, info->device_name );
5713
5714 if ( info->xmit_cnt ) {
5715
5716 /* If auto RTS enabled and RTS is inactive, then assert */
5717 /* RTS and set a flag indicating that the driver should */
5718 /* negate RTS when the transmission completes. */
5719
5720 info->drop_rts_on_tx_done = 0;
5721
5722 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5723 usc_get_serial_signals( info );
5724 if ( !(info->serial_signals & SerialSignal_RTS) ) {
5725 info->serial_signals |= SerialSignal_RTS;
5726 usc_set_serial_signals( info );
5727 info->drop_rts_on_tx_done = 1;
5728 }
5729 }
5730
5731
5732 if ( info->params.mode == MGSL_MODE_ASYNC ) {
5733 if ( !info->tx_active ) {
5734 usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5735 usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5736 usc_EnableInterrupts(info, TRANSMIT_DATA);
5737 usc_load_txfifo(info);
5738 }
5739 } else {
5740 /* Disable transmit DMA controller while programming. */
5741 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5742
5743 /* Transmit DMA buffer is loaded, so program USC */
5744 /* to send the frame contained in the buffers. */
5745
5746 FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
5747
5748 /* if operating in Raw sync mode, reset the rcc component
5749 * of the tx dma buffer entry, otherwise, the serial controller
5750 * will send a closing sync char after this count.
5751 */
5752 if ( info->params.mode == MGSL_MODE_RAW )
5753 info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
5754
5755 /* Program the Transmit Character Length Register (TCLR) */
5756 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5757 usc_OutReg( info, TCLR, (u16)FrameSize );
5758
5759 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5760
5761 /* Program the address of the 1st DMA Buffer Entry in linked list */
5762 phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
5763 usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5764 usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5765
5766 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5767 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5768 usc_EnableInterrupts( info, TRANSMIT_STATUS );
5769
5770 if ( info->params.mode == MGSL_MODE_RAW &&
5771 info->num_tx_dma_buffers > 1 ) {
5772 /* When running external sync mode, attempt to 'stream' transmit */
5773 /* by filling tx dma buffers as they become available. To do this */
5774 /* we need to enable Tx DMA EOB Status interrupts : */
5775 /* */
5776 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5777 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5778
5779 usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
5780 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
5781 }
5782
5783 /* Initialize Transmit DMA Channel */
5784 usc_DmaCmd( info, DmaCmd_InitTxChannel );
5785
5786 usc_TCmd( info, TCmd_SendFrame );
5787
5788 info->tx_timer.expires = jiffies + jiffies_from_ms(5000);
5789 add_timer(&info->tx_timer);
5790 }
5791 info->tx_active = 1;
5792 }
5793
5794 if ( !info->tx_enabled ) {
5795 info->tx_enabled = 1;
5796 if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5797 usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5798 else
5799 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5800 }
5801
5802 } /* end of usc_start_transmitter() */
5803
5804 /* usc_stop_transmitter()
5805 *
5806 * Stops the transmitter and DMA
5807 *
5808 * Arguments: info pointer to device isntance data
5809 * Return Value: None
5810 */
5811 void usc_stop_transmitter( struct mgsl_struct *info )
5812 {
5813 if (debug_level >= DEBUG_LEVEL_ISR)
5814 printk("%s(%d):usc_stop_transmitter(%s)\n",
5815 __FILE__,__LINE__, info->device_name );
5816
5817 del_timer(&info->tx_timer);
5818
5819 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5820 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5821 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5822
5823 usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5824 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5825 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5826
5827 info->tx_enabled = 0;
5828 info->tx_active = 0;
5829
5830 } /* end of usc_stop_transmitter() */
5831
5832 /* usc_load_txfifo()
5833 *
5834 * Fill the transmit FIFO until the FIFO is full or
5835 * there is no more data to load.
5836 *
5837 * Arguments: info pointer to device extension (instance data)
5838 * Return Value: None
5839 */
5840 void usc_load_txfifo( struct mgsl_struct *info )
5841 {
5842 int Fifocount;
5843 u8 TwoBytes[2];
5844
5845 if ( !info->xmit_cnt && !info->x_char )
5846 return;
5847
5848 /* Select transmit FIFO status readback in TICR */
5849 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5850
5851 /* load the Transmit FIFO until FIFOs full or all data sent */
5852
5853 while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5854 /* there is more space in the transmit FIFO and */
5855 /* there is more data in transmit buffer */
5856
5857 if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5858 /* write a 16-bit word from transmit buffer to 16C32 */
5859
5860 TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5861 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5862 TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5863 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5864
5865 outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5866
5867 info->xmit_cnt -= 2;
5868 info->icount.tx += 2;
5869 } else {
5870 /* only 1 byte left to transmit or 1 FIFO slot left */
5871
5872 outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5873 info->io_base + CCAR );
5874
5875 if (info->x_char) {
5876 /* transmit pending high priority char */
5877 outw( info->x_char,info->io_base + CCAR );
5878 info->x_char = 0;
5879 } else {
5880 outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5881 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5882 info->xmit_cnt--;
5883 }
5884 info->icount.tx++;
5885 }
5886 }
5887
5888 } /* end of usc_load_txfifo() */
5889
5890 /* usc_reset()
5891 *
5892 * Reset the adapter to a known state and prepare it for further use.
5893 *
5894 * Arguments: info pointer to device instance data
5895 * Return Value: None
5896 */
5897 void usc_reset( struct mgsl_struct *info )
5898 {
5899 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5900 int i;
5901 u32 readval;
5902
5903 /* Set BIT30 of Misc Control Register */
5904 /* (Local Control Register 0x50) to force reset of USC. */
5905
5906 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5907 u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5908
5909 info->misc_ctrl_value |= BIT30;
5910 *MiscCtrl = info->misc_ctrl_value;
5911
5912 /*
5913 * Force at least 170ns delay before clearing
5914 * reset bit. Each read from LCR takes at least
5915 * 30ns so 10 times for 300ns to be safe.
5916 */
5917 for(i=0;i<10;i++)
5918 readval = *MiscCtrl;
5919
5920 info->misc_ctrl_value &= ~BIT30;
5921 *MiscCtrl = info->misc_ctrl_value;
5922
5923 *LCR0BRDR = BUS_DESCRIPTOR(
5924 1, // Write Strobe Hold (0-3)
5925 2, // Write Strobe Delay (0-3)
5926 2, // Read Strobe Delay (0-3)
5927 0, // NWDD (Write data-data) (0-3)
5928 4, // NWAD (Write Addr-data) (0-31)
5929 0, // NXDA (Read/Write Data-Addr) (0-3)
5930 0, // NRDD (Read Data-Data) (0-3)
5931 5 // NRAD (Read Addr-Data) (0-31)
5932 );
5933 } else {
5934 /* do HW reset */
5935 outb( 0,info->io_base + 8 );
5936 }
5937
5938 info->mbre_bit = 0;
5939 info->loopback_bits = 0;
5940 info->usc_idle_mode = 0;
5941
5942 /*
5943 * Program the Bus Configuration Register (BCR)
5944 *
5945 * <15> 0 Don't use separate address
5946 * <14..6> 0 reserved
5947 * <5..4> 00 IAckmode = Default, don't care
5948 * <3> 1 Bus Request Totem Pole output
5949 * <2> 1 Use 16 Bit data bus
5950 * <1> 0 IRQ Totem Pole output
5951 * <0> 0 Don't Shift Right Addr
5952 *
5953 * 0000 0000 0000 1100 = 0x000c
5954 *
5955 * By writing to io_base + SDPIN the Wait/Ack pin is
5956 * programmed to work as a Wait pin.
5957 */
5958
5959 outw( 0x000c,info->io_base + SDPIN );
5960
5961
5962 outw( 0,info->io_base );
5963 outw( 0,info->io_base + CCAR );
5964
5965 /* select little endian byte ordering */
5966 usc_RTCmd( info, RTCmd_SelectLittleEndian );
5967
5968
5969 /* Port Control Register (PCR)
5970 *
5971 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5972 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5973 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5974 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5975 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5976 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5977 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5978 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5979 *
5980 * 1111 0000 1111 0101 = 0xf0f5
5981 */
5982
5983 usc_OutReg( info, PCR, 0xf0f5 );
5984
5985
5986 /*
5987 * Input/Output Control Register
5988 *
5989 * <15..14> 00 CTS is active low input
5990 * <13..12> 00 DCD is active low input
5991 * <11..10> 00 TxREQ pin is input (DSR)
5992 * <9..8> 00 RxREQ pin is input (RI)
5993 * <7..6> 00 TxD is output (Transmit Data)
5994 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5995 * <2..0> 100 RxC is Output (drive with BRG0)
5996 *
5997 * 0000 0000 0000 0100 = 0x0004
5998 */
5999
6000 usc_OutReg( info, IOCR, 0x0004 );
6001
6002 } /* end of usc_reset() */
6003
6004 /* usc_set_async_mode()
6005 *
6006 * Program adapter for asynchronous communications.
6007 *
6008 * Arguments: info pointer to device instance data
6009 * Return Value: None
6010 */
6011 void usc_set_async_mode( struct mgsl_struct *info )
6012 {
6013 u16 RegValue;
6014
6015 /* disable interrupts while programming USC */
6016 usc_DisableMasterIrqBit( info );
6017
6018 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
6019 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
6020
6021 usc_loopback_frame( info );
6022
6023 /* Channel mode Register (CMR)
6024 *
6025 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
6026 * <13..12> 00 00 = 16X Clock
6027 * <11..8> 0000 Transmitter mode = Asynchronous
6028 * <7..6> 00 reserved?
6029 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
6030 * <3..0> 0000 Receiver mode = Asynchronous
6031 *
6032 * 0000 0000 0000 0000 = 0x0
6033 */
6034
6035 RegValue = 0;
6036 if ( info->params.stop_bits != 1 )
6037 RegValue |= BIT14;
6038 usc_OutReg( info, CMR, RegValue );
6039
6040
6041 /* Receiver mode Register (RMR)
6042 *
6043 * <15..13> 000 encoding = None
6044 * <12..08> 00000 reserved (Sync Only)
6045 * <7..6> 00 Even parity
6046 * <5> 0 parity disabled
6047 * <4..2> 000 Receive Char Length = 8 bits
6048 * <1..0> 00 Disable Receiver
6049 *
6050 * 0000 0000 0000 0000 = 0x0
6051 */
6052
6053 RegValue = 0;
6054
6055 if ( info->params.data_bits != 8 )
6056 RegValue |= BIT4+BIT3+BIT2;
6057
6058 if ( info->params.parity != ASYNC_PARITY_NONE ) {
6059 RegValue |= BIT5;
6060 if ( info->params.parity != ASYNC_PARITY_ODD )
6061 RegValue |= BIT6;
6062 }
6063
6064 usc_OutReg( info, RMR, RegValue );
6065
6066
6067 /* Set IRQ trigger level */
6068
6069 usc_RCmd( info, RCmd_SelectRicrIntLevel );
6070
6071
6072 /* Receive Interrupt Control Register (RICR)
6073 *
6074 * <15..8> ? RxFIFO IRQ Request Level
6075 *
6076 * Note: For async mode the receive FIFO level must be set
6077 * to 0 to aviod the situation where the FIFO contains fewer bytes
6078 * than the trigger level and no more data is expected.
6079 *
6080 * <7> 0 Exited Hunt IA (Interrupt Arm)
6081 * <6> 0 Idle Received IA
6082 * <5> 0 Break/Abort IA
6083 * <4> 0 Rx Bound IA
6084 * <3> 0 Queued status reflects oldest byte in FIFO
6085 * <2> 0 Abort/PE IA
6086 * <1> 0 Rx Overrun IA
6087 * <0> 0 Select TC0 value for readback
6088 *
6089 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
6090 */
6091
6092 usc_OutReg( info, RICR, 0x0000 );
6093
6094 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
6095 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
6096
6097
6098 /* Transmit mode Register (TMR)
6099 *
6100 * <15..13> 000 encoding = None
6101 * <12..08> 00000 reserved (Sync Only)
6102 * <7..6> 00 Transmit parity Even
6103 * <5> 0 Transmit parity Disabled
6104 * <4..2> 000 Tx Char Length = 8 bits
6105 * <1..0> 00 Disable Transmitter
6106 *
6107 * 0000 0000 0000 0000 = 0x0
6108 */
6109
6110 RegValue = 0;
6111
6112 if ( info->params.data_bits != 8 )
6113 RegValue |= BIT4+BIT3+BIT2;
6114
6115 if ( info->params.parity != ASYNC_PARITY_NONE ) {
6116 RegValue |= BIT5;
6117 if ( info->params.parity != ASYNC_PARITY_ODD )
6118 RegValue |= BIT6;
6119 }
6120
6121 usc_OutReg( info, TMR, RegValue );
6122
6123 usc_set_txidle( info );
6124
6125
6126 /* Set IRQ trigger level */
6127
6128 usc_TCmd( info, TCmd_SelectTicrIntLevel );
6129
6130
6131 /* Transmit Interrupt Control Register (TICR)
6132 *
6133 * <15..8> ? Transmit FIFO IRQ Level
6134 * <7> 0 Present IA (Interrupt Arm)
6135 * <6> 1 Idle Sent IA
6136 * <5> 0 Abort Sent IA
6137 * <4> 0 EOF/EOM Sent IA
6138 * <3> 0 CRC Sent IA
6139 * <2> 0 1 = Wait for SW Trigger to Start Frame
6140 * <1> 0 Tx Underrun IA
6141 * <0> 0 TC0 constant on read back
6142 *
6143 * 0000 0000 0100 0000 = 0x0040
6144 */
6145
6146 usc_OutReg( info, TICR, 0x1f40 );
6147
6148 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
6149 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
6150
6151 usc_enable_async_clock( info, info->params.data_rate );
6152
6153
6154 /* Channel Control/status Register (CCSR)
6155 *
6156 * <15> X RCC FIFO Overflow status (RO)
6157 * <14> X RCC FIFO Not Empty status (RO)
6158 * <13> 0 1 = Clear RCC FIFO (WO)
6159 * <12> X DPLL in Sync status (RO)
6160 * <11> X DPLL 2 Missed Clocks status (RO)
6161 * <10> X DPLL 1 Missed Clock status (RO)
6162 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6163 * <7> X SDLC Loop On status (RO)
6164 * <6> X SDLC Loop Send status (RO)
6165 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6166 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6167 * <1..0> 00 reserved
6168 *
6169 * 0000 0000 0010 0000 = 0x0020
6170 */
6171
6172 usc_OutReg( info, CCSR, 0x0020 );
6173
6174 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6175 RECEIVE_DATA + RECEIVE_STATUS );
6176
6177 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6178 RECEIVE_DATA + RECEIVE_STATUS );
6179
6180 usc_EnableMasterIrqBit( info );
6181
6182 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6183 /* Enable INTEN (Port 6, Bit12) */
6184 /* This connects the IRQ request signal to the ISA bus */
6185 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6186 }
6187
6188 } /* end of usc_set_async_mode() */
6189
6190 /* usc_loopback_frame()
6191 *
6192 * Loop back a small (2 byte) dummy SDLC frame.
6193 * Interrupts and DMA are NOT used. The purpose of this is to
6194 * clear any 'stale' status info left over from running in async mode.
6195 *
6196 * The 16C32 shows the strange behaviour of marking the 1st
6197 * received SDLC frame with a CRC error even when there is no
6198 * CRC error. To get around this a small dummy from of 2 bytes
6199 * is looped back when switching from async to sync mode.
6200 *
6201 * Arguments: info pointer to device instance data
6202 * Return Value: None
6203 */
6204 void usc_loopback_frame( struct mgsl_struct *info )
6205 {
6206 int i;
6207 unsigned long oldmode = info->params.mode;
6208
6209 info->params.mode = MGSL_MODE_HDLC;
6210
6211 usc_DisableMasterIrqBit( info );
6212
6213 usc_set_sdlc_mode( info );
6214 usc_enable_loopback( info, 1 );
6215
6216 /* Write 16-bit Time Constant for BRG0 */
6217 usc_OutReg( info, TC0R, 0 );
6218
6219 /* Channel Control Register (CCR)
6220 *
6221 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6222 * <13> 0 Trigger Tx on SW Command Disabled
6223 * <12> 0 Flag Preamble Disabled
6224 * <11..10> 00 Preamble Length = 8-Bits
6225 * <9..8> 01 Preamble Pattern = flags
6226 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6227 * <5> 0 Trigger Rx on SW Command Disabled
6228 * <4..0> 0 reserved
6229 *
6230 * 0000 0001 0000 0000 = 0x0100
6231 */
6232
6233 usc_OutReg( info, CCR, 0x0100 );
6234
6235 /* SETUP RECEIVER */
6236 usc_RTCmd( info, RTCmd_PurgeRxFifo );
6237 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
6238
6239 /* SETUP TRANSMITTER */
6240 /* Program the Transmit Character Length Register (TCLR) */
6241 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6242 usc_OutReg( info, TCLR, 2 );
6243 usc_RTCmd( info, RTCmd_PurgeTxFifo );
6244
6245 /* unlatch Tx status bits, and start transmit channel. */
6246 usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
6247 outw(0,info->io_base + DATAREG);
6248
6249 /* ENABLE TRANSMITTER */
6250 usc_TCmd( info, TCmd_SendFrame );
6251 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
6252
6253 /* WAIT FOR RECEIVE COMPLETE */
6254 for (i=0 ; i<1000 ; i++)
6255 if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
6256 break;
6257
6258 /* clear Internal Data loopback mode */
6259 usc_enable_loopback(info, 0);
6260
6261 usc_EnableMasterIrqBit(info);
6262
6263 info->params.mode = oldmode;
6264
6265 } /* end of usc_loopback_frame() */
6266
6267 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6268 *
6269 * Arguments: info pointer to adapter info structure
6270 * Return Value: None
6271 */
6272 void usc_set_sync_mode( struct mgsl_struct *info )
6273 {
6274 usc_loopback_frame( info );
6275 usc_set_sdlc_mode( info );
6276
6277 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6278 /* Enable INTEN (Port 6, Bit12) */
6279 /* This connects the IRQ request signal to the ISA bus */
6280 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6281 }
6282
6283 usc_enable_aux_clock(info, info->params.clock_speed);
6284
6285 if (info->params.loopback)
6286 usc_enable_loopback(info,1);
6287
6288 } /* end of mgsl_set_sync_mode() */
6289
6290 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6291 *
6292 * Arguments: info pointer to device instance data
6293 * Return Value: None
6294 */
6295 void usc_set_txidle( struct mgsl_struct *info )
6296 {
6297 u16 usc_idle_mode = IDLEMODE_FLAGS;
6298
6299 /* Map API idle mode to USC register bits */
6300
6301 switch( info->idle_mode ){
6302 case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
6303 case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
6304 case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
6305 case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
6306 case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
6307 case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
6308 case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
6309 }
6310
6311 info->usc_idle_mode = usc_idle_mode;
6312 //usc_OutReg(info, TCSR, usc_idle_mode);
6313 info->tcsr_value &= ~IDLEMODE_MASK; /* clear idle mode bits */
6314 info->tcsr_value += usc_idle_mode;
6315 usc_OutReg(info, TCSR, info->tcsr_value);
6316
6317 /*
6318 * if SyncLink WAN adapter is running in external sync mode, the
6319 * transmitter has been set to Monosync in order to try to mimic
6320 * a true raw outbound bit stream. Monosync still sends an open/close
6321 * sync char at the start/end of a frame. Try to match those sync
6322 * patterns to the idle mode set here
6323 */
6324 if ( info->params.mode == MGSL_MODE_RAW ) {
6325 unsigned char syncpat = 0;
6326 switch( info->idle_mode ) {
6327 case HDLC_TXIDLE_FLAGS:
6328 syncpat = 0x7e;
6329 break;
6330 case HDLC_TXIDLE_ALT_ZEROS_ONES:
6331 syncpat = 0x55;
6332 break;
6333 case HDLC_TXIDLE_ZEROS:
6334 case HDLC_TXIDLE_SPACE:
6335 syncpat = 0x00;
6336 break;
6337 case HDLC_TXIDLE_ONES:
6338 case HDLC_TXIDLE_MARK:
6339 syncpat = 0xff;
6340 break;
6341 case HDLC_TXIDLE_ALT_MARK_SPACE:
6342 syncpat = 0xaa;
6343 break;
6344 }
6345
6346 usc_SetTransmitSyncChars(info,syncpat,syncpat);
6347 }
6348
6349 } /* end of usc_set_txidle() */
6350
6351 /* usc_get_serial_signals()
6352 *
6353 * Query the adapter for the state of the V24 status (input) signals.
6354 *
6355 * Arguments: info pointer to device instance data
6356 * Return Value: None
6357 */
6358 void usc_get_serial_signals( struct mgsl_struct *info )
6359 {
6360 u16 status;
6361
6362 /* clear all serial signals except DTR and RTS */
6363 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
6364
6365 /* Read the Misc Interrupt status Register (MISR) to get */
6366 /* the V24 status signals. */
6367
6368 status = usc_InReg( info, MISR );
6369
6370 /* set serial signal bits to reflect MISR */
6371
6372 if ( status & MISCSTATUS_CTS )
6373 info->serial_signals |= SerialSignal_CTS;
6374
6375 if ( status & MISCSTATUS_DCD )
6376 info->serial_signals |= SerialSignal_DCD;
6377
6378 if ( status & MISCSTATUS_RI )
6379 info->serial_signals |= SerialSignal_RI;
6380
6381 if ( status & MISCSTATUS_DSR )
6382 info->serial_signals |= SerialSignal_DSR;
6383
6384 } /* end of usc_get_serial_signals() */
6385
6386 /* usc_set_serial_signals()
6387 *
6388 * Set the state of DTR and RTS based on contents of
6389 * serial_signals member of device extension.
6390 *
6391 * Arguments: info pointer to device instance data
6392 * Return Value: None
6393 */
6394 void usc_set_serial_signals( struct mgsl_struct *info )
6395 {
6396 u16 Control;
6397 unsigned char V24Out = info->serial_signals;
6398
6399 /* get the current value of the Port Control Register (PCR) */
6400
6401 Control = usc_InReg( info, PCR );
6402
6403 if ( V24Out & SerialSignal_RTS )
6404 Control &= ~(BIT6);
6405 else
6406 Control |= BIT6;
6407
6408 if ( V24Out & SerialSignal_DTR )
6409 Control &= ~(BIT4);
6410 else
6411 Control |= BIT4;
6412
6413 usc_OutReg( info, PCR, Control );
6414
6415 } /* end of usc_set_serial_signals() */
6416
6417 /* usc_enable_async_clock()
6418 *
6419 * Enable the async clock at the specified frequency.
6420 *
6421 * Arguments: info pointer to device instance data
6422 * data_rate data rate of clock in bps
6423 * 0 disables the AUX clock.
6424 * Return Value: None
6425 */
6426 void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
6427 {
6428 if ( data_rate ) {
6429 /*
6430 * Clock mode Control Register (CMCR)
6431 *
6432 * <15..14> 00 counter 1 Disabled
6433 * <13..12> 00 counter 0 Disabled
6434 * <11..10> 11 BRG1 Input is TxC Pin
6435 * <9..8> 11 BRG0 Input is TxC Pin
6436 * <7..6> 01 DPLL Input is BRG1 Output
6437 * <5..3> 100 TxCLK comes from BRG0
6438 * <2..0> 100 RxCLK comes from BRG0
6439 *
6440 * 0000 1111 0110 0100 = 0x0f64
6441 */
6442
6443 usc_OutReg( info, CMCR, 0x0f64 );
6444
6445
6446 /*
6447 * Write 16-bit Time Constant for BRG0
6448 * Time Constant = (ClkSpeed / data_rate) - 1
6449 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6450 */
6451
6452 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6453 usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6454 else
6455 usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6456
6457
6458 /*
6459 * Hardware Configuration Register (HCR)
6460 * Clear Bit 1, BRG0 mode = Continuous
6461 * Set Bit 0 to enable BRG0.
6462 */
6463
6464 usc_OutReg( info, HCR,
6465 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6466
6467
6468 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6469
6470 usc_OutReg( info, IOCR,
6471 (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
6472 } else {
6473 /* data rate == 0 so turn off BRG0 */
6474 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
6475 }
6476
6477 } /* end of usc_enable_async_clock() */
6478
6479 /*
6480 * Buffer Structures:
6481 *
6482 * Normal memory access uses virtual addresses that can make discontiguous
6483 * physical memory pages appear to be contiguous in the virtual address
6484 * space (the processors memory mapping handles the conversions).
6485 *
6486 * DMA transfers require physically contiguous memory. This is because
6487 * the DMA system controller and DMA bus masters deal with memory using
6488 * only physical addresses.
6489 *
6490 * This causes a problem under Windows NT when large DMA buffers are
6491 * needed. Fragmentation of the nonpaged pool prevents allocations of
6492 * physically contiguous buffers larger than the PAGE_SIZE.
6493 *
6494 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6495 * allows DMA transfers to physically discontiguous buffers. Information
6496 * about each data transfer buffer is contained in a memory structure
6497 * called a 'buffer entry'. A list of buffer entries is maintained
6498 * to track and control the use of the data transfer buffers.
6499 *
6500 * To support this strategy we will allocate sufficient PAGE_SIZE
6501 * contiguous memory buffers to allow for the total required buffer
6502 * space.
6503 *
6504 * The 16C32 accesses the list of buffer entries using Bus Master
6505 * DMA. Control information is read from the buffer entries by the
6506 * 16C32 to control data transfers. status information is written to
6507 * the buffer entries by the 16C32 to indicate the status of completed
6508 * transfers.
6509 *
6510 * The CPU writes control information to the buffer entries to control
6511 * the 16C32 and reads status information from the buffer entries to
6512 * determine information about received and transmitted frames.
6513 *
6514 * Because the CPU and 16C32 (adapter) both need simultaneous access
6515 * to the buffer entries, the buffer entry memory is allocated with
6516 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6517 * entry list to PAGE_SIZE.
6518 *
6519 * The actual data buffers on the other hand will only be accessed
6520 * by the CPU or the adapter but not by both simultaneously. This allows
6521 * Scatter/Gather packet based DMA procedures for using physically
6522 * discontiguous pages.
6523 */
6524
6525 /*
6526 * mgsl_reset_tx_dma_buffers()
6527 *
6528 * Set the count for all transmit buffers to 0 to indicate the
6529 * buffer is available for use and set the current buffer to the
6530 * first buffer. This effectively makes all buffers free and
6531 * discards any data in buffers.
6532 *
6533 * Arguments: info pointer to device instance data
6534 * Return Value: None
6535 */
6536 void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
6537 {
6538 unsigned int i;
6539
6540 for ( i = 0; i < info->tx_buffer_count; i++ ) {
6541 *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
6542 }
6543
6544 info->current_tx_buffer = 0;
6545 info->start_tx_dma_buffer = 0;
6546 info->tx_dma_buffers_used = 0;
6547
6548 info->get_tx_holding_index = 0;
6549 info->put_tx_holding_index = 0;
6550 info->tx_holding_count = 0;
6551
6552 } /* end of mgsl_reset_tx_dma_buffers() */
6553
6554 /*
6555 * num_free_tx_dma_buffers()
6556 *
6557 * returns the number of free tx dma buffers available
6558 *
6559 * Arguments: info pointer to device instance data
6560 * Return Value: number of free tx dma buffers
6561 */
6562 int num_free_tx_dma_buffers(struct mgsl_struct *info)
6563 {
6564 return info->tx_buffer_count - info->tx_dma_buffers_used;
6565 }
6566
6567 /*
6568 * mgsl_reset_rx_dma_buffers()
6569 *
6570 * Set the count for all receive buffers to DMABUFFERSIZE
6571 * and set the current buffer to the first buffer. This effectively
6572 * makes all buffers free and discards any data in buffers.
6573 *
6574 * Arguments: info pointer to device instance data
6575 * Return Value: None
6576 */
6577 void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
6578 {
6579 unsigned int i;
6580
6581 for ( i = 0; i < info->rx_buffer_count; i++ ) {
6582 *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
6583 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6584 // info->rx_buffer_list[i].status = 0;
6585 }
6586
6587 info->current_rx_buffer = 0;
6588
6589 } /* end of mgsl_reset_rx_dma_buffers() */
6590
6591 /*
6592 * mgsl_free_rx_frame_buffers()
6593 *
6594 * Free the receive buffers used by a received SDLC
6595 * frame such that the buffers can be reused.
6596 *
6597 * Arguments:
6598 *
6599 * info pointer to device instance data
6600 * StartIndex index of 1st receive buffer of frame
6601 * EndIndex index of last receive buffer of frame
6602 *
6603 * Return Value: None
6604 */
6605 void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
6606 {
6607 int Done = 0;
6608 DMABUFFERENTRY *pBufEntry;
6609 unsigned int Index;
6610
6611 /* Starting with 1st buffer entry of the frame clear the status */
6612 /* field and set the count field to DMA Buffer Size. */
6613
6614 Index = StartIndex;
6615
6616 while( !Done ) {
6617 pBufEntry = &(info->rx_buffer_list[Index]);
6618
6619 if ( Index == EndIndex ) {
6620 /* This is the last buffer of the frame! */
6621 Done = 1;
6622 }
6623
6624 /* reset current buffer for reuse */
6625 // pBufEntry->status = 0;
6626 // pBufEntry->count = DMABUFFERSIZE;
6627 *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
6628
6629 /* advance to next buffer entry in linked list */
6630 Index++;
6631 if ( Index == info->rx_buffer_count )
6632 Index = 0;
6633 }
6634
6635 /* set current buffer to next buffer after last buffer of frame */
6636 info->current_rx_buffer = Index;
6637
6638 } /* end of free_rx_frame_buffers() */
6639
6640 /* mgsl_get_rx_frame()
6641 *
6642 * This function attempts to return a received SDLC frame from the
6643 * receive DMA buffers. Only frames received without errors are returned.
6644 *
6645 * Arguments: info pointer to device extension
6646 * Return Value: 1 if frame returned, otherwise 0
6647 */
6648 int mgsl_get_rx_frame(struct mgsl_struct *info)
6649 {
6650 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
6651 unsigned short status;
6652 DMABUFFERENTRY *pBufEntry;
6653 unsigned int framesize = 0;
6654 int ReturnCode = 0;
6655 unsigned long flags;
6656 struct tty_struct *tty = info->tty;
6657 int return_frame = 0;
6658
6659 /*
6660 * current_rx_buffer points to the 1st buffer of the next available
6661 * receive frame. To find the last buffer of the frame look for
6662 * a non-zero status field in the buffer entries. (The status
6663 * field is set by the 16C32 after completing a receive frame.
6664 */
6665
6666 StartIndex = EndIndex = info->current_rx_buffer;
6667
6668 while( !info->rx_buffer_list[EndIndex].status ) {
6669 /*
6670 * If the count field of the buffer entry is non-zero then
6671 * this buffer has not been used. (The 16C32 clears the count
6672 * field when it starts using the buffer.) If an unused buffer
6673 * is encountered then there are no frames available.
6674 */
6675
6676 if ( info->rx_buffer_list[EndIndex].count )
6677 goto Cleanup;
6678
6679 /* advance to next buffer entry in linked list */
6680 EndIndex++;
6681 if ( EndIndex == info->rx_buffer_count )
6682 EndIndex = 0;
6683
6684 /* if entire list searched then no frame available */
6685 if ( EndIndex == StartIndex ) {
6686 /* If this occurs then something bad happened,
6687 * all buffers have been 'used' but none mark
6688 * the end of a frame. Reset buffers and receiver.
6689 */
6690
6691 if ( info->rx_enabled ){
6692 spin_lock_irqsave(&info->irq_spinlock,flags);
6693 usc_start_receiver(info);
6694 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6695 }
6696 goto Cleanup;
6697 }
6698 }
6699
6700
6701 /* check status of receive frame */
6702
6703 status = info->rx_buffer_list[EndIndex].status;
6704
6705 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6706 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6707 if ( status & RXSTATUS_SHORT_FRAME )
6708 info->icount.rxshort++;
6709 else if ( status & RXSTATUS_ABORT )
6710 info->icount.rxabort++;
6711 else if ( status & RXSTATUS_OVERRUN )
6712 info->icount.rxover++;
6713 else {
6714 info->icount.rxcrc++;
6715 if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
6716 return_frame = 1;
6717 }
6718 framesize = 0;
6719 #ifdef CONFIG_SYNCLINK_SYNCPPP
6720 info->netstats.rx_errors++;
6721 info->netstats.rx_frame_errors++;
6722 #endif
6723 } else
6724 return_frame = 1;
6725
6726 if ( return_frame ) {
6727 /* receive frame has no errors, get frame size.
6728 * The frame size is the starting value of the RCC (which was
6729 * set to 0xffff) minus the ending value of the RCC (decremented
6730 * once for each receive character) minus 2 for the 16-bit CRC.
6731 */
6732
6733 framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
6734
6735 /* adjust frame size for CRC if any */
6736 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
6737 framesize -= 2;
6738 else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
6739 framesize -= 4;
6740 }
6741
6742 if ( debug_level >= DEBUG_LEVEL_BH )
6743 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6744 __FILE__,__LINE__,info->device_name,status,framesize);
6745
6746 if ( debug_level >= DEBUG_LEVEL_DATA )
6747 mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
6748 MIN(framesize,DMABUFFERSIZE),0);
6749
6750 if (framesize) {
6751 if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
6752 ((framesize+1) > info->max_frame_size) ) ||
6753 (framesize > info->max_frame_size) )
6754 info->icount.rxlong++;
6755 else {
6756 /* copy dma buffer(s) to contiguous intermediate buffer */
6757 int copy_count = framesize;
6758 int index = StartIndex;
6759 unsigned char *ptmp = info->intermediate_rxbuffer;
6760
6761 if ( !(status & RXSTATUS_CRC_ERROR))
6762 info->icount.rxok++;
6763
6764 while(copy_count) {
6765 int partial_count;
6766 if ( copy_count > DMABUFFERSIZE )
6767 partial_count = DMABUFFERSIZE;
6768 else
6769 partial_count = copy_count;
6770
6771 pBufEntry = &(info->rx_buffer_list[index]);
6772 memcpy( ptmp, pBufEntry->virt_addr, partial_count );
6773 ptmp += partial_count;
6774 copy_count -= partial_count;
6775
6776 if ( ++index == info->rx_buffer_count )
6777 index = 0;
6778 }
6779
6780 if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
6781 ++framesize;
6782 *ptmp = (status & RXSTATUS_CRC_ERROR ?
6783 RX_CRC_ERROR :
6784 RX_OK);
6785
6786 if ( debug_level >= DEBUG_LEVEL_DATA )
6787 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6788 __FILE__,__LINE__,info->device_name,
6789 *ptmp);
6790 }
6791
6792 #ifdef CONFIG_SYNCLINK_SYNCPPP
6793 if (info->netcount) {
6794 /* pass frame to syncppp device */
6795 mgsl_sppp_rx_done(info,info->intermediate_rxbuffer,framesize);
6796 }
6797 else
6798 #endif
6799 {
6800 /* Call the line discipline receive callback directly. */
6801 if ( tty && tty->ldisc.receive_buf )
6802 tty->ldisc.receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6803 }
6804 }
6805 }
6806 /* Free the buffers used by this frame. */
6807 mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
6808
6809 ReturnCode = 1;
6810
6811 Cleanup:
6812
6813 if ( info->rx_enabled && info->rx_overflow ) {
6814 /* The receiver needs to restarted because of
6815 * a receive overflow (buffer or FIFO). If the
6816 * receive buffers are now empty, then restart receiver.
6817 */
6818
6819 if ( !info->rx_buffer_list[EndIndex].status &&
6820 info->rx_buffer_list[EndIndex].count ) {
6821 spin_lock_irqsave(&info->irq_spinlock,flags);
6822 usc_start_receiver(info);
6823 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6824 }
6825 }
6826
6827 return ReturnCode;
6828
6829 } /* end of mgsl_get_rx_frame() */
6830
6831 /* mgsl_get_raw_rx_frame()
6832 *
6833 * This function attempts to return a received frame from the
6834 * receive DMA buffers when running in external loop mode. In this mode,
6835 * we will return at most one DMABUFFERSIZE frame to the application.
6836 * The USC receiver is triggering off of DCD going active to start a new
6837 * frame, and DCD going inactive to terminate the frame (similar to
6838 * processing a closing flag character).
6839 *
6840 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6841 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6842 * status field and the RCC field will indicate the length of the
6843 * entire received frame. We take this RCC field and get the modulus
6844 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6845 * last Rx DMA buffer and return that last portion of the frame.
6846 *
6847 * Arguments: info pointer to device extension
6848 * Return Value: 1 if frame returned, otherwise 0
6849 */
6850 int mgsl_get_raw_rx_frame(struct mgsl_struct *info)
6851 {
6852 unsigned int CurrentIndex, NextIndex;
6853 unsigned short status;
6854 DMABUFFERENTRY *pBufEntry;
6855 unsigned int framesize = 0;
6856 int ReturnCode = 0;
6857 unsigned long flags;
6858 struct tty_struct *tty = info->tty;
6859
6860 /*
6861 * current_rx_buffer points to the 1st buffer of the next available
6862 * receive frame. The status field is set by the 16C32 after
6863 * completing a receive frame. If the status field of this buffer
6864 * is zero, either the USC is still filling this buffer or this
6865 * is one of a series of buffers making up a received frame.
6866 *
6867 * If the count field of this buffer is zero, the USC is either
6868 * using this buffer or has used this buffer. Look at the count
6869 * field of the next buffer. If that next buffer's count is
6870 * non-zero, the USC is still actively using the current buffer.
6871 * Otherwise, if the next buffer's count field is zero, the
6872 * current buffer is complete and the USC is using the next
6873 * buffer.
6874 */
6875 CurrentIndex = NextIndex = info->current_rx_buffer;
6876 ++NextIndex;
6877 if ( NextIndex == info->rx_buffer_count )
6878 NextIndex = 0;
6879
6880 if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
6881 (info->rx_buffer_list[CurrentIndex].count == 0 &&
6882 info->rx_buffer_list[NextIndex].count == 0)) {
6883 /*
6884 * Either the status field of this dma buffer is non-zero
6885 * (indicating the last buffer of a receive frame) or the next
6886 * buffer is marked as in use -- implying this buffer is complete
6887 * and an intermediate buffer for this received frame.
6888 */
6889
6890 status = info->rx_buffer_list[CurrentIndex].status;
6891
6892 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6893 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6894 if ( status & RXSTATUS_SHORT_FRAME )
6895 info->icount.rxshort++;
6896 else if ( status & RXSTATUS_ABORT )
6897 info->icount.rxabort++;
6898 else if ( status & RXSTATUS_OVERRUN )
6899 info->icount.rxover++;
6900 else
6901 info->icount.rxcrc++;
6902 framesize = 0;
6903 } else {
6904 /*
6905 * A receive frame is available, get frame size and status.
6906 *
6907 * The frame size is the starting value of the RCC (which was
6908 * set to 0xffff) minus the ending value of the RCC (decremented
6909 * once for each receive character) minus 2 or 4 for the 16-bit
6910 * or 32-bit CRC.
6911 *
6912 * If the status field is zero, this is an intermediate buffer.
6913 * It's size is 4K.
6914 *
6915 * If the DMA Buffer Entry's Status field is non-zero, the
6916 * receive operation completed normally (ie: DCD dropped). The
6917 * RCC field is valid and holds the received frame size.
6918 * It is possible that the RCC field will be zero on a DMA buffer
6919 * entry with a non-zero status. This can occur if the total
6920 * frame size (number of bytes between the time DCD goes active
6921 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6922 * case the 16C32 has underrun on the RCC count and appears to
6923 * stop updating this counter to let us know the actual received
6924 * frame size. If this happens (non-zero status and zero RCC),
6925 * simply return the entire RxDMA Buffer
6926 */
6927 if ( status ) {
6928 /*
6929 * In the event that the final RxDMA Buffer is
6930 * terminated with a non-zero status and the RCC
6931 * field is zero, we interpret this as the RCC
6932 * having underflowed (received frame > 65535 bytes).
6933 *
6934 * Signal the event to the user by passing back
6935 * a status of RxStatus_CrcError returning the full
6936 * buffer and let the app figure out what data is
6937 * actually valid
6938 */
6939 if ( info->rx_buffer_list[CurrentIndex].rcc )
6940 framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
6941 else
6942 framesize = DMABUFFERSIZE;
6943 }
6944 else
6945 framesize = DMABUFFERSIZE;
6946 }
6947
6948 if ( framesize > DMABUFFERSIZE ) {
6949 /*
6950 * if running in raw sync mode, ISR handler for
6951 * End Of Buffer events terminates all buffers at 4K.
6952 * If this frame size is said to be >4K, get the
6953 * actual number of bytes of the frame in this buffer.
6954 */
6955 framesize = framesize % DMABUFFERSIZE;
6956 }
6957
6958
6959 if ( debug_level >= DEBUG_LEVEL_BH )
6960 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6961 __FILE__,__LINE__,info->device_name,status,framesize);
6962
6963 if ( debug_level >= DEBUG_LEVEL_DATA )
6964 mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
6965 MIN(framesize,DMABUFFERSIZE),0);
6966
6967 if (framesize) {
6968 /* copy dma buffer(s) to contiguous intermediate buffer */
6969 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6970
6971 pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
6972 memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
6973 info->icount.rxok++;
6974
6975 /* Call the line discipline receive callback directly. */
6976 if ( tty && tty->ldisc.receive_buf )
6977 tty->ldisc.receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6978 }
6979
6980 /* Free the buffers used by this frame. */
6981 mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
6982
6983 ReturnCode = 1;
6984 }
6985
6986
6987 if ( info->rx_enabled && info->rx_overflow ) {
6988 /* The receiver needs to restarted because of
6989 * a receive overflow (buffer or FIFO). If the
6990 * receive buffers are now empty, then restart receiver.
6991 */
6992
6993 if ( !info->rx_buffer_list[CurrentIndex].status &&
6994 info->rx_buffer_list[CurrentIndex].count ) {
6995 spin_lock_irqsave(&info->irq_spinlock,flags);
6996 usc_start_receiver(info);
6997 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6998 }
6999 }
7000
7001 return ReturnCode;
7002
7003 } /* end of mgsl_get_raw_rx_frame() */
7004
7005 /* mgsl_load_tx_dma_buffer()
7006 *
7007 * Load the transmit DMA buffer with the specified data.
7008 *
7009 * Arguments:
7010 *
7011 * info pointer to device extension
7012 * Buffer pointer to buffer containing frame to load
7013 * BufferSize size in bytes of frame in Buffer
7014 *
7015 * Return Value: None
7016 */
7017 void mgsl_load_tx_dma_buffer(struct mgsl_struct *info, const char *Buffer,
7018 unsigned int BufferSize)
7019 {
7020 unsigned short Copycount;
7021 unsigned int i = 0;
7022 DMABUFFERENTRY *pBufEntry;
7023
7024 if ( debug_level >= DEBUG_LEVEL_DATA )
7025 mgsl_trace_block(info,Buffer, MIN(BufferSize,DMABUFFERSIZE), 1);
7026
7027 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7028 /* set CMR:13 to start transmit when
7029 * next GoAhead (abort) is received
7030 */
7031 info->cmr_value |= BIT13;
7032 }
7033
7034 /* begin loading the frame in the next available tx dma
7035 * buffer, remember it's starting location for setting
7036 * up tx dma operation
7037 */
7038 i = info->current_tx_buffer;
7039 info->start_tx_dma_buffer = i;
7040
7041 /* Setup the status and RCC (Frame Size) fields of the 1st */
7042 /* buffer entry in the transmit DMA buffer list. */
7043
7044 info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
7045 info->tx_buffer_list[i].rcc = BufferSize;
7046 info->tx_buffer_list[i].count = BufferSize;
7047
7048 /* Copy frame data from 1st source buffer to the DMA buffers. */
7049 /* The frame data may span multiple DMA buffers. */
7050
7051 while( BufferSize ){
7052 /* Get a pointer to next DMA buffer entry. */
7053 pBufEntry = &info->tx_buffer_list[i++];
7054
7055 if ( i == info->tx_buffer_count )
7056 i=0;
7057
7058 /* Calculate the number of bytes that can be copied from */
7059 /* the source buffer to this DMA buffer. */
7060 if ( BufferSize > DMABUFFERSIZE )
7061 Copycount = DMABUFFERSIZE;
7062 else
7063 Copycount = BufferSize;
7064
7065 /* Actually copy data from source buffer to DMA buffer. */
7066 /* Also set the data count for this individual DMA buffer. */
7067 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
7068 mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
7069 else
7070 memcpy(pBufEntry->virt_addr, Buffer, Copycount);
7071
7072 pBufEntry->count = Copycount;
7073
7074 /* Advance source pointer and reduce remaining data count. */
7075 Buffer += Copycount;
7076 BufferSize -= Copycount;
7077
7078 ++info->tx_dma_buffers_used;
7079 }
7080
7081 /* remember next available tx dma buffer */
7082 info->current_tx_buffer = i;
7083
7084 } /* end of mgsl_load_tx_dma_buffer() */
7085
7086 /*
7087 * mgsl_register_test()
7088 *
7089 * Performs a register test of the 16C32.
7090 *
7091 * Arguments: info pointer to device instance data
7092 * Return Value: TRUE if test passed, otherwise FALSE
7093 */
7094 BOOLEAN mgsl_register_test( struct mgsl_struct *info )
7095 {
7096 static unsigned short BitPatterns[] =
7097 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
7098 static unsigned int Patterncount = sizeof(BitPatterns)/sizeof(unsigned short);
7099 unsigned int i;
7100 BOOLEAN rc = TRUE;
7101 unsigned long flags;
7102
7103 spin_lock_irqsave(&info->irq_spinlock,flags);
7104 usc_reset(info);
7105
7106 /* Verify the reset state of some registers. */
7107
7108 if ( (usc_InReg( info, SICR ) != 0) ||
7109 (usc_InReg( info, IVR ) != 0) ||
7110 (usc_InDmaReg( info, DIVR ) != 0) ){
7111 rc = FALSE;
7112 }
7113
7114 if ( rc == TRUE ){
7115 /* Write bit patterns to various registers but do it out of */
7116 /* sync, then read back and verify values. */
7117
7118 for ( i = 0 ; i < Patterncount ; i++ ) {
7119 usc_OutReg( info, TC0R, BitPatterns[i] );
7120 usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
7121 usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
7122 usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
7123 usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
7124 usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
7125
7126 if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
7127 (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
7128 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
7129 (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
7130 (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
7131 (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
7132 rc = FALSE;
7133 break;
7134 }
7135 }
7136 }
7137
7138 usc_reset(info);
7139 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7140
7141 return rc;
7142
7143 } /* end of mgsl_register_test() */
7144
7145 /* mgsl_irq_test() Perform interrupt test of the 16C32.
7146 *
7147 * Arguments: info pointer to device instance data
7148 * Return Value: TRUE if test passed, otherwise FALSE
7149 */
7150 BOOLEAN mgsl_irq_test( struct mgsl_struct *info )
7151 {
7152 unsigned long EndTime;
7153 unsigned long flags;
7154
7155 spin_lock_irqsave(&info->irq_spinlock,flags);
7156 usc_reset(info);
7157
7158 /*
7159 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
7160 * The ISR sets irq_occurred to 1.
7161 */
7162
7163 info->irq_occurred = FALSE;
7164
7165 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7166 /* Enable INTEN (Port 6, Bit12) */
7167 /* This connects the IRQ request signal to the ISA bus */
7168 /* on the ISA adapter. This has no effect for the PCI adapter */
7169 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
7170
7171 usc_EnableMasterIrqBit(info);
7172 usc_EnableInterrupts(info, IO_PIN);
7173 usc_ClearIrqPendingBits(info, IO_PIN);
7174
7175 usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
7176 usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
7177
7178 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7179
7180 EndTime=100;
7181 while( EndTime-- && !info->irq_occurred ) {
7182 set_current_state(TASK_INTERRUPTIBLE);
7183 schedule_timeout(jiffies_from_ms(10));
7184 }
7185
7186 spin_lock_irqsave(&info->irq_spinlock,flags);
7187 usc_reset(info);
7188 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7189
7190 if ( !info->irq_occurred )
7191 return FALSE;
7192 else
7193 return TRUE;
7194
7195 } /* end of mgsl_irq_test() */
7196
7197 /* mgsl_dma_test()
7198 *
7199 * Perform a DMA test of the 16C32. A small frame is
7200 * transmitted via DMA from a transmit buffer to a receive buffer
7201 * using single buffer DMA mode.
7202 *
7203 * Arguments: info pointer to device instance data
7204 * Return Value: TRUE if test passed, otherwise FALSE
7205 */
7206 BOOLEAN mgsl_dma_test( struct mgsl_struct *info )
7207 {
7208 unsigned short FifoLevel;
7209 unsigned long phys_addr;
7210 unsigned int FrameSize;
7211 unsigned int i;
7212 char *TmpPtr;
7213 BOOLEAN rc = TRUE;
7214 unsigned short status=0;
7215 unsigned long EndTime;
7216 unsigned long flags;
7217 MGSL_PARAMS tmp_params;
7218
7219 /* save current port options */
7220 memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
7221 /* load default port options */
7222 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
7223
7224 #define TESTFRAMESIZE 40
7225
7226 spin_lock_irqsave(&info->irq_spinlock,flags);
7227
7228 /* setup 16C32 for SDLC DMA transfer mode */
7229
7230 usc_reset(info);
7231 usc_set_sdlc_mode(info);
7232 usc_enable_loopback(info,1);
7233
7234 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7235 * field of the buffer entry after fetching buffer address. This
7236 * way we can detect a DMA failure for a DMA read (which should be
7237 * non-destructive to system memory) before we try and write to
7238 * memory (where a failure could corrupt system memory).
7239 */
7240
7241 /* Receive DMA mode Register (RDMR)
7242 *
7243 * <15..14> 11 DMA mode = Linked List Buffer mode
7244 * <13> 1 RSBinA/L = store Rx status Block in List entry
7245 * <12> 0 1 = Clear count of List Entry after fetching
7246 * <11..10> 00 Address mode = Increment
7247 * <9> 1 Terminate Buffer on RxBound
7248 * <8> 0 Bus Width = 16bits
7249 * <7..0> ? status Bits (write as 0s)
7250 *
7251 * 1110 0010 0000 0000 = 0xe200
7252 */
7253
7254 usc_OutDmaReg( info, RDMR, 0xe200 );
7255
7256 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7257
7258
7259 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7260
7261 FrameSize = TESTFRAMESIZE;
7262
7263 /* setup 1st transmit buffer entry: */
7264 /* with frame size and transmit control word */
7265
7266 info->tx_buffer_list[0].count = FrameSize;
7267 info->tx_buffer_list[0].rcc = FrameSize;
7268 info->tx_buffer_list[0].status = 0x4000;
7269
7270 /* build a transmit frame in 1st transmit DMA buffer */
7271
7272 TmpPtr = info->tx_buffer_list[0].virt_addr;
7273 for (i = 0; i < FrameSize; i++ )
7274 *TmpPtr++ = i;
7275
7276 /* setup 1st receive buffer entry: */
7277 /* clear status, set max receive buffer size */
7278
7279 info->rx_buffer_list[0].status = 0;
7280 info->rx_buffer_list[0].count = FrameSize + 4;
7281
7282 /* zero out the 1st receive buffer */
7283
7284 memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
7285
7286 /* Set count field of next buffer entries to prevent */
7287 /* 16C32 from using buffers after the 1st one. */
7288
7289 info->tx_buffer_list[1].count = 0;
7290 info->rx_buffer_list[1].count = 0;
7291
7292
7293 /***************************/
7294 /* Program 16C32 receiver. */
7295 /***************************/
7296
7297 spin_lock_irqsave(&info->irq_spinlock,flags);
7298
7299 /* setup DMA transfers */
7300 usc_RTCmd( info, RTCmd_PurgeRxFifo );
7301
7302 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7303 phys_addr = info->rx_buffer_list[0].phys_entry;
7304 usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
7305 usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
7306
7307 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7308 usc_InDmaReg( info, RDMR );
7309 usc_DmaCmd( info, DmaCmd_InitRxChannel );
7310
7311 /* Enable Receiver (RMR <1..0> = 10) */
7312 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
7313
7314 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7315
7316
7317 /*************************************************************/
7318 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7319 /*************************************************************/
7320
7321 /* Wait 100ms for interrupt. */
7322 EndTime = jiffies + jiffies_from_ms(100);
7323
7324 for(;;) {
7325 if (time_after(jiffies, EndTime)) {
7326 rc = FALSE;
7327 break;
7328 }
7329
7330 spin_lock_irqsave(&info->irq_spinlock,flags);
7331 status = usc_InDmaReg( info, RDMR );
7332 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7333
7334 if ( !(status & BIT4) && (status & BIT5) ) {
7335 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7336 /* BUSY (BIT 5) is active (channel still active). */
7337 /* This means the buffer entry read has completed. */
7338 break;
7339 }
7340 }
7341
7342
7343 /******************************/
7344 /* Program 16C32 transmitter. */
7345 /******************************/
7346
7347 spin_lock_irqsave(&info->irq_spinlock,flags);
7348
7349 /* Program the Transmit Character Length Register (TCLR) */
7350 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7351
7352 usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
7353 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7354
7355 /* Program the address of the 1st DMA Buffer Entry in linked list */
7356
7357 phys_addr = info->tx_buffer_list[0].phys_entry;
7358 usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
7359 usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
7360
7361 /* unlatch Tx status bits, and start transmit channel. */
7362
7363 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
7364 usc_DmaCmd( info, DmaCmd_InitTxChannel );
7365
7366 /* wait for DMA controller to fill transmit FIFO */
7367
7368 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
7369
7370 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7371
7372
7373 /**********************************/
7374 /* WAIT FOR TRANSMIT FIFO TO FILL */
7375 /**********************************/
7376
7377 /* Wait 100ms */
7378 EndTime = jiffies + jiffies_from_ms(100);
7379
7380 for(;;) {
7381 if (time_after(jiffies, EndTime)) {
7382 rc = FALSE;
7383 break;
7384 }
7385
7386 spin_lock_irqsave(&info->irq_spinlock,flags);
7387 FifoLevel = usc_InReg(info, TICR) >> 8;
7388 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7389
7390 if ( FifoLevel < 16 )
7391 break;
7392 else
7393 if ( FrameSize < 32 ) {
7394 /* This frame is smaller than the entire transmit FIFO */
7395 /* so wait for the entire frame to be loaded. */
7396 if ( FifoLevel <= (32 - FrameSize) )
7397 break;
7398 }
7399 }
7400
7401
7402 if ( rc == TRUE )
7403 {
7404 /* Enable 16C32 transmitter. */
7405
7406 spin_lock_irqsave(&info->irq_spinlock,flags);
7407
7408 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7409 usc_TCmd( info, TCmd_SendFrame );
7410 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
7411
7412 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7413
7414
7415 /******************************/
7416 /* WAIT FOR TRANSMIT COMPLETE */
7417 /******************************/
7418
7419 /* Wait 100ms */
7420 EndTime = jiffies + jiffies_from_ms(100);
7421
7422 /* While timer not expired wait for transmit complete */
7423
7424 spin_lock_irqsave(&info->irq_spinlock,flags);
7425 status = usc_InReg( info, TCSR );
7426 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7427
7428 while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) {
7429 if (time_after(jiffies, EndTime)) {
7430 rc = FALSE;
7431 break;
7432 }
7433
7434 spin_lock_irqsave(&info->irq_spinlock,flags);
7435 status = usc_InReg( info, TCSR );
7436 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7437 }
7438 }
7439
7440
7441 if ( rc == TRUE ){
7442 /* CHECK FOR TRANSMIT ERRORS */
7443 if ( status & (BIT5 + BIT1) )
7444 rc = FALSE;
7445 }
7446
7447 if ( rc == TRUE ) {
7448 /* WAIT FOR RECEIVE COMPLETE */
7449
7450 /* Wait 100ms */
7451 EndTime = jiffies + jiffies_from_ms(100);
7452
7453 /* Wait for 16C32 to write receive status to buffer entry. */
7454 status=info->rx_buffer_list[0].status;
7455 while ( status == 0 ) {
7456 if (time_after(jiffies, EndTime)) {
7457 rc = FALSE;
7458 break;
7459 }
7460 status=info->rx_buffer_list[0].status;
7461 }
7462 }
7463
7464
7465 if ( rc == TRUE ) {
7466 /* CHECK FOR RECEIVE ERRORS */
7467 status = info->rx_buffer_list[0].status;
7468
7469 if ( status & (BIT8 + BIT3 + BIT1) ) {
7470 /* receive error has occurred */
7471 rc = FALSE;
7472 } else {
7473 if ( memcmp( info->tx_buffer_list[0].virt_addr ,
7474 info->rx_buffer_list[0].virt_addr, FrameSize ) ){
7475 rc = FALSE;
7476 }
7477 }
7478 }
7479
7480 spin_lock_irqsave(&info->irq_spinlock,flags);
7481 usc_reset( info );
7482 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7483
7484 /* restore current port options */
7485 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
7486
7487 return rc;
7488
7489 } /* end of mgsl_dma_test() */
7490
7491 /* mgsl_adapter_test()
7492 *
7493 * Perform the register, IRQ, and DMA tests for the 16C32.
7494 *
7495 * Arguments: info pointer to device instance data
7496 * Return Value: 0 if success, otherwise -ENODEV
7497 */
7498 int mgsl_adapter_test( struct mgsl_struct *info )
7499 {
7500 if ( debug_level >= DEBUG_LEVEL_INFO )
7501 printk( "%s(%d):Testing device %s\n",
7502 __FILE__,__LINE__,info->device_name );
7503
7504 if ( !mgsl_register_test( info ) ) {
7505 info->init_error = DiagStatus_AddressFailure;
7506 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7507 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
7508 return -ENODEV;
7509 }
7510
7511 if ( !mgsl_irq_test( info ) ) {
7512 info->init_error = DiagStatus_IrqFailure;
7513 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7514 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
7515 return -ENODEV;
7516 }
7517
7518 if ( !mgsl_dma_test( info ) ) {
7519 info->init_error = DiagStatus_DmaFailure;
7520 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7521 __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
7522 return -ENODEV;
7523 }
7524
7525 if ( debug_level >= DEBUG_LEVEL_INFO )
7526 printk( "%s(%d):device %s passed diagnostics\n",
7527 __FILE__,__LINE__,info->device_name );
7528
7529 return 0;
7530
7531 } /* end of mgsl_adapter_test() */
7532
7533 /* mgsl_memory_test()
7534 *
7535 * Test the shared memory on a PCI adapter.
7536 *
7537 * Arguments: info pointer to device instance data
7538 * Return Value: TRUE if test passed, otherwise FALSE
7539 */
7540 BOOLEAN mgsl_memory_test( struct mgsl_struct *info )
7541 {
7542 static unsigned long BitPatterns[] = { 0x0, 0x55555555, 0xaaaaaaaa,
7543 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7544 unsigned long Patterncount = sizeof(BitPatterns)/sizeof(unsigned long);
7545 unsigned long i;
7546 unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
7547 unsigned long * TestAddr;
7548
7549 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
7550 return TRUE;
7551
7552 TestAddr = (unsigned long *)info->memory_base;
7553
7554 /* Test data lines with test pattern at one location. */
7555
7556 for ( i = 0 ; i < Patterncount ; i++ ) {
7557 *TestAddr = BitPatterns[i];
7558 if ( *TestAddr != BitPatterns[i] )
7559 return FALSE;
7560 }
7561
7562 /* Test address lines with incrementing pattern over */
7563 /* entire address range. */
7564
7565 for ( i = 0 ; i < TestLimit ; i++ ) {
7566 *TestAddr = i * 4;
7567 TestAddr++;
7568 }
7569
7570 TestAddr = (unsigned long *)info->memory_base;
7571
7572 for ( i = 0 ; i < TestLimit ; i++ ) {
7573 if ( *TestAddr != i * 4 )
7574 return FALSE;
7575 TestAddr++;
7576 }
7577
7578 memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
7579
7580 return TRUE;
7581
7582 } /* End Of mgsl_memory_test() */
7583
7584
7585 /* mgsl_load_pci_memory()
7586 *
7587 * Load a large block of data into the PCI shared memory.
7588 * Use this instead of memcpy() or memmove() to move data
7589 * into the PCI shared memory.
7590 *
7591 * Notes:
7592 *
7593 * This function prevents the PCI9050 interface chip from hogging
7594 * the adapter local bus, which can starve the 16C32 by preventing
7595 * 16C32 bus master cycles.
7596 *
7597 * The PCI9050 documentation says that the 9050 will always release
7598 * control of the local bus after completing the current read
7599 * or write operation.
7600 *
7601 * It appears that as long as the PCI9050 write FIFO is full, the
7602 * PCI9050 treats all of the writes as a single burst transaction
7603 * and will not release the bus. This causes DMA latency problems
7604 * at high speeds when copying large data blocks to the shared
7605 * memory.
7606 *
7607 * This function in effect, breaks the a large shared memory write
7608 * into multiple transations by interleaving a shared memory read
7609 * which will flush the write FIFO and 'complete' the write
7610 * transation. This allows any pending DMA request to gain control
7611 * of the local bus in a timely fasion.
7612 *
7613 * Arguments:
7614 *
7615 * TargetPtr pointer to target address in PCI shared memory
7616 * SourcePtr pointer to source buffer for data
7617 * count count in bytes of data to copy
7618 *
7619 * Return Value: None
7620 */
7621 void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
7622 unsigned short count )
7623 {
7624 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7625 #define PCI_LOAD_INTERVAL 64
7626
7627 unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
7628 unsigned short Index;
7629 unsigned long Dummy;
7630
7631 for ( Index = 0 ; Index < Intervalcount ; Index++ )
7632 {
7633 memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
7634 Dummy = *((volatile unsigned long *)TargetPtr);
7635 TargetPtr += PCI_LOAD_INTERVAL;
7636 SourcePtr += PCI_LOAD_INTERVAL;
7637 }
7638
7639 memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
7640
7641 } /* End Of mgsl_load_pci_memory() */
7642
7643 void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
7644 {
7645 int i;
7646 int linecount;
7647 if (xmit)
7648 printk("%s tx data:\n",info->device_name);
7649 else
7650 printk("%s rx data:\n",info->device_name);
7651
7652 while(count) {
7653 if (count > 16)
7654 linecount = 16;
7655 else
7656 linecount = count;
7657
7658 for(i=0;i<linecount;i++)
7659 printk("%02X ",(unsigned char)data[i]);
7660 for(;i<17;i++)
7661 printk(" ");
7662 for(i=0;i<linecount;i++) {
7663 if (data[i]>=040 && data[i]<=0176)
7664 printk("%c",data[i]);
7665 else
7666 printk(".");
7667 }
7668 printk("\n");
7669
7670 data += linecount;
7671 count -= linecount;
7672 }
7673 } /* end of mgsl_trace_block() */
7674
7675 /* mgsl_tx_timeout()
7676 *
7677 * called when HDLC frame times out
7678 * update stats and do tx completion processing
7679 *
7680 * Arguments: context pointer to device instance data
7681 * Return Value: None
7682 */
7683 void mgsl_tx_timeout(unsigned long context)
7684 {
7685 struct mgsl_struct *info = (struct mgsl_struct*)context;
7686 unsigned long flags;
7687
7688 if ( debug_level >= DEBUG_LEVEL_INFO )
7689 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7690 __FILE__,__LINE__,info->device_name);
7691 if(info->tx_active &&
7692 (info->params.mode == MGSL_MODE_HDLC ||
7693 info->params.mode == MGSL_MODE_RAW) ) {
7694 info->icount.txtimeout++;
7695 }
7696 spin_lock_irqsave(&info->irq_spinlock,flags);
7697 info->tx_active = 0;
7698 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
7699
7700 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
7701 usc_loopmode_cancel_transmit( info );
7702
7703 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7704
7705 #ifdef CONFIG_SYNCLINK_SYNCPPP
7706 if (info->netcount)
7707 mgsl_sppp_tx_done(info);
7708 else
7709 #endif
7710 mgsl_bh_transmit(info);
7711
7712 } /* end of mgsl_tx_timeout() */
7713
7714 /* signal that there are no more frames to send, so that
7715 * line is 'released' by echoing RxD to TxD when current
7716 * transmission is complete (or immediately if no tx in progress).
7717 */
7718 static int mgsl_loopmode_send_done( struct mgsl_struct * info )
7719 {
7720 unsigned long flags;
7721
7722 spin_lock_irqsave(&info->irq_spinlock,flags);
7723 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7724 if (info->tx_active)
7725 info->loopmode_send_done_requested = TRUE;
7726 else
7727 usc_loopmode_send_done(info);
7728 }
7729 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7730
7731 return 0;
7732 }
7733
7734 /* release the line by echoing RxD to TxD
7735 * upon completion of a transmit frame
7736 */
7737 void usc_loopmode_send_done( struct mgsl_struct * info )
7738 {
7739 info->loopmode_send_done_requested = FALSE;
7740 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7741 info->cmr_value &= ~BIT13;
7742 usc_OutReg(info, CMR, info->cmr_value);
7743 }
7744
7745 /* abort a transmit in progress while in HDLC LoopMode
7746 */
7747 void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
7748 {
7749 /* reset tx dma channel and purge TxFifo */
7750 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7751 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
7752 usc_loopmode_send_done( info );
7753 }
7754
7755 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7756 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7757 * we must clear CMR:13 to begin repeating TxData to RxData
7758 */
7759 void usc_loopmode_insert_request( struct mgsl_struct * info )
7760 {
7761 info->loopmode_insert_requested = TRUE;
7762
7763 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7764 * begin repeating TxData on RxData (complete insertion)
7765 */
7766 usc_OutReg( info, RICR,
7767 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
7768
7769 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7770 info->cmr_value |= BIT13;
7771 usc_OutReg(info, CMR, info->cmr_value);
7772 }
7773
7774 /* return 1 if station is inserted into the loop, otherwise 0
7775 */
7776 int usc_loopmode_active( struct mgsl_struct * info)
7777 {
7778 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
7779 }
7780
7781 /* return 1 if USC is in loop send mode, otherwise 0
7782 */
7783 int usc_loopmode_send_active( struct mgsl_struct * info )
7784 {
7785 return usc_InReg( info, CCSR ) & BIT6 ? 1 : 0 ;
7786 }
7787
7788 #ifdef CONFIG_SYNCLINK_SYNCPPP
7789 /* syncppp net device routines
7790 */
7791
7792 void mgsl_sppp_init(struct mgsl_struct *info)
7793 {
7794 struct net_device *d;
7795
7796 sprintf(info->netname,"mgsl%d",info->line);
7797
7798 info->if_ptr = &info->pppdev;
7799 info->netdev = info->pppdev.dev = &info->netdevice;
7800
7801 sppp_attach(&info->pppdev);
7802
7803 d = info->netdev;
7804 strcpy(d->name,info->netname);
7805 d->base_addr = info->io_base;
7806 d->irq = info->irq_level;
7807 d->dma = info->dma_level;
7808 d->priv = info;
7809 d->init = NULL;
7810 d->open = mgsl_sppp_open;
7811 d->stop = mgsl_sppp_close;
7812 d->hard_start_xmit = mgsl_sppp_tx;
7813 d->do_ioctl = mgsl_sppp_ioctl;
7814 d->get_stats = mgsl_net_stats;
7815 d->tx_timeout = mgsl_sppp_tx_timeout;
7816 d->watchdog_timeo = 10*HZ;
7817
7818 if (register_netdev(d) == -1) {
7819 printk(KERN_WARNING "%s: register_netdev failed.\n", d->name);
7820 sppp_detach(info->netdev);
7821 return;
7822 }
7823
7824 if (debug_level >= DEBUG_LEVEL_INFO)
7825 printk("mgsl_sppp_init()\n");
7826 }
7827
7828 void mgsl_sppp_delete(struct mgsl_struct *info)
7829 {
7830 if (debug_level >= DEBUG_LEVEL_INFO)
7831 printk("mgsl_sppp_delete(%s)\n",info->netname);
7832 sppp_detach(info->netdev);
7833 unregister_netdev(info->netdev);
7834 }
7835
7836 int mgsl_sppp_open(struct net_device *d)
7837 {
7838 struct mgsl_struct *info = d->priv;
7839 int err;
7840 unsigned long flags;
7841
7842 if (debug_level >= DEBUG_LEVEL_INFO)
7843 printk("mgsl_sppp_open(%s)\n",info->netname);
7844
7845 spin_lock_irqsave(&info->netlock, flags);
7846 if (info->count != 0 || info->netcount != 0) {
7847 printk(KERN_WARNING "%s: sppp_open returning busy\n", info->netname);
7848 spin_unlock_irqrestore(&info->netlock, flags);
7849 return -EBUSY;
7850 }
7851 info->netcount=1;
7852 spin_unlock_irqrestore(&info->netlock, flags);
7853
7854 /* claim resources and init adapter */
7855 if ((err = startup(info)) != 0)
7856 goto open_fail;
7857
7858 /* allow syncppp module to do open processing */
7859 if ((err = sppp_open(d)) != 0) {
7860 shutdown(info);
7861 goto open_fail;
7862 }
7863
7864 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
7865 mgsl_program_hw(info);
7866
7867 d->trans_start = jiffies;
7868 netif_start_queue(d);
7869 return 0;
7870
7871 open_fail:
7872 spin_lock_irqsave(&info->netlock, flags);
7873 info->netcount=0;
7874 spin_unlock_irqrestore(&info->netlock, flags);
7875 return err;
7876 }
7877
7878 void mgsl_sppp_tx_timeout(struct net_device *dev)
7879 {
7880 struct mgsl_struct *info = dev->priv;
7881 unsigned long flags;
7882
7883 if (debug_level >= DEBUG_LEVEL_INFO)
7884 printk("mgsl_sppp_tx_timeout(%s)\n",info->netname);
7885
7886 info->netstats.tx_errors++;
7887 info->netstats.tx_aborted_errors++;
7888
7889 spin_lock_irqsave(&info->irq_spinlock,flags);
7890 usc_stop_transmitter(info);
7891 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7892
7893 netif_wake_queue(dev);
7894 }
7895
7896 int mgsl_sppp_tx(struct sk_buff *skb, struct net_device *dev)
7897 {
7898 struct mgsl_struct *info = dev->priv;
7899 unsigned long flags;
7900
7901 if (debug_level >= DEBUG_LEVEL_INFO)
7902 printk("mgsl_sppp_tx(%s)\n",info->netname);
7903
7904 netif_stop_queue(dev);
7905
7906 info->xmit_cnt = skb->len;
7907 mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
7908 info->netstats.tx_packets++;
7909 info->netstats.tx_bytes += skb->len;
7910 dev_kfree_skb(skb);
7911
7912 dev->trans_start = jiffies;
7913
7914 spin_lock_irqsave(&info->irq_spinlock,flags);
7915 if (!info->tx_active)
7916 usc_start_transmitter(info);
7917 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7918
7919 return 0;
7920 }
7921
7922 int mgsl_sppp_close(struct net_device *d)
7923 {
7924 struct mgsl_struct *info = d->priv;
7925 unsigned long flags;
7926
7927 if (debug_level >= DEBUG_LEVEL_INFO)
7928 printk("mgsl_sppp_close(%s)\n",info->netname);
7929
7930 /* shutdown adapter and release resources */
7931 shutdown(info);
7932
7933 /* allow syncppp to do close processing */
7934 sppp_close(d);
7935 netif_stop_queue(d);
7936
7937 spin_lock_irqsave(&info->netlock, flags);
7938 info->netcount=0;
7939 spin_unlock_irqrestore(&info->netlock, flags);
7940 return 0;
7941 }
7942
7943 void mgsl_sppp_rx_done(struct mgsl_struct *info, char *buf, int size)
7944 {
7945 struct sk_buff *skb = dev_alloc_skb(size);
7946 if (debug_level >= DEBUG_LEVEL_INFO)
7947 printk("mgsl_sppp_rx_done(%s)\n",info->netname);
7948 if (skb == NULL) {
7949 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
7950 info->netname);
7951 info->netstats.rx_dropped++;
7952 return;
7953 }
7954
7955 memcpy(skb_put(skb, size),buf,size);
7956
7957 skb->protocol = htons(ETH_P_WAN_PPP);
7958 skb->dev = info->netdev;
7959 skb->mac.raw = skb->data;
7960 info->netstats.rx_packets++;
7961 info->netstats.rx_bytes += size;
7962 netif_rx(skb);
7963 info->netdev->trans_start = jiffies;
7964 }
7965
7966 void mgsl_sppp_tx_done(struct mgsl_struct *info)
7967 {
7968 if (netif_queue_stopped(info->netdev))
7969 netif_wake_queue(info->netdev);
7970 }
7971
7972 struct net_device_stats *mgsl_net_stats(struct net_device *dev)
7973 {
7974 struct mgsl_struct *info = dev->priv;
7975 if (debug_level >= DEBUG_LEVEL_INFO)
7976 printk("mgsl_net_stats(%s)\n",info->netname);
7977 return &info->netstats;
7978 }
7979
7980 int mgsl_sppp_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7981 {
7982 struct mgsl_struct *info = (struct mgsl_struct *)dev->priv;
7983 if (debug_level >= DEBUG_LEVEL_INFO)
7984 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
7985 info->netname, cmd );
7986 return sppp_do_ioctl(dev, ifr, cmd);
7987 }
7988
7989 #endif /* ifdef CONFIG_SYNCLINK_SYNCPPP */
7990
7991 static int __init synclink_init_one (struct pci_dev *dev,
7992 const struct pci_device_id *ent)
7993 {
7994 struct mgsl_struct *info;
7995
7996 if (pci_enable_device(dev)) {
7997 printk("error enabling pci device %p\n", dev);
7998 return -EIO;
7999 }
8000
8001 if (!(info = mgsl_allocate_device())) {
8002 printk("can't allocate device instance data.\n");
8003 return -EIO;
8004 }
8005
8006 /* Copy user configuration info to device instance data */
8007
8008 info->io_base = pci_resource_start(dev, 2);
8009 info->irq_level = dev->irq;
8010 info->phys_memory_base = pci_resource_start(dev, 3);
8011
8012 /* Because veremap only works on page boundaries we must map
8013 * a larger area than is actually implemented for the LCR
8014 * memory range. We map a full page starting at the page boundary.
8015 */
8016 info->phys_lcr_base = pci_resource_start(dev, 0);
8017 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
8018 info->phys_lcr_base &= ~(PAGE_SIZE-1);
8019
8020 info->bus_type = MGSL_BUS_TYPE_PCI;
8021 info->io_addr_size = 8;
8022 info->irq_flags = SA_SHIRQ;
8023
8024 if (dev->device == 0x0210) {
8025 /* Version 1 PCI9030 based universal PCI adapter */
8026 info->misc_ctrl_value = 0x007c4080;
8027 info->hw_version = 1;
8028 } else {
8029 /* Version 0 PCI9050 based 5V PCI adapter
8030 * A PCI9050 bug prevents reading LCR registers if
8031 * LCR base address bit 7 is set. Maintain shadow
8032 * value so we can write to LCR misc control reg.
8033 */
8034 info->misc_ctrl_value = 0x087e4546;
8035 info->hw_version = 0;
8036 }
8037
8038 mgsl_add_device(info);
8039
8040 return 0;
8041 }
8042
8043 static void __devexit synclink_remove_one (struct pci_dev *dev)
8044 {
8045 }
8046
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