drivers/char/agp/sworks-agp.c

   1 /*
   2  * Serverworks AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/agp_backend.h>
   9 #include "agp.h"
  10
  11 static int agp_try_unsupported __initdata = 0;
  12
  13 struct serverworks_page_map {
  14         unsigned long *real;
  15         unsigned long *remapped;
  16 };
  17
  18 static struct _serverworks_private {
  19         struct pci_dev *svrwrks_dev;    /* device one */
  20         volatile u8 *registers;
  21         struct serverworks_page_map **gatt_pages;
  22         int num_tables;
  23         struct serverworks_page_map scratch_dir;
  24
  25         int gart_addr_ofs;
  26         int mm_addr_ofs;
  27 } serverworks_private;
  28
  29 static int serverworks_create_page_map(struct serverworks_page_map *page_map)
  30 {
  31         int i;
  32
  33         page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
  34         if (page_map->real == NULL) {
  35                 return -ENOMEM;
  36         }
  37         SetPageReserved(virt_to_page(page_map->real));
  38         global_cache_flush();
  39         page_map->remapped = ioremap_nocache(virt_to_phys(page_map->real),
  40                                             PAGE_SIZE);
  41         if (page_map->remapped == NULL) {
  42                 ClearPageReserved(virt_to_page(page_map->real));
  43                 free_page((unsigned long) page_map->real);
  44                 page_map->real = NULL;
  45                 return -ENOMEM;
  46         }
  47         global_cache_flush();
  48
  49         for(i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
  50                 page_map->remapped[i] = agp_bridge->scratch_page;
  51         }
  52
  53         return 0;
  54 }
  55
  56 static void serverworks_free_page_map(struct serverworks_page_map *page_map)
  57 {
  58         iounmap(page_map->remapped);
  59         ClearPageReserved(virt_to_page(page_map->real));
  60         free_page((unsigned long) page_map->real);
  61 }
  62
  63 static void serverworks_free_gatt_pages(void)
  64 {
  65         int i;
  66         struct serverworks_page_map **tables;
  67         struct serverworks_page_map *entry;
  68
  69         tables = serverworks_private.gatt_pages;
  70         for(i = 0; i < serverworks_private.num_tables; i++) {
  71                 entry = tables[i];
  72                 if (entry != NULL) {
  73                         if (entry->real != NULL) {
  74                                 serverworks_free_page_map(entry);
  75                         }
  76                         kfree(entry);
  77                 }
  78         }
  79         kfree(tables);
  80 }
  81
  82 static int serverworks_create_gatt_pages(int nr_tables)
  83 {
  84         struct serverworks_page_map **tables;
  85         struct serverworks_page_map *entry;
  86         int retval = 0;
  87         int i;
  88
  89         tables = kmalloc((nr_tables + 1) * sizeof(struct serverworks_page_map *),
  90                          GFP_KERNEL);
  91         if (tables == NULL) {
  92                 return -ENOMEM;
  93         }
  94         memset(tables, 0, sizeof(struct serverworks_page_map *) * (nr_tables + 1));
  95         for (i = 0; i < nr_tables; i++) {
  96                 entry = kmalloc(sizeof(struct serverworks_page_map), GFP_KERNEL);
  97                 if (entry == NULL) {
  98                         retval = -ENOMEM;
  99                         break;
 100                 }
 101                 memset(entry, 0, sizeof(struct serverworks_page_map));
 102                 tables[i] = entry;
 103                 retval = serverworks_create_page_map(entry);
 104                 if (retval != 0) break;
 105         }
 106         serverworks_private.num_tables = nr_tables;
 107         serverworks_private.gatt_pages = tables;
 108
 109         if (retval != 0) serverworks_free_gatt_pages();
 110
 111         return retval;
 112 }
 113
 114 #define SVRWRKS_GET_GATT(addr) (serverworks_private.gatt_pages[\
 115         GET_PAGE_DIR_IDX(addr)]->remapped)
 116
 117 #ifndef GET_PAGE_DIR_OFF
 118 #define GET_PAGE_DIR_OFF(addr) (addr >> 22)
 119 #endif
 120
 121 #ifndef GET_PAGE_DIR_IDX
 122 #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
 123         GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
 124 #endif
 125
 126 #ifndef GET_GATT_OFF
 127 #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
 128 #endif
 129
 130 static int serverworks_create_gatt_table(void)
 131 {
 132         struct aper_size_info_lvl2 *value;
 133         struct serverworks_page_map page_dir;
 134         int retval;
 135         u32 temp;
 136         int i;
 137
 138         value = A_SIZE_LVL2(agp_bridge->current_size);
 139         retval = serverworks_create_page_map(&page_dir);
 140         if (retval != 0) {
 141                 return retval;
 142         }
 143         retval = serverworks_create_page_map(&serverworks_private.scratch_dir);
 144         if (retval != 0) {
 145                 serverworks_free_page_map(&page_dir);
 146                 return retval;
 147         }
 148         /* Create a fake scratch directory */
 149         for(i = 0; i < 1024; i++) {
 150                 serverworks_private.scratch_dir.remapped[i] = (unsigned long) agp_bridge->scratch_page;
 151                 page_dir.remapped[i] =
 152                         virt_to_phys(serverworks_private.scratch_dir.real);
 153                 page_dir.remapped[i] |= 0x00000001;
 154         }
 155
 156         retval = serverworks_create_gatt_pages(value->num_entries / 1024);
 157         if (retval != 0) {
 158                 serverworks_free_page_map(&page_dir);
 159                 serverworks_free_page_map(&serverworks_private.scratch_dir);
 160                 return retval;
 161         }
 162
 163         agp_bridge->gatt_table_real = (u32 *)page_dir.real;
 164         agp_bridge->gatt_table = (u32 *)page_dir.remapped;
 165         agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);
 166
 167         /* Get the address for the gart region.
 168          * This is a bus address even on the alpha, b/c its
 169          * used to program the agp master not the cpu
 170          */
 171
 172         pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
 173         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 174
 175         /* Calculate the agp offset */
 176
 177         for(i = 0; i < value->num_entries / 1024; i++) {
 178                 page_dir.remapped[i] =
 179                         virt_to_phys(serverworks_private.gatt_pages[i]->real);
 180                 page_dir.remapped[i] |= 0x00000001;
 181         }
 182
 183         return 0;
 184 }
 185
 186 static int serverworks_free_gatt_table(void)
 187 {
 188         struct serverworks_page_map page_dir;
 189
 190         page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
 191         page_dir.remapped = (unsigned long *)agp_bridge->gatt_table;
 192
 193         serverworks_free_gatt_pages();
 194         serverworks_free_page_map(&page_dir);
 195         serverworks_free_page_map(&serverworks_private.scratch_dir);
 196         return 0;
 197 }
 198
 199 static int serverworks_fetch_size(void)
 200 {
 201         int i;
 202         u32 temp;
 203         u32 temp2;
 204         struct aper_size_info_lvl2 *values;
 205
 206         values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
 207         pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
 208         pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,
 209                                         SVWRKS_SIZE_MASK);
 210         pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp2);
 211         pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,temp);
 212         temp2 &= SVWRKS_SIZE_MASK;
 213
 214         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
 215                 if (temp2 == values[i].size_value) {
 216                         agp_bridge->previous_size =
 217                             agp_bridge->current_size = (void *) (values + i);
 218
 219                         agp_bridge->aperture_size_idx = i;
 220                         return values[i].size;
 221                 }
 222         }
 223
 224         return 0;
 225 }
 226
 227 /*
 228  * This routine could be implemented by taking the addresses
 229  * written to the GATT, and flushing them individually.  However
 230  * currently it just flushes the whole table.  Which is probably
 231  * more efficent, since agp_memory blocks can be a large number of
 232  * entries.
 233  */
 234 static void serverworks_tlbflush(struct agp_memory *temp)
 235 {
 236         unsigned long end;
 237
 238         OUTREG8(serverworks_private.registers, SVWRKS_POSTFLUSH, 0x01);
 239         end = jiffies + 3*HZ;
 240         while(INREG8(serverworks_private.registers,
 241                      SVWRKS_POSTFLUSH) == 0x01) {
 242                 if((signed)(end - jiffies) <= 0) {
 243                         printk(KERN_ERR PFX "Posted write buffer flush took more"
 244                                "then 3 seconds\n");
 245                 }
 246         }
 247         OUTREG32(serverworks_private.registers, SVWRKS_DIRFLUSH, 0x00000001);
 248         end = jiffies + 3*HZ;
 249         while(INREG32(serverworks_private.registers,
 250                      SVWRKS_DIRFLUSH) == 0x00000001) {
 251                 if((signed)(end - jiffies) <= 0) {
 252                         printk(KERN_ERR PFX "TLB flush took more"
 253                                "then 3 seconds\n");
 254                 }
 255         }
 256 }
 257
 258 static int serverworks_configure(void)
 259 {
 260         struct aper_size_info_lvl2 *current_size;
 261         u32 temp;
 262         u8 enable_reg;
 263         u16 cap_reg;
 264
 265         current_size = A_SIZE_LVL2(agp_bridge->current_size);
 266
 267         /* Get the memory mapped registers */
 268         pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp);
 269         temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 270         serverworks_private.registers = (volatile u8 *) ioremap(temp, 4096);
 271
 272         OUTREG8(serverworks_private.registers, SVWRKS_GART_CACHE, 0x0a);
 273
 274         OUTREG32(serverworks_private.registers, SVWRKS_GATTBASE,
 275                  agp_bridge->gatt_bus_addr);
 276
 277         cap_reg = INREG16(serverworks_private.registers, SVWRKS_COMMAND);
 278         cap_reg &= ~0x0007;
 279         cap_reg |= 0x4;
 280         OUTREG16(serverworks_private.registers, SVWRKS_COMMAND, cap_reg);
 281
 282         pci_read_config_byte(serverworks_private.svrwrks_dev,
 283                              SVWRKS_AGP_ENABLE, &enable_reg);
 284         enable_reg |= 0x1; /* Agp Enable bit */
 285         pci_write_config_byte(serverworks_private.svrwrks_dev,
 286                               SVWRKS_AGP_ENABLE, enable_reg);
 287         serverworks_tlbflush(NULL);
 288
 289         agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);
 290
 291         /* Fill in the mode register */
 292         pci_read_config_dword(serverworks_private.svrwrks_dev,
 293                               agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
 294
 295         pci_read_config_byte(agp_bridge->dev, SVWRKS_CACHING, &enable_reg);
 296         enable_reg &= ~0x3;
 297         pci_write_config_byte(agp_bridge->dev, SVWRKS_CACHING, enable_reg);
 298
 299         pci_read_config_byte(agp_bridge->dev, SVWRKS_FEATURE, &enable_reg);
 300         enable_reg |= (1<<6);
 301         pci_write_config_byte(agp_bridge->dev,SVWRKS_FEATURE, enable_reg);
 302
 303         return 0;
 304 }
 305
 306 static void serverworks_cleanup(void)
 307 {
 308         iounmap((void *) serverworks_private.registers);
 309 }
 310
 311 static int serverworks_insert_memory(struct agp_memory *mem,
 312                              off_t pg_start, int type)
 313 {
 314         int i, j, num_entries;
 315         unsigned long *cur_gatt;
 316         unsigned long addr;
 317
 318         num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
 319
 320         if (type != 0 || mem->type != 0) {
 321                 return -EINVAL;
 322         }
 323         if ((pg_start + mem->page_count) > num_entries) {
 324                 return -EINVAL;
 325         }
 326
 327         j = pg_start;
 328         while (j < (pg_start + mem->page_count)) {
 329                 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 330                 cur_gatt = SVRWRKS_GET_GATT(addr);
 331                 if (!PGE_EMPTY(agp_bridge, cur_gatt[GET_GATT_OFF(addr)])) {
 332                         return -EBUSY;
 333                 }
 334                 j++;
 335         }
 336
 337         if (mem->is_flushed == FALSE) {
 338                 global_cache_flush();
 339                 mem->is_flushed = TRUE;
 340         }
 341
 342         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 343                 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 344                 cur_gatt = SVRWRKS_GET_GATT(addr);
 345                 cur_gatt[GET_GATT_OFF(addr)] =
 346                         agp_bridge->driver->mask_memory(mem->memory[i], mem->type);
 347         }
 348         serverworks_tlbflush(mem);
 349         return 0;
 350 }
 351
 352 static int serverworks_remove_memory(struct agp_memory *mem, off_t pg_start,
 353                              int type)
 354 {
 355         int i;
 356         unsigned long *cur_gatt;
 357         unsigned long addr;
 358
 359         if (type != 0 || mem->type != 0) {
 360                 return -EINVAL;
 361         }
 362
 363         global_cache_flush();
 364         serverworks_tlbflush(mem);
 365
 366         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 367                 addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 368                 cur_gatt = SVRWRKS_GET_GATT(addr);
 369                 cur_gatt[GET_GATT_OFF(addr)] =
 370                         (unsigned long) agp_bridge->scratch_page;
 371         }
 372
 373         serverworks_tlbflush(mem);
 374         return 0;
 375 }
 376
 377 static struct gatt_mask serverworks_masks[] =
 378 {
 379         {.mask = 1, .type = 0}
 380 };
 381
 382 static struct aper_size_info_lvl2 serverworks_sizes[7] =
 383 {
 384         {2048, 524288, 0x80000000},
 385         {1024, 262144, 0xc0000000},
 386         {512, 131072, 0xe0000000},
 387         {256, 65536, 0xf0000000},
 388         {128, 32768, 0xf8000000},
 389         {64, 16384, 0xfc000000},
 390         {32, 8192, 0xfe000000}
 391 };
 392
 393 static void serverworks_agp_enable(u32 mode)
 394 {
 395         u32 command;
 396
 397         pci_read_config_dword(serverworks_private.svrwrks_dev,
 398                               agp_bridge->capndx + PCI_AGP_STATUS,
 399                               &command);
 400
 401         command = agp_collect_device_status(mode, command);
 402
 403         command &= ~0x10;       /* disable FW */
 404         command &= ~0x08;
 405
 406         command |= 0x100;
 407
 408         pci_write_config_dword(serverworks_private.svrwrks_dev,
 409                                agp_bridge->capndx + PCI_AGP_COMMAND,
 410                                command);
 411
 412         agp_device_command(command, 0);
 413 }
 414
 415 struct agp_bridge_driver sworks_driver = {
 416         .owner                  = THIS_MODULE,
 417         .aperture_sizes         = serverworks_sizes,
 418         .size_type              = LVL2_APER_SIZE,
 419         .num_aperture_sizes     = 7,
 420         .configure              = serverworks_configure,
 421         .fetch_size             = serverworks_fetch_size,
 422         .cleanup                = serverworks_cleanup,
 423         .tlb_flush              = serverworks_tlbflush,
 424         .mask_memory            = agp_generic_mask_memory,
 425         .masks                  = serverworks_masks,
 426         .agp_enable             = serverworks_agp_enable,
 427         .cache_flush            = global_cache_flush,
 428         .create_gatt_table      = serverworks_create_gatt_table,
 429         .free_gatt_table        = serverworks_free_gatt_table,
 430         .insert_memory          = serverworks_insert_memory,
 431         .remove_memory          = serverworks_remove_memory,
 432         .alloc_by_type          = agp_generic_alloc_by_type,
 433         .free_by_type           = agp_generic_free_by_type,
 434         .agp_alloc_page         = agp_generic_alloc_page,
 435         .agp_destroy_page       = agp_generic_destroy_page,
 436 };
 437
 438 static int __init agp_serverworks_probe(struct pci_dev *pdev,
 439                                         const struct pci_device_id *ent)
 440 {
 441         struct agp_bridge_data *bridge;
 442         struct pci_dev *bridge_dev;
 443         u32 temp, temp2;
 444
 445         /* Everything is on func 1 here so we are hardcoding function one */
 446         bridge_dev = pci_find_slot((unsigned int)pdev->bus->number,
 447                         PCI_DEVFN(0, 1));
 448         if (!bridge_dev) {
 449                 printk(KERN_INFO PFX "agpgart: Detected a Serverworks "
 450                        "Chipset, but could not find the secondary device.\n");
 451                 return -ENODEV;
 452         }
 453
 454         switch (pdev->device) {
 455         case PCI_DEVICE_ID_SERVERWORKS_HE:
 456         case PCI_DEVICE_ID_SERVERWORKS_LE:
 457         case 0x0007:
 458                 break;
 459         default:
 460                 if (!agp_try_unsupported)
 461                         return -ENODEV;
 462                 break;
 463         }
 464
 465         serverworks_private.svrwrks_dev = bridge_dev;
 466         serverworks_private.gart_addr_ofs = 0x10;
 467
 468         pci_read_config_dword(pdev, SVWRKS_APSIZE, &temp);
 469         if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 470                 pci_read_config_dword(pdev, SVWRKS_APSIZE + 4, &temp2);
 471                 if (temp2 != 0) {
 472                         printk(KERN_INFO PFX "Detected 64 bit aperture address, "
 473                                "but top bits are not zero.  Disabling agp\n");
 474                         return -ENODEV;
 475                 }
 476                 serverworks_private.mm_addr_ofs = 0x18;
 477         } else
 478                 serverworks_private.mm_addr_ofs = 0x14;
 479
 480         pci_read_config_dword(pdev, serverworks_private.mm_addr_ofs, &temp);
 481         if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 482                 pci_read_config_dword(pdev,
 483                                 serverworks_private.mm_addr_ofs + 4, &temp2);
 484                 if (temp2 != 0) {
 485                         printk(KERN_INFO PFX "Detected 64 bit MMIO address, "
 486                                "but top bits are not zero.  Disabling agp\n");
 487                         return -ENODEV;
 488                 }
 489         }
 490
 491         bridge = agp_alloc_bridge();
 492         if (!bridge)
 493                 return -ENOMEM;
 494
 495         bridge->driver = &sworks_driver;
 496         bridge->dev_private_data = &serverworks_private,
 497         bridge->dev = pdev;
 498
 499         pci_set_drvdata(pdev, bridge);
 500         return agp_add_bridge(bridge);
 501 }
 502
 503 static void __devexit agp_serverworks_remove(struct pci_dev *pdev)
 504 {
 505         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
 506
 507         agp_remove_bridge(bridge);
 508         agp_put_bridge(bridge);
 509 }
 510
 511 static struct pci_device_id agp_serverworks_pci_table[] __initdata = {
 512         {
 513         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 514         .class_mask     = ~0,
 515         .vendor         = PCI_VENDOR_ID_SERVERWORKS,
 516         .device         = PCI_ANY_ID,
 517         .subvendor      = PCI_ANY_ID,
 518         .subdevice      = PCI_ANY_ID,
 519         },
 520         { }
 521 };
 522
 523 MODULE_DEVICE_TABLE(pci, agp_serverworks_pci_table);
 524
 525 static struct pci_driver agp_serverworks_pci_driver = {
 526         .name           = "agpgart-serverworks",
 527         .id_table       = agp_serverworks_pci_table,
 528         .probe          = agp_serverworks_probe,
 529         .remove         = agp_serverworks_remove,
 530 };
 531
 532 static int __init agp_serverworks_init(void)
 533 {
 534         return pci_module_init(&agp_serverworks_pci_driver);
 535 }
 536
 537 static void __exit agp_serverworks_cleanup(void)
 538 {
 539         pci_unregister_driver(&agp_serverworks_pci_driver);
 540 }
 541
 542 module_init(agp_serverworks_init);
 543 module_exit(agp_serverworks_cleanup);
 544
 545 MODULE_PARM(agp_try_unsupported, "1i");
 546 MODULE_LICENSE("GPL and additional rights");
 547