2 * linux/arch/alpha/kernel/pci.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
9 /* 2.3.x PCI/resources, 1999 Andrea Arcangeli <andrea@suse.de> */
11 #include <linux/string.h>
12 #include <linux/pci.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/kernel.h>
16 #include <linux/bootmem.h>
17 #include <asm/machvec.h>
24 * Some string constants used by the various core logics.
27 const char *const pci_io_names
[] = {
28 "PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3",
29 "PCI IO bus 4", "PCI IO bus 5", "PCI IO bus 6", "PCI IO bus 7"
32 const char *const pci_mem_names
[] = {
33 "PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3",
34 "PCI mem bus 4", "PCI mem bus 5", "PCI mem bus 6", "PCI mem bus 7"
37 const char pci_hae0_name
[] = "HAE0";
41 * The PCI controler list.
44 struct pci_controler
*hose_head
, **hose_tail
= &hose_head
;
45 struct pci_controler
*pci_isa_hose
;
52 quirk_eisa_bridge(struct pci_dev
*dev
)
54 dev
->class = PCI_CLASS_BRIDGE_EISA
;
58 quirk_isa_bridge(struct pci_dev
*dev
)
60 dev
->class = PCI_CLASS_BRIDGE_ISA
;
64 quirk_ali_ide_ports(struct pci_dev
*dev
)
66 if (dev
->resource
[0].end
== 0xffff)
67 dev
->resource
[0].end
= dev
->resource
[0].start
+ 7;
68 if (dev
->resource
[2].end
== 0xffff)
69 dev
->resource
[2].end
= dev
->resource
[2].start
+ 7;
70 if (dev
->resource
[3].end
== 0xffff)
71 dev
->resource
[3].end
= dev
->resource
[3].start
+ 7;
75 quirk_vga_enable_rom(struct pci_dev
*dev
)
77 /* If it's a VGA, enable its BIOS ROM at C0000.
78 But if its a Cirrus 543x/544x DISABLE it, since
79 enabling ROM disables the memory... */
80 if ((dev
->class >> 8) == PCI_CLASS_DISPLAY_VGA
&&
81 /* But if its a Cirrus 543x/544x DISABLE it */
82 (dev
->vendor
!= PCI_VENDOR_ID_CIRRUS
||
83 (dev
->device
< 0x00a0) || (dev
->device
> 0x00ac)))
87 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
88 reg
|= PCI_ROM_ADDRESS_ENABLE
;
89 pci_write_config_dword(dev
, dev
->rom_base_reg
, reg
);
90 dev
->resource
[PCI_ROM_RESOURCE
].flags
|= PCI_ROM_ADDRESS_ENABLE
;
94 struct pci_fixup pcibios_fixups
[] __initdata
= {
95 { PCI_FIXUP_HEADER
, PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82375
,
97 { PCI_FIXUP_HEADER
, PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82378
,
99 { PCI_FIXUP_HEADER
, PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M5229
,
100 quirk_ali_ide_ports
},
101 { PCI_FIXUP_FINAL
, PCI_ANY_ID
, PCI_ANY_ID
, quirk_vga_enable_rom
},
105 #define MAX(val1, val2) ((val1) > (val2) ? (val1) : (val2))
106 #define ALIGN(val,align) (((val) + ((align) - 1)) & ~((align) - 1))
112 pcibios_align_resource(void *data
, struct resource
*res
, unsigned long size
)
114 struct pci_dev
*dev
= data
;
115 struct pci_controler
*hose
= dev
->sysdata
;
116 unsigned long alignto
;
117 unsigned long start
= res
->start
;
119 if (res
->flags
& IORESOURCE_IO
) {
120 /* Make sure we start at our min on all hoses */
121 if (start
- hose
->io_space
->start
< PCIBIOS_MIN_IO
)
122 start
= PCIBIOS_MIN_IO
+ hose
->io_space
->start
;
125 * Aligning to 0x800 rather than the minimum base of
126 * 0x400 is an attempt to avoid having devices in
127 * any 0x?C?? range, which is where the de4x5 driver
128 * probes for EISA cards.
130 * Adaptecs, especially, resent such intrusions.
132 * The de4x5 driver has the eisa probe conditionalized
133 * out for Alpha, so lower the minimum base back to 0x400.
135 alignto
= MAX(0x400, size
);
136 start
= ALIGN(start
, alignto
);
138 else if (res
->flags
& IORESOURCE_MEM
) {
139 /* Make sure we start at our min on all hoses */
140 if (start
- hose
->mem_space
->start
< PCIBIOS_MIN_MEM
)
141 start
= PCIBIOS_MIN_MEM
+ hose
->io_space
->start
;
144 * The following holds at least for the Low Cost
145 * Alpha implementation of the PCI interface:
147 * In sparse memory address space, the first
148 * octant (16MB) of every 128MB segment is
149 * aliased to the very first 16 MB of the
150 * address space (i.e., it aliases the ISA
151 * memory address space). Thus, we try to
152 * avoid allocating PCI devices in that range.
153 * Can be allocated in 2nd-7th octant only.
154 * Devices that need more than 112MB of
155 * address space must be accessed through
156 * dense memory space only!
159 /* Align to multiple of size of minimum base. */
160 alignto
= MAX(0x1000, size
);
161 start
= ALIGN(start
, alignto
);
162 if (size
<= 7 * 16*MB
) {
163 if (((start
/ (16*MB
)) & 0x7) == 0) {
164 start
&= ~(128*MB
- 1);
166 start
= ALIGN(start
, alignto
);
168 if (start
/(128*MB
) != (start
+ size
)/(128*MB
)) {
169 start
&= ~(128*MB
- 1);
170 start
+= (128 + 16)*MB
;
171 start
= ALIGN(start
, alignto
);
185 * Pre-layout host-independant device initialization.
189 pcibios_assign_special(struct pci_dev
* dev
)
193 /* The first three resources of an IDE controler are often magic,
194 so leave them unchanged. This is true, for instance, of the
195 Contaq 82C693 as seen on SX164 and DP264. */
197 if (dev
->class >> 8 == PCI_CLASS_STORAGE_IDE
) {
198 /* Resource 1 of IDE controller is the address of HD_CMD
199 register which actually occupies a single byte (0x3f6
200 for ide0) in reported 0x3f4-3f7 range. We have to fix
201 that to avoid resource conflict with AT-style floppy
203 dev
->resource
[1].start
+= 2;
204 dev
->resource
[1].end
= dev
->resource
[1].start
;
205 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
206 if (dev
->resource
[i
].flags
&& dev
->resource
[i
].start
)
207 pci_claim_resource(dev
, i
);
210 * We don't have code that will init the CYPRESS bridge correctly
211 * so we do the next best thing, and depend on the previous
212 * console code to do the right thing, and ignore it here... :-\
214 else if (dev
->vendor
== PCI_VENDOR_ID_CONTAQ
&&
215 dev
->device
== PCI_DEVICE_ID_CONTAQ_82C693
)
216 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
217 if (dev
->resource
[i
].flags
&& dev
->resource
[i
].start
)
218 pci_claim_resource(dev
, i
);
225 if (!alpha_mv
.init_pci
)
231 pcibios_setup(char *str
)
237 pcibios_fixup_resource(struct resource
*res
, struct resource
*root
)
239 res
->start
+= root
->start
;
240 res
->end
+= root
->start
;
244 pcibios_fixup_device_resources(struct pci_dev
*dev
, struct pci_bus
*bus
)
246 /* Update device resources. */
247 struct pci_controler
*hose
= (struct pci_controler
*)bus
->sysdata
;
250 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
251 if (!dev
->resource
[i
].start
)
253 if (dev
->resource
[i
].flags
& IORESOURCE_IO
)
254 pcibios_fixup_resource(&dev
->resource
[i
],
256 else if (dev
->resource
[i
].flags
& IORESOURCE_MEM
)
257 pcibios_fixup_resource(&dev
->resource
[i
],
260 pcibios_assign_special(dev
);
264 pcibios_fixup_bus(struct pci_bus
*bus
)
266 /* Propogate hose info into the subordinate devices. */
268 struct pci_controler
*hose
= (struct pci_controler
*) bus
->sysdata
;
269 struct list_head
*ln
;
272 bus
->resource
[0] = hose
->io_space
;
273 bus
->resource
[1] = hose
->mem_space
;
275 /* If this is a bridge, get the current bases */
277 pci_read_bridge_bases(bus
);
278 pcibios_fixup_device_resources(bus
->self
, bus
->parent
);
281 for (ln
= bus
->devices
.next
; ln
!= &bus
->devices
; ln
= ln
->next
) {
282 struct pci_dev
*dev
= pci_dev_b(ln
);
283 if ((dev
->class >> 8) != PCI_CLASS_BRIDGE_PCI
)
284 pcibios_fixup_device_resources(dev
, bus
);
289 pcibios_update_resource(struct pci_dev
*dev
, struct resource
*root
,
290 struct resource
*res
, int resource
)
292 struct pci_controler
*hose
= dev
->sysdata
;
296 if (resource
< PCI_ROM_RESOURCE
)
297 where
= PCI_BASE_ADDRESS_0
+ (resource
* 4);
298 else if (resource
== PCI_ROM_RESOURCE
)
299 where
= dev
->rom_base_reg
;
301 return; /* Don't update non-standard resources here. */
304 /* Point root at the hose root. */
305 if (res
->flags
& IORESOURCE_IO
)
306 root
= hose
->io_space
;
307 if (res
->flags
& IORESOURCE_MEM
)
308 root
= hose
->mem_space
;
310 reg
= (res
->start
- root
->start
) | (res
->flags
& 0xf);
311 pci_write_config_dword(dev
, where
, reg
);
312 if ((res
->flags
& (PCI_BASE_ADDRESS_SPACE
313 | PCI_BASE_ADDRESS_MEM_TYPE_MASK
))
314 == (PCI_BASE_ADDRESS_SPACE_MEMORY
315 | PCI_BASE_ADDRESS_MEM_TYPE_64
)) {
316 pci_write_config_dword(dev
, where
+4, 0);
317 printk(KERN_WARNING
"PCI: dev %s type 64-bit\n", dev
->name
);
320 /* ??? FIXME -- record old value for shutdown. */
324 pcibios_update_irq(struct pci_dev
*dev
, int irq
)
326 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, irq
);
328 /* ??? FIXME -- record old value for shutdown. */
331 /* Most Alphas have straight-forward swizzling needs. */
334 common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
336 struct pci_controler
*hose
= dev
->sysdata
;
338 if (dev
->bus
->number
!= hose
->first_busno
) {
341 pin
= bridge_swizzle(pin
, PCI_SLOT(dev
->devfn
));
342 /* Move up the chain of bridges. */
343 dev
= dev
->bus
->self
;
344 } while (dev
->bus
->self
);
347 /* The slot is the slot of the last bridge. */
350 return PCI_SLOT(dev
->devfn
);
354 pcibios_fixup_pbus_ranges(struct pci_bus
* bus
,
355 struct pbus_set_ranges_data
* ranges
)
357 struct pci_controler
*hose
= (struct pci_controler
*)bus
->sysdata
;
359 ranges
->io_start
-= hose
->io_space
->start
;
360 ranges
->io_end
-= hose
->io_space
->start
;
361 ranges
->mem_start
-= hose
->mem_space
->start
;
362 ranges
->mem_end
-= hose
->mem_space
->start
;
366 pcibios_enable_device(struct pci_dev
*dev
)
368 /* Nothing to do, since we enable all devices at startup. */
373 * If we set up a device for bus mastering, we need to check the latency
374 * timer as certain firmware forgets to set it properly, as seen
375 * on SX164 and LX164 with SRM.
378 pcibios_set_master(struct pci_dev
*dev
)
381 pci_read_config_byte(dev
, PCI_LATENCY_TIMER
, &lat
);
382 if (lat
>= 16) return;
383 printk("PCI: Setting latency timer of device %s to 64\n",
385 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 64);
388 #define ROUND_UP(x, a) (((x) + (a) - 1) & ~((a) - 1))
391 pcibios_size_bridge(struct pci_bus
*bus
, struct pbus_set_ranges_data
*outer
)
393 struct pbus_set_ranges_data inner
;
395 struct pci_dev
*bridge
= bus
->self
;
396 struct pci_controler
*hose
= bus
->sysdata
;
397 struct list_head
*ln
;
400 return; /* host bridge, nothing to do */
402 /* set reasonable default locations for pcibios_align_resource */
403 inner
.io_start
= hose
->io_space
->start
+ PCIBIOS_MIN_IO
;
404 inner
.mem_start
= hose
->mem_space
->start
+ PCIBIOS_MIN_MEM
;
405 inner
.io_end
= inner
.io_start
;
406 inner
.mem_end
= inner
.mem_start
;
408 /* Collect information about how our direct children are layed out. */
409 for (ln
=bus
->devices
.next
; ln
!= &bus
->devices
; ln
=ln
->next
) {
413 /* Skip bridges for now */
414 if (dev
->class >> 8 == PCI_CLASS_BRIDGE_PCI
)
417 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
421 memcpy(&res
, &dev
->resource
[i
], sizeof(res
));
422 size
= res
.end
- res
.start
+ 1;
424 if (res
.flags
& IORESOURCE_IO
) {
425 res
.start
= inner
.io_end
;
426 pcibios_align_resource(dev
, &res
, size
);
427 inner
.io_end
= res
.start
+ size
;
428 } else if (res
.flags
& IORESOURCE_MEM
) {
429 res
.start
= inner
.mem_end
;
430 pcibios_align_resource(dev
, &res
, size
);
431 inner
.mem_end
= res
.start
+ size
;
436 /* And for all of the subordinate busses. */
437 for (ln
=bus
->children
.next
; ln
!= &bus
->children
; ln
=ln
->next
)
438 pcibios_size_bridge(pci_bus_b(ln
), &inner
);
440 /* turn the ending locations into sizes (subtract start) */
441 inner
.io_end
-= inner
.io_start
;
442 inner
.mem_end
-= inner
.mem_start
;
444 /* Align the sizes up by bridge rules */
445 inner
.io_end
= ROUND_UP(inner
.io_end
, 4*1024) - 1;
446 inner
.mem_end
= ROUND_UP(inner
.mem_end
, 1*1024*1024) - 1;
448 /* Adjust the bridge's allocation requirements */
449 bridge
->resource
[0].end
= bridge
->resource
[0].start
+ inner
.io_end
;
450 bridge
->resource
[1].end
= bridge
->resource
[1].start
+ inner
.mem_end
;
452 bridge
->resource
[PCI_BRIDGE_RESOURCES
].end
=
453 bridge
->resource
[PCI_BRIDGE_RESOURCES
].start
+ inner
.io_end
;
454 bridge
->resource
[PCI_BRIDGE_RESOURCES
+1].end
=
455 bridge
->resource
[PCI_BRIDGE_RESOURCES
+1].start
+ inner
.mem_end
;
457 /* adjust parent's resource requirements */
459 outer
->io_end
= ROUND_UP(outer
->io_end
, 4*1024);
460 outer
->io_end
+= inner
.io_end
;
462 outer
->mem_end
= ROUND_UP(outer
->mem_end
, 1*1024*1024);
463 outer
->mem_end
+= inner
.mem_end
;
470 pcibios_size_bridges(void)
472 struct list_head
*ln1
, *ln2
;
474 for(ln1
=pci_root_buses
.next
; ln1
!= &pci_root_buses
; ln1
=ln1
->next
)
475 for(ln2
= pci_bus_b(ln1
)->children
.next
;
476 ln2
!= &pci_bus_b(ln1
)->children
;
478 pcibios_size_bridge(pci_bus_b(ln2
), NULL
);
482 common_init_pci(void)
484 struct pci_controler
*hose
;
488 /* Scan all of the recorded PCI controlers. */
489 for (next_busno
= 0, hose
= hose_head
; hose
; hose
= hose
->next
) {
490 hose
->first_busno
= next_busno
;
491 hose
->last_busno
= 0xff;
492 bus
= pci_scan_bus(next_busno
, alpha_mv
.pci_ops
, hose
);
494 next_busno
= hose
->last_busno
= bus
->subordinate
;
498 pcibios_size_bridges();
499 pci_assign_unassigned_resources();
500 pci_fixup_irqs(alpha_mv
.pci_swizzle
, alpha_mv
.pci_map_irq
);
501 pci_set_bus_ranges();
505 struct pci_controler
* __init
506 alloc_pci_controler(void)
508 struct pci_controler
*hose
;
510 hose
= alloc_bootmem(sizeof(*hose
));
513 hose_tail
= &hose
->next
;
518 struct resource
* __init
521 struct resource
*res
;
523 res
= alloc_bootmem(sizeof(*res
));
529 /* Provide information on locations of various I/O regions in physical
530 memory. Do this on a per-card basis so that we choose the right hose. */
533 sys_pciconfig_iobase(long which
, unsigned long bus
, unsigned long dfn
)
535 struct pci_controler
*hose
;
538 /* from hose or from bus.devfn */
539 if (which
& IOBASE_FROM_HOSE
) {
540 for(hose
= hose_head
; hose
; hose
= hose
->next
)
541 if (hose
->index
== bus
) break;
542 if (!hose
) return -ENODEV
;
544 /* Special hook for ISA access. */
545 if (bus
== 0 && dfn
== 0) {
548 dev
= pci_find_slot(bus
, dfn
);
555 switch (which
& ~IOBASE_FROM_HOSE
) {
558 case IOBASE_SPARSE_MEM
:
559 return hose
->sparse_mem_base
;
560 case IOBASE_DENSE_MEM
:
561 return hose
->dense_mem_base
;
562 case IOBASE_SPARSE_IO
:
563 return hose
->sparse_io_base
;
564 case IOBASE_DENSE_IO
:
565 return hose
->dense_io_base
;
566 case IOBASE_ROOT_BUS
:
567 return hose
->bus
->number
;