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Merge with Linux 2.4.0-test5-pre3.
[linux-2.6/linux-mips.git] / arch / alpha / kernel / core_titan.c
blob5e53d091ca37a29d2df3f5db83216f8e8e54812f
1 /*
2 * linux/arch/alpha/kernel/core_titan.c
3 *
4 * Code common to all TITAN core logic chips.
5 */
6
7 #include <linux/config.h>
8 #include <linux/kernel.h>
9 #include <linux/types.h>
10 #include <linux/pci.h>
11 #include <linux/sched.h>
12 #include <linux/init.h>
13
14 #include <asm/ptrace.h>
15 #include <asm/system.h>
16 #include <asm/smp.h>
17
18 #define __EXTERN_INLINE inline
19 #include <asm/io.h>
20 #include <asm/core_titan.h>
21 #undef __EXTERN_INLINE
22
23 #include "proto.h"
24 #include "pci_impl.h"
25
26 unsigned TITAN_agp = 0;
27
28 static struct
29 {
30 unsigned long wsba[4];
31 unsigned long wsm[4];
32 unsigned long tba[4];
33 } saved_pachip_port[4];
34
35 /*
36 * BIOS32-style PCI interface:
37 */
38
39 #define DEBUG_MCHECK 0 /* 0 = minimum, 1 = debug, 2 = dump+dump */
40 #define DEBUG_CONFIG 0
41
42 #if DEBUG_CONFIG
43 # define DBG_CFG(args) printk args
44 #else
45 # define DBG_CFG(args)
46 #endif
47
48 /*
49 * Given a bus, device, and function number, compute resulting
50 * configuration space address
51 * accordingly. It is therefore not safe to have concurrent
52 * invocations to configuration space access routines, but there
53 * really shouldn't be any need for this.
54 *
55 * Note that all config space accesses use Type 1 address format.
56 *
57 * Note also that type 1 is determined by non-zero bus number.
58 *
59 * Type 1:
60 *
61 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
62 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
63 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
64 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
65 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
66 *
67 * 31:24 reserved
68 * 23:16 bus number (8 bits = 128 possible buses)
69 * 15:11 Device number (5 bits)
70 * 10:8 function number
71 * 7:2 register number
72 *
73 * Notes:
74 * The function number selects which function of a multi-function device
75 * (e.g., SCSI and Ethernet).
76 *
77 * The register selects a DWORD (32 bit) register offset. Hence it
78 * doesn't get shifted by 2 bits as we want to "drop" the bottom two
79 * bits.
80 */
81
82 static int
83 mk_conf_addr(struct pci_dev *dev, int where, unsigned long *pci_addr,
84 unsigned char *type1)
85 {
86 struct pci_controler *hose = dev->sysdata;
87 unsigned long addr;
88 u8 bus = dev->bus->number;
89 u8 device_fn = dev->devfn;
90
91 DBG_CFG(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x, "
92 "pci_addr=0x%p, type1=0x%p)\n",
93 bus, device_fn, where, pci_addr, type1));
94
95 if (hose->first_busno == dev->bus->number)
96 bus = 0;
97 *type1 = (bus != 0);
98
99 addr = (bus << 16) | (device_fn << 8) | where;
100 addr |= hose->config_space_base;
101
102 *pci_addr = addr;
103 DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
104 return 0;
105 }
106
107 static int
108 titan_read_config_byte(struct pci_dev *dev, int where, u8 *value)
109 {
110 unsigned long addr;
111 unsigned char type1;
112
113 if (mk_conf_addr(dev, where, &addr, &type1))
114 return PCIBIOS_DEVICE_NOT_FOUND;
115
116 *value = __kernel_ldbu(*(vucp)addr);
117 return PCIBIOS_SUCCESSFUL;
118 }
119
120 static int
121 titan_read_config_word(struct pci_dev *dev, int where, u16 *value)
122 {
123 unsigned long addr;
124 unsigned char type1;
125
126 if (mk_conf_addr(dev, where, &addr, &type1))
127 return PCIBIOS_DEVICE_NOT_FOUND;
128
129 *value = __kernel_ldwu(*(vusp)addr);
130 return PCIBIOS_SUCCESSFUL;
131 }
132
133 static int
134 titan_read_config_dword(struct pci_dev *dev, int where, u32 *value)
135 {
136 unsigned long addr;
137 unsigned char type1;
138
139 if (mk_conf_addr(dev, where, &addr, &type1))
140 return PCIBIOS_DEVICE_NOT_FOUND;
141
142 *value = *(vuip)addr;
143 return PCIBIOS_SUCCESSFUL;
144 }
145
146 static int
147 titan_write_config_byte(struct pci_dev *dev, int where, u8 value)
148 {
149 unsigned long addr;
150 unsigned char type1;
151
152 if (mk_conf_addr(dev, where, &addr, &type1))
153 return PCIBIOS_DEVICE_NOT_FOUND;
154
155 __kernel_stb(value, *(vucp)addr);
156 mb();
157 __kernel_ldbu(*(vucp)addr);
158 return PCIBIOS_SUCCESSFUL;
159 }
160
161 static int
162 titan_write_config_word(struct pci_dev *dev, int where, u16 value)
163 {
164 unsigned long addr;
165 unsigned char type1;
166
167 if (mk_conf_addr(dev, where, &addr, &type1))
168 return PCIBIOS_DEVICE_NOT_FOUND;
169
170 __kernel_stw(value, *(vusp)addr);
171 mb();
172 __kernel_ldwu(*(vusp)addr);
173 return PCIBIOS_SUCCESSFUL;
174 }
175
176 static int
177 titan_write_config_dword(struct pci_dev *dev, int where, u32 value)
178 {
179 unsigned long addr;
180 unsigned char type1;
181
182 if (mk_conf_addr(dev, where, &addr, &type1))
183 return PCIBIOS_DEVICE_NOT_FOUND;
184
185 *(vuip)addr = value;
186 mb();
187 *(vuip)addr;
188 return PCIBIOS_SUCCESSFUL;
189 }
190
191 struct pci_ops titan_pci_ops =
192 {
193 read_byte: titan_read_config_byte,
194 read_word: titan_read_config_word,
195 read_dword: titan_read_config_dword,
196 write_byte: titan_write_config_byte,
197 write_word: titan_write_config_word,
198 write_dword: titan_write_config_dword
199 };
200
201 \f
202 void
203 titan_pci_tbi(struct pci_controler *hose, dma_addr_t start, dma_addr_t end)
204 {
205 titan_pachip *pachip =
206 (hose->index & 1) ? TITAN_pachip1 : TITAN_pachip0;
207 titan_pachip_port *port;
208 volatile unsigned long *csr;
209 unsigned long value;
210
211 /* Get the right hose */
212 port = &pachip->g_port;
213 if (hose->index & 2)
214 port = &pachip->a_port;
215
216 /* We can invalidate up to 8 tlb entries in a go. The flush
217 matches against <31:16> in the pci address. */
218 csr = &port->port_specific.g.gtlbia.csr;
219 if (((start ^ end) & 0xffff0000) == 0)
220 csr = &port->port_specific.g.gtlbiv.csr;
221
222 /* For TBIA, it doesn't matter what value we write. For TBI,
223 it's the shifted tag bits. */
224 value = (start & 0xffff0000) >> 12;
225
226 wmb();
227 *csr = value;
228 mb();
229 *csr;
230 }
231
232 #define FN __FUNCTION__
233
234 static int __init
235 titan_query_agp(titan_pachip_port *port)
236 {
237 union TPAchipPCTL pctl;
238
239 /* set up APCTL */
240 pctl.pctl_q_whole = port->pctl.csr;
241
242 return pctl.pctl_r_bits.apctl_v_agp_present;
243
244 }
245 static void __init
246 titan_init_agp(titan_pachip_port *port, struct pci_controler *hose)
247 {
248 union TPAchipPCTL pctl;
249
250 if (!titan_query_agp(port))
251 return;
252
253 printk("AGP present on hose %d\n", hose->index);
254
255 /* get APCTL */
256 pctl.pctl_q_whole = port->pctl.csr;
257
258
259 pctl.pctl_r_bits.apctl_v_agp_en = 1; /* enable AGP */
260 pctl.pctl_r_bits.apctl_v_agp_lp_rd = 0;
261 pctl.pctl_r_bits.apctl_v_agp_hp_rd = 0;
262
263 port->pctl.csr = pctl.pctl_q_whole;
264
265 TITAN_agp |= 1 << hose->index;
266
267 #ifdef CONFIG_VGA_HOSE
268 /* is a graphics card on the AGP? (always device 5) */
269 if (hose != NULL &&
270 __kernel_ldwu(*(vusp)(hose->config_space_base + 0x280a)) ==
271 PCI_CLASS_DISPLAY_VGA)
272 set_vga_hose(hose);
273 #endif
274 }
275
276 static void __init
277 titan_init_one_pachip_port(titan_pachip_port *port, int index)
278 {
279 struct pci_controler *hose;
280
281 hose = alloc_pci_controler();
282 if (index == 0)
283 pci_isa_hose = hose;
284 hose->io_space = alloc_resource();
285 hose->mem_space = alloc_resource();
286
287 /* This is for userland consumption. For some reason, the 40-bit
288 PIO bias that we use in the kernel through KSEG didn't work for
289 the page table based user mappings. So make sure we get the
290 43-bit PIO bias. */
291 hose->sparse_mem_base = 0;
292 hose->sparse_io_base = 0;
293 hose->dense_mem_base
294 = (TITAN_MEM(index) & 0xffffffffff) | 0x80000000000;
295 hose->dense_io_base
296 = (TITAN_IO(index) & 0xffffffffff) | 0x80000000000;
297
298 hose->config_space_base = TITAN_CONF(index);
299 hose->index = index;
300
301 hose->io_space->start = TITAN_IO(index) - TITAN_IO_BIAS;
302 hose->io_space->end = hose->io_space->start + TITAN_IO_SPACE - 1;
303 hose->io_space->name = pci_io_names[index];
304 hose->io_space->flags = IORESOURCE_IO;
305
306 hose->mem_space->start = TITAN_MEM(index) - TITAN_MEM_BIAS;
307 hose->mem_space->end = hose->mem_space->start + 0xffffffff;
308 hose->mem_space->name = pci_mem_names[index];
309 hose->mem_space->flags = IORESOURCE_MEM;
310
311 if (request_resource(&ioport_resource, hose->io_space) < 0)
312 printk(KERN_ERR "Failed to request IO on hose %d\n", index);
313 if (request_resource(&iomem_resource, hose->mem_space) < 0)
314 printk(KERN_ERR "Failed to request MEM on hose %d\n", index);
315
316 /* It's safe to call this for both G-Ports and A-Ports */
317 titan_init_agp(port, hose);
318
319 /*
320 * Save the existing PCI window translations. SRM will
321 * need them when we go to reboot.
322 */
323 saved_pachip_port[index].wsba[0] = port->wsba[0].csr;
324 saved_pachip_port[index].wsm[0] = port->wsm[0].csr;
325 saved_pachip_port[index].tba[0] = port->tba[0].csr;
326
327 saved_pachip_port[index].wsba[1] = port->wsba[1].csr;
328 saved_pachip_port[index].wsm[1] = port->wsm[1].csr;
329 saved_pachip_port[index].tba[1] = port->tba[1].csr;
330
331 saved_pachip_port[index].wsba[2] = port->wsba[2].csr;
332 saved_pachip_port[index].wsm[2] = port->wsm[2].csr;
333 saved_pachip_port[index].tba[2] = port->tba[2].csr;
334
335 saved_pachip_port[index].wsba[3] = port->wsba[3].csr;
336 saved_pachip_port[index].wsm[3] = port->wsm[3].csr;
337 saved_pachip_port[index].tba[3] = port->tba[3].csr;
338
339 /*
340 * Set up the PCI to main memory translation windows.
341 *
342 * Note: Window 3 on Titan is Scatter-Gather ONLY
343 *
344 * Window 0 is scatter-gather 8MB at 8MB (for isa)
345 * Window 1 is direct access 1GB at 1GB
346 * Window 2 is direct access 1GB at 2GB
347 * Window 3 is scatter-gather 128MB at 3GB
348 * ??? We ought to scale window 3 memory.
349 *
350 * We must actually use 2 windows to direct-map the 2GB space,
351 * because of an idiot-syncrasy of the CYPRESS chip. It may
352 * respond to a PCI bus address in the last 1MB of the 4GB
353 * address range.
354 */
355 hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 0);
356 hose->sg_isa->align_entry = 8; /* 64KB for ISA */
357
358 hose->sg_pci = iommu_arena_new(hose, 0xc0000000, 0x08000000, 0);
359 hose->sg_pci->align_entry = 4; /* Titan caches 4 PTEs at a time */
360
361 __direct_map_base = 0x40000000;
362 __direct_map_size = 0x80000000;
363
364 port->wsba[0].csr = hose->sg_isa->dma_base | 3;
365 port->wsm[0].csr = (hose->sg_isa->size - 1) & 0xfff00000;
366 port->tba[0].csr = virt_to_phys(hose->sg_isa->ptes);
367
368 port->wsba[1].csr = 0x40000000 | 1;
369 port->wsm[1].csr = (0x40000000 - 1) & 0xfff00000;
370 port->tba[1].csr = 0;
371
372 port->wsba[2].csr = 0x80000000 | 1;
373 port->wsm[2].csr = (0x40000000 - 1) & 0xfff00000;
374 port->tba[2].csr = 0x40000000;
375
376 port->wsba[3].csr = hose->sg_pci->dma_base | 3;
377 port->wsm[3].csr = (hose->sg_pci->size - 1) & 0xfff00000;
378 port->tba[3].csr = virt_to_phys(hose->sg_pci->ptes);
379
380 titan_pci_tbi(hose, 0, -1);
381 }
382
383 static void __init
384 titan_init_pachips(titan_pachip *pachip0, titan_pachip *pachip1)
385 {
386 int pchip1_present = TITAN_cchip->csc.csr & 1L<<14;
387
388 /* Init the ports in hose order... */
389 titan_init_one_pachip_port(&pachip0->g_port, 0); /* hose 0 */
390 if (pchip1_present)
391 titan_init_one_pachip_port(&pachip1->g_port, 1);/* hose 1 */
392 titan_init_one_pachip_port(&pachip0->a_port, 2); /* hose 2 */
393 if (pchip1_present)
394 titan_init_one_pachip_port(&pachip1->a_port, 3);/* hose 3 */
395 }
396
397 void __init
398 titan_init_arch(void)
399 {
400 #if 0
401 printk("%s: titan_init_arch()\n", FN);
402 printk("%s: CChip registers:\n", FN);
403 printk("%s: CSR_CSC 0x%lx\n", FN, TITAN_cchip->csc.csr);
404 printk("%s: CSR_MTR 0x%lx\n", FN, TITAN_cchip->mtr.csr);
405 printk("%s: CSR_MISC 0x%lx\n", FN, TITAN_cchip->misc.csr);
406 printk("%s: CSR_DIM0 0x%lx\n", FN, TITAN_cchip->dim0.csr);
407 printk("%s: CSR_DIM1 0x%lx\n", FN, TITAN_cchip->dim1.csr);
408 printk("%s: CSR_DIR0 0x%lx\n", FN, TITAN_cchip->dir0.csr);
409 printk("%s: CSR_DIR1 0x%lx\n", FN, TITAN_cchip->dir1.csr);
410 printk("%s: CSR_DRIR 0x%lx\n", FN, TITAN_cchip->drir.csr);
411
412 printk("%s: DChip registers:\n", FN);
413 printk("%s: CSR_DSC 0x%lx\n", FN, TITAN_dchip->dsc.csr);
414 printk("%s: CSR_STR 0x%lx\n", FN, TITAN_dchip->str.csr);
415 printk("%s: CSR_DREV 0x%lx\n", FN, TITAN_dchip->drev.csr);
416 #endif
417
418 boot_cpuid = __hard_smp_processor_id();
419
420 /* With multiple PCI busses, we play with I/O as physical addrs. */
421 ioport_resource.end = ~0UL;
422 iomem_resource.end = ~0UL;
423
424 /* Init the PA chip(s) */
425 titan_init_pachips(TITAN_pachip0, TITAN_pachip1);
426 }
427
428 static void
429 titan_kill_one_pachip_port(titan_pachip_port *port, int index)
430 {
431 port->wsba[0].csr = saved_pachip_port[index].wsba[0];
432 port->wsm[0].csr = saved_pachip_port[index].wsm[0];
433 port->tba[0].csr = saved_pachip_port[index].tba[0];
434
435 port->wsba[1].csr = saved_pachip_port[index].wsba[1];
436 port->wsm[1].csr = saved_pachip_port[index].wsm[1];
437 port->tba[1].csr = saved_pachip_port[index].tba[1];
438
439 port->wsba[2].csr = saved_pachip_port[index].wsba[2];
440 port->wsm[2].csr = saved_pachip_port[index].wsm[2];
441 port->tba[2].csr = saved_pachip_port[index].tba[2];
442
443 port->wsba[3].csr = saved_pachip_port[index].wsba[3];
444 port->wsm[3].csr = saved_pachip_port[index].wsm[3];
445 port->tba[3].csr = saved_pachip_port[index].tba[3];
446 }
447
448 static void
449 titan_kill_pachips(titan_pachip *pachip0, titan_pachip *pachip1)
450 {
451 int pchip1_present = TITAN_cchip->csc.csr & 1L<<14;
452
453 if (pchip1_present) {
454 titan_kill_one_pachip_port(&pachip0->g_port, 1);
455 titan_kill_one_pachip_port(&pachip0->a_port, 3);
456 }
457 titan_kill_one_pachip_port(&pachip0->g_port, 0);
458 titan_kill_one_pachip_port(&pachip0->a_port, 2);
459 }
460
461 void
462 titan_kill_arch(int mode)
463 {
464 titan_kill_pachips(TITAN_pachip0, TITAN_pachip1);
465 }
466
467 static inline void
468 titan_pci_clr_err_1(titan_pachip *pachip)
469 {
470 unsigned int jd;
471
472 jd = pachip->g_port.port_specific.g.gperror.csr;
473 pachip->g_port.port_specific.g.gperror.csr = jd;
474 mb();
475 pachip->g_port.port_specific.g.gperror.csr;
476 }
477
478 static inline void
479 titan_pci_clr_err(void)
480 {
481 titan_pci_clr_err_1(TITAN_pachip0);
482
483 if (TITAN_cchip->csc.csr & 1L<<14)
484 titan_pci_clr_err_1(TITAN_pachip1);
485 }
486
487 void
488 titan_machine_check(unsigned long vector, unsigned long la_ptr,
489 struct pt_regs * regs)
490 {
491 /* clear error before any reporting. */
492 mb();
493 draina();
494 titan_pci_clr_err();
495 wrmces(0x7);
496 mb();
497
498 process_mcheck_info(vector, la_ptr, regs, "TITAN",
499 mcheck_expected(smp_processor_id()));
500 }
501
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